dri-devel April 2022

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[PATCH 11/11] dt-bindings: display: convert Arm Komeda to DT schema
by Andre Przywara 27 Apr '22

27 Apr '22

The Arm Komeda (aka Mali-D71) is a display controller that scans out a framebuffer and hands a signal to a digital encoder to generate a DVI or HDMI signal. It supports up to two pipelines, each frame can be composed of up to four layers. Convert the existing DT binding to DT schema. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- .../bindings/display/arm,komeda.txt | 78 ----------- .../bindings/display/arm,komeda.yaml | 130 ++++++++++++++++++ 2 files changed, 130 insertions(+), 78 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/arm,komeda.txt create mode 100644 Documentation/devicetree/bindings/display/arm,komeda.yaml diff --git a/Documentation/devicetree/bindings/display/arm,komeda.txt b/Documentation/devicetree/bindings/display/arm,komeda.txt deleted file mode 100644 index 8513695ee47fe..0000000000000 --- a/Documentation/devicetree/bindings/display/arm,komeda.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device Tree bindings for Arm Komeda display driver - -Required properties: -- compatible: Should be "arm,mali-d71" -- reg: Physical base address and length of the registers in the system -- interrupts: the interrupt line number of the device in the system -- clocks: A list of phandle + clock-specifier pairs, one for each entry - in 'clock-names' -- clock-names: A list of clock names. It should contain: - - "aclk": for the main processor clock -- #address-cells: Must be 1 -- #size-cells: Must be 0 -- iommus: configure the stream id to IOMMU, Must be configured if want to - enable iommu in display. for how to configure this node please reference - devicetree/bindings/iommu/arm,smmu-v3.txt, - devicetree/bindings/iommu/iommu.txt - -Required properties for sub-node: pipeline@nq -Each device contains one or two pipeline sub-nodes (at least one), each -pipeline node should provide properties: -- reg: Zero-indexed identifier for the pipeline -- clocks: A list of phandle + clock-specifier pairs, one for each entry - in 'clock-names' -- clock-names: should contain: - - "pxclk": pixel clock - -- port: each pipeline connect to an encoder input port. The connection is - modeled using the OF graph bindings specified in - Documentation/devicetree/bindings/graph.txt - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for the framebuffer; if not present, the framebuffer may - be located anywhere in memory. - -Example: -/ { - ... - - dp0: display@c00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "arm,mali-d71"; - reg = <0xc00000 0x20000>; - interrupts = <0 168 4>; - clocks = <&dpu_aclk>; - clock-names = "aclk"; - iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, - <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, - <&smmu 8>, <&smmu 9>; - - dp0_pipe0: pipeline@0 { - clocks = <&fpgaosc2>; - clock-names = "pxclk"; - reg = <0>; - - port { - dp0_pipe0_out: endpoint { - remote-endpoint = <&db_dvi0_in>; - }; - }; - }; - - dp0_pipe1: pipeline@1 { - clocks = <&fpgaosc2>; - clock-names = "pxclk"; - reg = <1>; - - port { - dp0_pipe1_out: endpoint { - remote-endpoint = <&db_dvi1_in>; - }; - }; - }; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/display/arm,komeda.yaml b/Documentation/devicetree/bindings/display/arm,komeda.yaml new file mode 100644 index 0000000000000..c619a0acfb307 --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm,komeda.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/arm,komeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Komeda display processor + +maintainers: + - Liviu Dudau <Liviu.Dudau(a)arm.com> + - Andre Przywara <andre.przywara(a)arm.com> + +description: |+ + The Arm Mali D71 display processor supports up to two displays with up + to a 4K resolution each. Each pipeline can be composed of up to four + layers. It is typically connected to a digital display connector like HDMI. + +properties: + compatible: + oneOf: + - items: + - const: arm,mali-d32 + - const: arm,mali-d71 + - const: arm,mali-d71 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + const: aclk + + clocks: + maxItems: 1 + description: The main DPU processor clock + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + memory-region: + maxItems: 1 + description: + Phandle to a node describing memory to be used for the framebuffer. + If not present, the framebuffer may be located anywhere in memory. + + iommus: + description: + The stream IDs for each of the used pipelines, each four IDs for the + four layers, plus one for the write-back stream. + minItems: 5 + maxItems: 10 + +patternProperties: + '^pipeline@[01]$': + type: object + description: + clocks + + properties: + reg: + enum: [ 0, 1 ] + + clock-names: + const: pxclk + + clocks: + maxItems: 1 + description: The input reference for the pixel clock. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + +additionalProperties: false + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + - interrupts + - clock-names + - clocks + - pipeline@0 + +examples: + - | + display@c00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,mali-d71"; + reg = <0xc00000 0x20000>; + interrupts = <168>; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, + <&smmu 8>, + <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, + <&smmu 9>; + + dp0_pipe0: pipeline@0 { + clocks = <&fpgaosc2>; + clock-names = "pxclk"; + reg = <0>; + + port { + dp0_pipe0_out: endpoint { + remote-endpoint = <&db_dvi0_in>; + }; + }; + }; + + dp0_pipe1: pipeline@1 { + clocks = <&fpgaosc2>; + clock-names = "pxclk"; + reg = <1>; + + port { + dp0_pipe1_out: endpoint { + remote-endpoint = <&db_dvi1_in>; + }; + }; + }; + }; +... -- 2.25.1

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[PATCH 08/11] dt-bindings: display: convert PL110/PL111 to DT schema
by Andre Przywara 27 Apr '22

27 Apr '22

The Arm PL110 and PL111 are IP blocks that provide a display engine with an LCD interface, being able to drive a variety of LC panels. Convert the binding over to DT schema, to the DTs can be automatically checked. This still contains the deprecated "arm,pl11x,tft-r0g0b0-pads" property, because this is used by several DTs in the tree. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- .../devicetree/bindings/display/arm,pl11x.txt | 110 ----------- .../bindings/display/arm,pl11x.yaml | 174 ++++++++++++++++++ 2 files changed, 174 insertions(+), 110 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/arm,pl11x.txt create mode 100644 Documentation/devicetree/bindings/display/arm,pl11x.yaml diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.txt b/Documentation/devicetree/bindings/display/arm,pl11x.txt deleted file mode 100644 index 3f977e72a2005..0000000000000 --- a/Documentation/devicetree/bindings/display/arm,pl11x.txt +++ /dev/null @@ -1,110 +0,0 @@ -* ARM PrimeCell Color LCD Controller PL110/PL111 - -See also Documentation/devicetree/bindings/arm/primecell.yaml - -Required properties: - -- compatible: must be one of: - "arm,pl110", "arm,primecell" - "arm,pl111", "arm,primecell" - -- reg: base address and size of the control registers block - -- interrupt-names: either the single entry "combined" representing a - combined interrupt output (CLCDINTR), or the four entries - "mbe", "vcomp", "lnbu", "fuf" representing the individual - CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts - -- interrupts: contains an interrupt specifier for each entry in - interrupt-names - -- clock-names: should contain "clcdclk" and "apb_pclk" - -- clocks: contains phandle and clock specifier pairs for the entries - in the clock-names property. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - -Optional properties: - -- memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for the framebuffer; if not present, the framebuffer - may be located anywhere in the memory - -- max-memory-bandwidth: maximum bandwidth in bytes per second that the - cell's memory interface can handle; if not present, the memory - interface is fast enough to handle all possible video modes - -Required sub-nodes: - -- port: describes LCD panel signals, following the common binding - for video transmitter interfaces; see - Documentation/devicetree/bindings/media/video-interfaces.txt - -Deprecated properties: - The port's endbpoint subnode had this, now deprecated property - in the past. Drivers should be able to survive without it: - - - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, - defining the way CLD pads are wired up; first value - contains index of the "CLD" external pin (pad) used - as R0 (first bit of the red component), second value - index of the pad used as G0, third value index of the - pad used as B0, see also "LCD panel signal multiplexing - details" paragraphs in the PL110/PL111 Technical - Reference Manuals; this implicitly defines available - color modes, for example: - - PL111 TFT 4:4:4 panel: - arm,pl11x,tft-r0g0b0-pads = <4 15 20>; - - PL110 TFT (1:)5:5:5 panel: - arm,pl11x,tft-r0g0b0-pads = <1 7 13>; - - PL111 TFT (1:)5:5:5 panel: - arm,pl11x,tft-r0g0b0-pads = <3 11 19>; - - PL111 TFT 5:6:5 panel: - arm,pl11x,tft-r0g0b0-pads = <3 10 19>; - - PL110 and PL111 TFT 8:8:8 panel: - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: - arm,pl11x,tft-r0g0b0-pads = <16 8 0>; - - -Example: - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupt-names = "combined"; - interrupts = <0 44 4>; - clocks = <&oscclk1>, <&oscclk2>; - clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ - - port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; - }; - }; - - }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/arm,pl11x.yaml b/Documentation/devicetree/bindings/display/arm,pl11x.yaml new file mode 100644 index 0000000000000..43b86c2827723 --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm,pl11x.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/arm,pl11x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm PrimeCell Color LCD Controller PL110/PL111 + +maintainers: + - Liviu Dudau <Liviu.Dudau(a)arm.com> + - Andre Przywara <andre.przywara(a)arm.com> + +description: |+ + The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out + a framebuffer region in system memory, and creates timed signals for + a variety of LCD panels. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + enum: + - arm,pl110 + - arm,pl111 + required: + - compatible + +properties: + compatible: + items: + - enum: + - arm,pl110 + - arm,pl111 + - const: arm,primecell + + reg: + maxItems: 1 + + interrupt-names: + oneOf: + - const: combined + description: + The IP provides four individual interrupt lines, but also one + combined line. If the integration only connects this line to the + interrupt controller, this single interrupt is noted here. + - items: + - const: mbe # CLCDMBEINTR + - const: vcomp # CLCDVCOMPINTR + - const: lnbu # CLCDLNBUINTR + - const: fuf # CLCDFUFINTR + + interrupts: + minItems: 1 + maxItems: 4 + + clock-names: + items: + - const: clcdclk + - const: apb_pclk + + clocks: + items: + - description: The CLCDCLK reference clock for the controller. + - description: The HCLK AHB slave clock for the register access. + + memory-region: + maxItems: 1 + description: + Phandle to a node describing memory to be used for the framebuffer. + If not present, the framebuffer may be located anywhere in memory. + + max-memory-bandwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum bandwidth in bytes per second that the cell's memory interface + can handle. + If not present, the memory interface is fast enough to handle all + possible video modes. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + description: + Output endpoint of the controller, connecting the LCD panel signals. + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + arm,pl11x,tft-r0g0b0-pads: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: index of CLD pad used for first red bit (R0) + - description: index of CLD pad used for first green bit (G0) + - description: index of CLD pad used for first blue bit (G0) + deprecated: true + description: | + DEPRECATED. An array of three 32-bit values, defining the way + CLD[23:0] pads are wired up. + The first value contains the index of the "CLD" external pin (pad) + used as R0 (first bit of the red component), the second value for + green, the third value for blue. + See also "LCD panel signal multiplexing details" paragraphs in the + PL110/PL111 Technical Reference Manuals. + This implicitly defines available color modes, for example: + - PL111 TFT 4:4:4 panel: + arm,pl11x,tft-r0g0b0-pads = <4 15 20>; + - PL110 TFT (1:)5:5:5 panel: + arm,pl11x,tft-r0g0b0-pads = <1 7 13>; + - PL111 TFT (1:)5:5:5 panel: + arm,pl11x,tft-r0g0b0-pads = <3 11 19>; + - PL111 TFT 5:6:5 panel: + arm,pl11x,tft-r0g0b0-pads = <3 10 19>; + - PL110 and PL111 TFT 8:8:8 panel: + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: + arm,pl11x,tft-r0g0b0-pads = <16 8 0>; + +additionalProperties: false + +required: + - compatible + - reg + - interrupt-names + - interrupts + - clock-names + - clocks + - port + +examples: + - | + clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + interrupts = <44>; + clocks = <&oscclk1>, <&oscclk2>; + clock-names = "clcdclk", "apb_pclk"; + max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + }; + }; + }; + + panel { + compatible = "arm,rtsm-display", "panel-dpi"; + power-supply = <&vcc_supply>; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; +... -- 2.25.1

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[PULL] drm-intel-gt-next
by Tvrtko Ursulin 27 Apr '22

27 Apr '22

Hi Dave, Daniel, Here goes the first drm-intel-gt-next PR towards 5.19. A lot of stuff here across the board in terms of new features, new platform support and bug fixes. For bug fixes the most interesting are: * a fix for out of bounds kernel access in mmap ops due incorrect object bound checking; * a fix for a GPU hang triggered by usage, of multiple media engines on Tigerlake and above; * correcting the sequence for doing engine resets on Tigerlake; * fix for split frame workloads in GuC mode; * fix for mmap of prime imported local memory objects; * fix for a VM refcounting bug; * fix fbdev setup to avoid potential out of bounds access. Another two nice user visible improvements are one in frame buffer pinning logic which enables Weston to reach 60fps on 8K displays and resurrection of the ability to monitor per client GPU usage using intel_gpu_top (consuming data exported via proc fdinfo). The latter contains a common DRM format specification and is hopeful of gaining more wide spread adoption in the future. GuC backend has finally achieved feature parity in terms of being able to provide error capture state after GPU hangs. The captured data is compatible with existing error parsing tools (IGT and Mesa) and also contains a new GuC log segment which does not currently have an open source parser. Also in the GuC area there was a bunch of refactoring to prepare for new firmware API and also lay the ground work for supporting new platforms like DG2. For the latter a buch of GuC based workarounds were added, together with support for small PCI BAR setups, eviction of compressed objects and general platform bring-up like code refactoring to deal with steered register writes. DG2 also needs two new bits of UAPI. One is the hwconfig query which is a new way of obtaining a binary table describing the GPU configuration directly from the firmware blob. Second is a new query enabling query of geometry subslices needed to support the fact geometry and compute slice configuration is no longer uniform. Also on the UAPI front there is sysfs support for multi-tile platforms which exports the existing controls such as frequency and similar but duplicated for each tile. Graphics System Controller (GSC) support was added for discrete platforms as well, which is required both for firmware management and protected media path. Access to this is via the existing MEI character device. Work has also started refactoring the codebase to allow driver builds outside x86. Finally, there were two drm-next backmerges to unblock feature development. Regards, Tvrtko drm-intel-gt-next-2022-04-27: UAPI Changes: - GuC hwconfig support and query (John Harrison, Rodrigo Vivi, Tvrtko Ursulin) - Sysfs support for multi-tile devices (Andi Shyti, Sujaritha Sundaresan) - Per client GPU utilisation via fdinfo (Tvrtko Ursulin, Ashutosh Dixit) - Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (Matt Atwood) Cross-subsystem Changes: - Add GSC as a MEI auxiliary device (Tomas Winkler, Alexander Usyskin) Core Changes: - Document fdinfo format specification (Tvrtko Ursulin) Driver Changes: - Fix prime_mmap to work when using LMEM (Gwan-gyeong Mun) - Fix vm open count and remove vma refcount (Thomas Hellström) - Fixup setting screen_size (Matthew Auld) - Opportunistically apply ALLOC_CONTIGIOUS (Matthew Auld) - Limit where we apply TTM_PL_FLAG_CONTIGUOUS (Matthew Auld) - Drop aux table invalidation on FlatCCS platforms (Matt Roper) - Add missing boundary check in vm_access (Mastan Katragadda) - Update topology dumps for Xe_HP (Matt Roper) - Add support for steered register writes (Matt Roper) - Add steering info to GuC register save/restore list (Daniele Ceraolo Spurio) - Small PCI BAR enabling (Matthew Auld, Akeem G Abodunrin, CQ Tang) - Add preemption changes for Wa_14015141709 (Akeem G Abodunrin) - Add logical mapping for video decode engines (Matthew Brost) - Don't evict unmappable VMAs when pinning with PIN_MAPPABLE (v2) (Vivek Kasireddy) - GuC error capture support (Alan Previn, Daniele Ceraolo Spurio) - avoid concurrent writes to aux_inv (Fei Yang) - Add Wa_22014226127 (José Roberto de Souza) - Sunset igpu legacy mmap support based on GRAPHICS_VER_FULL (Matt Roper) - Evict and restore of compressed objects (Ramalingam C) - Update to GuC version 70.1.1 (John Harrison) - Add Wa_22011802037 force cs halt (Tilak Tangudu) - Enable Wa_22011802037 for gen12 GuC based platforms (Umesh Nerlige Ramappa) - GuC based workarounds for DG2 (Vinay Belgaumkar, John Harrison, Matthew Brost, José Roberto de Souza) - consider min_page_size when migrating (Matthew Auld) - Prep work for next GuC firmware release (John Harrison) - Support platforms with CCS engines but no RCS (Matt Roper, Stuart Summers) - Don't overallocate subslice storage (Matt Roper) - Reduce stack usage in debugfs due to SSEU (John Harrison) - Report steering details in debugfs (Matt Roper) - Refactor some x86-ism out to prepare for non-x86 builds (Michael Cheng) - add lmem_size modparam (CQ Tang) - Refactor for non-x86 driver builds (Casey Bowman) - Centralize computation of freq caps (Ashutosh Dixit) - Update dma_buf_ops.unmap_dma_buf callback to use drm_gem_unmap_dma_buf() (Gwan-gyeong Mun) - Limit the async bind to bind_async_flags (Matthew Auld) - Stop checking for NULL vma->obj (Matthew Auld) - Reduce overzealous alignment constraints for GGTT (Matthew Auld) - Remove GEN12_SFC_DONE_MAX from register defs header (Matt Roper) - Fix renamed struct field (Lucas De Marchi) - Do not return '0' if there is nothing to return (Andi Shyti) - fix i915_reg_t initialization (Jani Nikula) - move the migration sanity check (Matthew Auld) - handle more rounding in selftests (Matthew Auld) - Perf and i915 query kerneldoc updates (Matt Roper) - Use i915_probe_error instead of drm_err (Vinay Belgaumkar) - sanity check object size in the buddy allocator (Matthew Auld) - fixup selftests min_alignment usage (Matthew Auld) - tweak selftests misaligned_case (Matthew Auld) The following changes since commit c54b39a565227538c52ead2349eb17d54aadd6f7: Merge tag 'drm-intel-next-2022-04-13-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2022-04-14 12:03:09 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2022-04-27 for you to fetch changes up to f15856d7de914595d0daa2c706f53a693b48e228: drm/i915/dg2: add gsc with special gsc bar offsets (2022-04-21 11:34:39 -0700) ---------------------------------------------------------------- UAPI Changes: - GuC hwconfig support and query (John Harrison, Rodrigo Vivi, Tvrtko Ursulin) - Sysfs support for multi-tile devices (Andi Shyti, Sujaritha Sundaresan) - Per client GPU utilisation via fdinfo (Tvrtko Ursulin, Ashutosh Dixit) - Add DRM_I915_QUERY_GEOMETRY_SUBSLICES (Matt Atwood) Cross-subsystem Changes: - Add GSC as a MEI auxiliary device (Tomas Winkler, Alexander Usyskin) Core Changes: - Document fdinfo format specification (Tvrtko Ursulin) Driver Changes: - Fix prime_mmap to work when using LMEM (Gwan-gyeong Mun) - Fix vm open count and remove vma refcount (Thomas Hellström) - Fixup setting screen_size (Matthew Auld) - Opportunistically apply ALLOC_CONTIGIOUS (Matthew Auld) - Limit where we apply TTM_PL_FLAG_CONTIGUOUS (Matthew Auld) - Drop aux table invalidation on FlatCCS platforms (Matt Roper) - Add missing boundary check in vm_access (Mastan Katragadda) - Update topology dumps for Xe_HP (Matt Roper) - Add support for steered register writes (Matt Roper) - Add steering info to GuC register save/restore list (Daniele Ceraolo Spurio) - Small PCI BAR enabling (Matthew Auld, Akeem G Abodunrin, CQ Tang) - Add preemption changes for Wa_14015141709 (Akeem G Abodunrin) - Add logical mapping for video decode engines (Matthew Brost) - Don't evict unmappable VMAs when pinning with PIN_MAPPABLE (v2) (Vivek Kasireddy) - GuC error capture support (Alan Previn, Daniele Ceraolo Spurio) - avoid concurrent writes to aux_inv (Fei Yang) - Add Wa_22014226127 (José Roberto de Souza) - Sunset igpu legacy mmap support based on GRAPHICS_VER_FULL (Matt Roper) - Evict and restore of compressed objects (Ramalingam C) - Update to GuC version 70.1.1 (John Harrison) - Add Wa_22011802037 force cs halt (Tilak Tangudu) - Enable Wa_22011802037 for gen12 GuC based platforms (Umesh Nerlige Ramappa) - GuC based workarounds for DG2 (Vinay Belgaumkar, John Harrison, Matthew Brost, José Roberto de Souza) - consider min_page_size when migrating (Matthew Auld) - Prep work for next GuC firmware release (John Harrison) - Support platforms with CCS engines but no RCS (Matt Roper, Stuart Summers) - Don't overallocate subslice storage (Matt Roper) - Reduce stack usage in debugfs due to SSEU (John Harrison) - Report steering details in debugfs (Matt Roper) - Refactor some x86-ism out to prepare for non-x86 builds (Michael Cheng) - add lmem_size modparam (CQ Tang) - Refactor for non-x86 driver builds (Casey Bowman) - Centralize computation of freq caps (Ashutosh Dixit) - Update dma_buf_ops.unmap_dma_buf callback to use drm_gem_unmap_dma_buf() (Gwan-gyeong Mun) - Limit the async bind to bind_async_flags (Matthew Auld) - Stop checking for NULL vma->obj (Matthew Auld) - Reduce overzealous alignment constraints for GGTT (Matthew Auld) - Remove GEN12_SFC_DONE_MAX from register defs header (Matt Roper) - Fix renamed struct field (Lucas De Marchi) - Do not return '0' if there is nothing to return (Andi Shyti) - fix i915_reg_t initialization (Jani Nikula) - move the migration sanity check (Matthew Auld) - handle more rounding in selftests (Matthew Auld) - Perf and i915 query kerneldoc updates (Matt Roper) - Use i915_probe_error instead of drm_err (Vinay Belgaumkar) - sanity check object size in the buddy allocator (Matthew Auld) - fixup selftests min_alignment usage (Matthew Auld) - tweak selftests misaligned_case (Matthew Auld) ---------------------------------------------------------------- Akeem G Abodunrin (2): drm/i915/stolen: don't treat small BAR as an error drm/i915/dg2: Add preemption changes for Wa_14015141709 Alan Previn (13): drm/i915/guc: Update GuC ADS size for error capture lists drm/i915/guc: Add XE_LP static registers for GuC error capture. drm/i915/guc: Add XE_LP steered register lists support drm/i915/guc: Add DG2 registers for GuC error state capture. drm/i915/guc: Add Gen9 registers for GuC error state capture. drm/i915/guc: Add GuC's error state capture output structures. drm/i915/guc: Update GuC-log relay function names drm/i915/guc: Add capture region into intel_guc_log drm/i915/guc: Check sizing of guc_capture output drm/i915/guc: Extract GuC error capture lists on G2H notification. drm/i915/guc: Pre-allocate output nodes for extraction drm/i915/guc: Plumb GuC-capture into gpu_coredump drm/i915/guc: Print the GuC error capture output register list. Alexander Usyskin (2): mei: gsc: setup char driver alive in spite of firmware handshake failure mei: gsc: retrieve the firmware version Andi Shyti (6): drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0 drm/i915/gt: add gt_is_root() helper drm/i915/gt: create per-tile sysfs interface drm/i915/gt: Create per-tile RC6 sysfs interface drm/i915/gt: Create per-tile RPS sysfs interfaces drm/i915/debugfs: Do not return '0' if there is nothing to return Ashutosh Dixit (2): drm/i915/rps: Centralize computation of freq caps drm/i915: Don't show engine information in fdinfo with GuC submission CQ Tang (2): drm/i915/display: Check mappable aperture when pinning preallocated vma drm/i915: add lmem_size modparam Casey Bowman (2): drm/i915/gt: Split intel-gtt functions by arch drm/i915: Require INTEL_GTT to depend on X86 Daniele Ceraolo Spurio (2): drm/i915/guc: add steering info to GuC register save/restore list drm/i915/guc: Correctly free guc capture struct on error Fei Yang (1): drm/i915: avoid concurrent writes to aux_inv Gwan-gyeong Mun (2): drm/i915/dmabuf: Update dma_buf_ops.unmap_dma_buf callback to use drm_gem_unmap_dma_buf() drm/i915/dmabuf: Fix prime_mmap to work when using LMEM Jani Nikula (1): drm/i915/gt: fix i915_reg_t initialization John Harrison (13): drm/i915/guc: Do not conflate lrc_desc with GuC id for registration drm/i915/guc: Add an explicit 'submission_initialized' flag drm/i915/guc: Better name for context id limit drm/i915/guc: Split guc_lrc_desc_pin apart drm/i915/guc: Move lrc desc setup to where it is needed drm/i915/guc: Rename desc_idx to ctx_id drm/i915/guc: Drop obsolete H2G definitions drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs drm/i915: Reduce stack usage in debugfs due to SSEU drm/i915/guc: Add fetch of hwconfig blob drm/i915/guc: Update to GuC version 70.1.1 drm/i915/guc: Enable GuC based workarounds for DG2 drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 Joonas Lahtinen (1): Merge drm/drm-next into drm-intel-gt-next José Roberto de Souza (2): drm/i915/dg2: Add Wa_22014226127 drm/i915/dg2: Add workaround 18019627453 Lucas De Marchi (1): drm/i915: Fix renamed struct field Mastan Katragadda (1): drm/i915/gem: add missing boundary check in vm_access Matt Atwood (1): drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES Matt Roper (11): drm/i915/xehp: Support platforms with CCS engines but no RCS drm/i915/xehp: Drop aux table invalidation on FlatCCS platforms drm/i915/gt: Remove GEN12_SFC_DONE_MAX from register defs header drm/i915/sseu: Don't overallocate subslice storage drm/i915/xehp: Update topology dumps for Xe_HP drm/i915: Report steering details in debugfs drm/i915: Add support for steered register writes drm/i915: Sunset igpu legacy mmap support based on GRAPHICS_VER_FULL drm/i915/doc: Convert drm_i915_query_topology_info comment to kerneldoc drm/i915/doc: Convert perf UAPI comments to kerneldoc drm/i915/doc: Link query items to their uapi structs Matthew Auld (17): drm/i915/fbdev: fixup setting screen_size drm/i915: limit the async bind to bind_async_flags drm/i915: stop checking for NULL vma->obj drm/i915/gtt: reduce overzealous alignment constraints for GGTT drm/i915: opportunistically apply ALLOC_CONTIGIOUS drm/i915/lmem: don't treat small BAR as an error drm/i915/stolen: consider I915_BO_ALLOC_GPU_ONLY drm/i915: add i915_gem_object_create_region_at() drm/i915/ttm: wire up the object offset drm/i915: fixup the initial fb base on DGFX drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS drm/i915/migrate: move the sanity check drm/i915/selftests: handle more rounding drm/i915: consider min_page_size when migrating drm/i915/buddy: sanity check the size drm/i915/selftests: fixup min_alignment usage drm/i915/selftests: tweak the misaligned_case Matthew Brost (2): drm/i915: Add logical mapping for video decode engines drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Michael Cheng (5): drm/i915/gt: Re-work intel_write_status_page drm/i915/gt: Drop invalidate_csb_entries drm/i915/gt: Re-work reset_csb drm/i915/: Re-work clflush_write32 drm/i915/gt: replace cache_clflush_range Ramalingam C (9): drm/i915/gt: use engine instance directly for offset drm/i915/gt: Use XY_FAST_COLOR_BLT to clear obj on graphics ver 12+ drm/i915/gt: Optimize the migration and clear loop drm/i915/gt: Pass the -EINVAL when emit_pte doesn't update any PTE drm/i915/gt: Clear compress metadata for Flat-ccs objects drm/i915/selftest_migrate: Consider the possible roundup of size drm/i915/selftest_migrate: Check CCS meta data clear drm/i915/gem: Add extra pages in ttm_tt for ccs data drm/i915/migrate: Evict and restore the flatccs capable lmem obj Rodrigo Vivi (3): drm/i915/uapi: Add query for hwconfig blob drm/i915/hwconfig: Add DG2 support Merge drm/drm-next into drm-intel-gt-next Stuart Summers (1): drm/i915: Add RCS mask to GuC ADS params Sujaritha Sundaresan (1): drm/i915/gt: Add sysfs throttle frequency interfaces Thomas Hellström (3): drm/i915: Remove the vm open count drm/i915: Remove the vma refcount drm/i915/gem: Remove some unnecessary code Tilak Tangudu (1): drm/i915: Add Wa_22011802037 force cs halt Tomas Winkler (4): drm/i915/gsc: add gsc as a mei auxiliary device mei: add support for graphics system controller (gsc) devices mei: gsc: add runtime pm handlers drm/i915/dg2: add gsc with special gsc bar offsets Tvrtko Ursulin (11): drm/i915: Prepare for multiple GTs drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB drm/i915: Explicitly track DRM clients drm/i915: Make GEM contexts track DRM clients drm/i915: Track runtime spent in closed and unreachable GEM contexts drm/i915: Track all user contexts per client drm/i915: Track context current active time drm: Document fdinfo format specification drm/i915: Count engine instances per uabi class drm/i915: Expose client engine utilisation via fdinfo drm/i915: Fixup kerneldoc in struct i915_gem_context Umesh Nerlige Ramappa (1): drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Vinay Belgaumkar (2): drm/i915/guc/slpc: Use i915_probe_error instead of drm_err drm/i915/guc: Apply Wa_16011777198 Vivek Kasireddy (1): drm/i915/gem: Don't evict unmappable VMAs when pinning with PIN_MAPPABLE (v2) Documentation/gpu/drm-usage-stats.rst | 112 ++ Documentation/gpu/i915.rst | 28 + Documentation/gpu/index.rst | 1 + MAINTAINERS | 1 + drivers/gpu/drm/i915/Kconfig | 3 +- drivers/gpu/drm/i915/Makefile | 10 + drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 4 +- drivers/gpu/drm/i915/display/intel_plane_initial.c | 56 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 70 +- drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 6 + drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 14 +- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 + drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 2 + drivers/gpu/drm/i915/gem/i915_gem_region.c | 50 +- drivers/gpu/drm/i915/gem/i915_gem_region.h | 7 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 144 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 4 - drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 52 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 1 + .../gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +- .../gpu/drm/i915/gem/selftests/i915_gem_migrate.c | 12 +- drivers/gpu/drm/i915/gem/selftests/mock_context.c | 5 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 113 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 4 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +- drivers/gpu/drm/i915/gt/intel_context.c | 29 +- drivers/gpu/drm/i915/gt/intel_context.h | 15 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 24 +- drivers/gpu/drm/i915/gt/intel_engine.h | 13 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 40 +- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +- drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 +- .../gpu/drm/i915/gt/intel_execlists_submission.c | 49 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 693 +------- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 29 + drivers/gpu/drm/i915/gt/intel_gsc.c | 224 +++ drivers/gpu/drm/i915/gt/intel_gsc.h | 37 + drivers/gpu/drm/i915/gt/intel_gt.c | 223 ++- drivers/gpu/drm/i915/gt/intel_gt.h | 41 +- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 4 + drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 20 +- drivers/gpu/drm/i915/gt/intel_gt_debugfs.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 654 ++++++++ drivers/gpu/drm/i915/gt/intel_gt_gmch.h | 46 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 18 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 40 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 4 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 21 + drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 122 ++ drivers/gpu/drm/i915/gt/intel_gt_sysfs.h | 34 + drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 601 +++++++ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h | 15 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 + drivers/gpu/drm/i915/gt/intel_gtt.c | 56 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 65 +- drivers/gpu/drm/i915/gt/intel_hwconfig.h | 21 + drivers/gpu/drm/i915/gt/intel_lrc.c | 39 +- drivers/gpu/drm/i915/gt/intel_lrc.h | 27 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 390 ++++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 8 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +- drivers/gpu/drm/i915/gt/intel_reset.c | 7 +- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 126 +- drivers/gpu/drm/i915/gt/intel_rps.h | 6 +- drivers/gpu/drm/i915/gt/intel_rps_types.h | 15 + drivers/gpu/drm/i915/gt/intel_sseu.c | 54 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 50 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 21 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 86 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 +- drivers/gpu/drm/i915/gt/selftest_migrate.c | 259 ++- drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +- drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 4 + drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 15 + drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 218 +++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 48 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 19 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 185 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 1657 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h | 33 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 92 +- drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 164 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 125 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 7 +- drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 56 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 645 +++++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 30 +- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 12 +- drivers/gpu/drm/i915/i915_driver.c | 37 +- drivers/gpu/drm/i915/i915_drm_client.c | 158 ++ drivers/gpu/drm/i915/i915_drm_client.h | 68 + drivers/gpu/drm/i915/i915_drv.h | 25 + drivers/gpu/drm/i915/i915_file_private.h | 3 + drivers/gpu/drm/i915/i915_gem.c | 89 +- drivers/gpu/drm/i915/i915_gpu_error.c | 297 ++-- drivers/gpu/drm/i915/i915_gpu_error.h | 37 +- drivers/gpu/drm/i915/i915_params.c | 3 + drivers/gpu/drm/i915/i915_params.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 4 +- drivers/gpu/drm/i915/i915_query.c | 94 +- drivers/gpu/drm/i915/i915_reg.h | 18 + drivers/gpu/drm/i915/i915_reg_defs.h | 2 - drivers/gpu/drm/i915/i915_sysfs.c | 310 +--- drivers/gpu/drm/i915/i915_sysfs.h | 3 + drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 4 +- drivers/gpu/drm/i915/i915_vma.c | 98 +- drivers/gpu/drm/i915/i915_vma.h | 14 - drivers/gpu/drm/i915/i915_vma_resource.c | 2 +- drivers/gpu/drm/i915/i915_vma_resource.h | 6 + drivers/gpu/drm/i915/i915_vma_types.h | 8 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_memory_region.c | 2 +- drivers/gpu/drm/i915/intel_memory_region.h | 8 +- drivers/gpu/drm/i915/intel_region_ttm.c | 7 +- drivers/gpu/drm/i915/intel_region_ttm.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 86 +- drivers/gpu/drm/i915/intel_uncore.h | 7 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 18 +- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 13 +- drivers/gpu/drm/i915/selftests/mock_region.c | 4 + drivers/misc/mei/Kconfig | 14 + drivers/misc/mei/Makefile | 3 + drivers/misc/mei/bus-fixup.c | 25 + drivers/misc/mei/gsc-me.c | 259 +++ drivers/misc/mei/hw-me.c | 29 +- drivers/misc/mei/hw-me.h | 2 + include/linux/mei_aux.h | 19 + include/uapi/drm/i915_drm.h | 291 +++- 143 files changed, 8161 insertions(+), 2326 deletions(-) create mode 100644 Documentation/gpu/drm-usage-stats.rst create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h create mode 100644 drivers/gpu/drm/i915/gt/intel_hwconfig.h create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h create mode 100644 drivers/misc/mei/gsc-me.c create mode 100644 include/linux/mei_aux.h

1 0

[PATCH v2 0/5] drm/i915: ttm for stolen region
by Robert Beckett 27 Apr '22

27 Apr '22

This series refactors i915's stolen memory region to use ttm. v2: handle disabled stolen similar to legacy version. relying on ttm to fail allocs works fine, but is dmesg noisy and causes testing dmesg warning regressions. Robert Beckett (5): drm/i915: instantiate ttm ranger manager for stolen memory drm/i915: sanitize mem_flags for stolen buffers drm/i915: ttm move/clear logic fix drm/i915: ttm backend dont provide mmap_offset for kernel buffers drm/i915: stolen memory use ttm backend drivers/gpu/drm/i915/display/intel_fbc.c | 78 ++-- .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 - drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 407 ++++++------------ drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 21 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 32 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 7 + drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 33 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 16 +- drivers/gpu/drm/i915/i915_debugfs.c | 7 +- drivers/gpu/drm/i915/i915_drv.h | 5 - drivers/gpu/drm/i915/intel_region_ttm.c | 67 ++- drivers/gpu/drm/i915/intel_region_ttm.h | 8 +- drivers/gpu/drm/i915/selftests/mock_region.c | 3 +- 14 files changed, 319 insertions(+), 371 deletions(-) -- 2.25.1

2 10

[PATCH v6] drm/msm/dp: remove fail safe mode related code
by Kuogee Hsieh 27 Apr '22

27 Apr '22

Current DP driver implementation has adding safe mode done at dp_hpd_plug_handle() which is expected to be executed under event thread context. However there is possible circular locking happen (see blow stack trace) after edp driver call dp_hpd_plug_handle() from dp_bridge_enable() which is executed under drm_thread context. After review all possibilities methods and as discussed on https://patchwork.freedesktop.org/patch/483155/, supporting EDID compliance tests in the driver is quite hacky. As seen with other vendor drivers, supporting these will be much easier with IGT. Hence removing all the related fail safe code for it so that no possibility of circular lock will happen. ====================================================== WARNING: possible circular locking dependency detected 5.15.35-lockdep #6 Tainted: G W ------------------------------------------------------ frecon/429 is trying to acquire lock: ffffff808dc3c4e8 (&dev->mode_config.mutex){+.+.}-{3:3}, at: dp_panel_add_fail_safe_mode+0x4c/0xa0 but task is already holding lock: ffffff808dc441e0 (&kms->commit_lock[i]){+.+.}-{3:3}, at: lock_crtcs+0xb4/0x124 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #3 (&kms->commit_lock[i]){+.+.}-{3:3}: __mutex_lock_common+0x174/0x1a64 mutex_lock_nested+0x98/0xac lock_crtcs+0xb4/0x124 msm_atomic_commit_tail+0x330/0x748 commit_tail+0x19c/0x278 drm_atomic_helper_commit+0x1dc/0x1f0 drm_atomic_commit+0xc0/0xd8 drm_atomic_helper_set_config+0xb4/0x134 drm_mode_setcrtc+0x688/0x1248 drm_ioctl_kernel+0x1e4/0x338 drm_ioctl+0x3a4/0x684 __arm64_sys_ioctl+0x118/0x154 invoke_syscall+0x78/0x224 el0_svc_common+0x178/0x200 do_el0_svc+0x94/0x13c el0_svc+0x5c/0xec el0t_64_sync_handler+0x78/0x108 el0t_64_sync+0x1a4/0x1a8 -> #2 (crtc_ww_class_mutex){+.+.}-{3:3}: __mutex_lock_common+0x174/0x1a64 ww_mutex_lock+0xb8/0x278 modeset_lock+0x304/0x4ac drm_modeset_lock+0x4c/0x7c drmm_mode_config_init+0x4a8/0xc50 msm_drm_init+0x274/0xac0 msm_drm_bind+0x20/0x2c try_to_bring_up_master+0x3dc/0x470 __component_add+0x18c/0x3c0 component_add+0x1c/0x28 dp_display_probe+0x954/0xa98 platform_probe+0x124/0x15c really_probe+0x1b0/0x5f8 __driver_probe_device+0x174/0x20c driver_probe_device+0x70/0x134 __device_attach_driver+0x130/0x1d0 bus_for_each_drv+0xfc/0x14c __device_attach+0x1bc/0x2bc device_initial_probe+0x1c/0x28 bus_probe_device+0x94/0x178 deferred_probe_work_func+0x1a4/0x1f0 process_one_work+0x5d4/0x9dc worker_thread+0x898/0xccc kthread+0x2d4/0x3d4 ret_from_fork+0x10/0x20 -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}: ww_acquire_init+0x1c4/0x2c8 drm_modeset_acquire_init+0x44/0xc8 drm_helper_probe_single_connector_modes+0xb0/0x12dc drm_mode_getconnector+0x5dc/0xfe8 drm_ioctl_kernel+0x1e4/0x338 drm_ioctl+0x3a4/0x684 __arm64_sys_ioctl+0x118/0x154 invoke_syscall+0x78/0x224 el0_svc_common+0x178/0x200 do_el0_svc+0x94/0x13c el0_svc+0x5c/0xec el0t_64_sync_handler+0x78/0x108 el0t_64_sync+0x1a4/0x1a8 -> #0 (&dev->mode_config.mutex){+.+.}-{3:3}: __lock_acquire+0x2650/0x672c lock_acquire+0x1b4/0x4ac __mutex_lock_common+0x174/0x1a64 mutex_lock_nested+0x98/0xac dp_panel_add_fail_safe_mode+0x4c/0xa0 dp_hpd_plug_handle+0x1f0/0x280 dp_bridge_enable+0x94/0x2b8 drm_atomic_bridge_chain_enable+0x11c/0x168 drm_atomic_helper_commit_modeset_enables+0x500/0x740 msm_atomic_commit_tail+0x3e4/0x748 commit_tail+0x19c/0x278 drm_atomic_helper_commit+0x1dc/0x1f0 drm_atomic_commit+0xc0/0xd8 drm_atomic_helper_set_config+0xb4/0x134 drm_mode_setcrtc+0x688/0x1248 drm_ioctl_kernel+0x1e4/0x338 drm_ioctl+0x3a4/0x684 __arm64_sys_ioctl+0x118/0x154 invoke_syscall+0x78/0x224 el0_svc_common+0x178/0x200 do_el0_svc+0x94/0x13c el0_svc+0x5c/0xec el0t_64_sync_handler+0x78/0x108 el0t_64_sync+0x1a4/0x1a8 Changes in v2: -- re text commit title -- remove all fail safe mode Changes in v3: -- remove dp_panel_add_fail_safe_mode() from dp_panel.h -- add Fixes Changes in v5: -- to=dianders(a)chromium.org Changes in v6: -- fix Fixes commit ID Fixes: 8b2c181e3dcf ("drm/msm/dp: add fail safe mode outside of event_mutex context") Reported-by: Douglas Anderson <dianders(a)chromium.org> Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> --- drivers/gpu/drm/msm/dp/dp_display.c | 6 ------ drivers/gpu/drm/msm/dp/dp_panel.c | 11 ----------- drivers/gpu/drm/msm/dp/dp_panel.h | 1 - 3 files changed, 18 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 92cd50f..01453db 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -555,12 +555,6 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) mutex_unlock(&dp->event_mutex); - /* - * add fail safe mode outside event_mutex scope - * to avoid potiential circular lock with drm thread - */ - dp_panel_add_fail_safe_mode(dp->dp_display.connector); - /* uevent will complete connection part */ return 0; }; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 1aa9aa8c..8ff174a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -151,15 +151,6 @@ static int dp_panel_update_modes(struct drm_connector *connector, return rc; } -void dp_panel_add_fail_safe_mode(struct drm_connector *connector) -{ - /* fail safe edid */ - mutex_lock(&connector->dev->mode_config.mutex); - if (drm_add_modes_noedid(connector, 640, 480)) - drm_set_preferred_mode(connector, 640, 480); - mutex_unlock(&connector->dev->mode_config.mutex); -} - int dp_panel_read_sink_caps(struct dp_panel *dp_panel, struct drm_connector *connector) { @@ -215,8 +206,6 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, rc = -ETIMEDOUT; goto end; } - - dp_panel_add_fail_safe_mode(connector); } if (panel->aux_cfg_update_done) { diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 99739ea..9023e5b 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -59,7 +59,6 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel); int dp_panel_deinit(struct dp_panel *dp_panel); int dp_panel_timing_cfg(struct dp_panel *dp_panel); void dp_panel_dump_regs(struct dp_panel *dp_panel); -void dp_panel_add_fail_safe_mode(struct drm_connector *connector); int dp_panel_read_sink_caps(struct dp_panel *dp_panel, struct drm_connector *connector); u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

4 3

[PATCH v2 0/3] i915: Upstream initial DG2 PCI IDs
by Matt Roper 27 Apr '22

27 Apr '22

We've had all of our DG2 and ATS-M PCI IDs in the topic/core-for-CI branch for a while, but we've now got the critical uapi changes in place to unblock upstreaming the initial subset (which correspond to "motherboard down" designs) through the drm-intel tree. The remaining IDs (which correspond to add-in card designs) will remain in the topic/core-for-CI branch until some additional prerequisite functionality lands. Since the topic/core-for-CI branch is a rebasing branch, we'll just rebase the relevant IDs out of it when the time comes, but I'm sending them as a formal revert here so that the CI system doesn't get confused when testing the series. Note that a handful of new DG2-G12 IDs have also shown up recently, so those additional IDs are also included here. Cc: Lucas De Marchi <lucas.demarchi(a)intel.com> Matt Roper (3): topic/core-for-CI: Revert DG2 and ATS-M device IDs drm/i915: Add first set of DG2 PCI IDs topic/core-for-CI: Add remaining DG2 and ATS-M device IDs include/drm/i915_pciids.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.35.1

2 4

[PULL] drm-misc-fixes
by Maarten Lankhorst 27 Apr '22

27 Apr '22

drm-misc-fixes-2022-04-27: drm-misc-fixes for v5.18-rc5: - Single fix removing applying PHYS_OFFSET twice in sunxi. The following changes since commit 94f4c4965e5513ba624488f4b601d6b385635aec: drm/amdgpu: partial revert "remove ctx->lock" v2 (2022-04-21 11:26:20 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-04-27 for you to fetch changes up to dc3ae06c5f2170d879ff58696f629d8c3868aec3: drm/sun4i: Remove obsolete references to PHYS_OFFSET (2022-04-26 14:39:56 +0200) ---------------------------------------------------------------- drm-misc-fixes for v5.18-rc5: - Single fix removing applying PHYS_OFFSET twice in sunxi. ---------------------------------------------------------------- Samuel Holland (1): drm/sun4i: Remove obsolete references to PHYS_OFFSET drivers/gpu/drm/sun4i/sun4i_frontend.c | 3 --- 1 file changed, 3 deletions(-)

1 0

[PATCH 1/2] drm/vmwgfx: Remove unused hugepage support
by Zack Rusin 27 Apr '22

27 Apr '22

From: Zack Rusin <zackr(a)vmware.com> There's no point in explicitly trying to align virtual memory to facilitate huge page table entries or huge page memory in buffer objects given that they're not being used. Transparent hugepages support for vram allocations has been gradually retired over the last two years making alignment of unmapped areas unneeded and pointless. Signed-off-by: Zack Rusin <zackr(a)vmware.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 5dc02fd806db..45028e25d490 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -1423,18 +1423,6 @@ static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) root, "system_mob_ttm"); } -static unsigned long -vmw_get_unmapped_area(struct file *file, unsigned long uaddr, - unsigned long len, unsigned long pgoff, - unsigned long flags) -{ - struct drm_file *file_priv = file->private_data; - struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); - - return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, - dev_priv->drm.vma_offset_manager); -} - static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, void *ptr) { @@ -1601,7 +1589,6 @@ static const struct file_operations vmwgfx_driver_fops = { .compat_ioctl = vmw_compat_ioctl, #endif .llseek = noop_llseek, - .get_unmapped_area = vmw_get_unmapped_area, }; static const struct drm_driver driver = { -- 2.32.0

2 2

[PATCH 0/5] MediaTek MT8195 display binding
by Rex-BC Chen 27 Apr '22

27 Apr '22

Add this series to present MediaTek display binding for MT8195. The reason I send this series is Jason and Nancy's binding patches are never received by devicetree mail server. Therefore, I help them to resend binding patches. All of these patches are reviewed in other series: [1]: message id: 20220415083911.5186-1-jason-jh.lin(a)mediatek.com [2]: message id: 20220416020749.29010-1-nancy.lin(a)mediatek.com This series depends on Yong's MT8195 IOMMU series: [3]: message id: 20220407075726.17771-2-yong.wu(a)mediatek.com Without this patch, some patches of this series will build failed. Nancy.Lin (3): dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195 dt-bindings: reset: mt8195: add vdosys1 reset control bit dt-bindings: mediatek: add ethdr definition for mt8195 jason-jh.lin (2): dt-bindings: arm: mediatek: mmsys: add power and gce properties dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding .../bindings/arm/mediatek/mediatek,mmsys.yaml | 32 ++++ .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ .../display/mediatek/mediatek,mdp-rdma.yaml | 86 ++++++++++ include/dt-bindings/reset/mt8195-resets.h | 12 ++ 4 files changed, 288 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml -- 2.18.0

6 20

[PATCH 1/2] drm/amdgpu: debugfs: fix error codes in write functions
by Dan Carpenter 27 Apr '22

27 Apr '22

There are two error code bugs here. The copy_to/from_user() functions return the number of bytes remaining (a positive number). We should return -EFAULT if the copy fails. Second if we fail because "context.resp_status" is non-zero then return -EINVAL instead of zero. Fixes: e50d9ba0d2cd ("drm/amdgpu: Add debugfs TA load/unload/invoke support") Signed-off-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- There are a bunch of exit paths where copy_from_user() fails and this function returns -EINVAL which is wrong as well. If the copy fails it should be -EFAULT. If the data is bad, then -EINVAL. drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c index 247a476e6354..32bcc20b9e3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c @@ -159,9 +159,10 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t ta_bin = kzalloc(ta_bin_len, GFP_KERNEL); if (!ta_bin) ret = -ENOMEM; - ret = copy_from_user((void *)ta_bin, &buf[copy_pos], ta_bin_len); - if (ret) + if (copy_from_user((void *)ta_bin, &buf[copy_pos], ta_bin_len)) { + ret = -EFAULT; goto err_free_bin; + } ret = psp_ras_terminate(psp); if (ret) { @@ -180,11 +181,14 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t if (ret || context.resp_status) { dev_err(adev->dev, "TA load via debugfs failed (%d) status %d\n", ret, context.resp_status); + if (!ret) + ret = -EINVAL; goto err_free_bin; } context.initialized = true; - ret = copy_to_user((char *)buf, (void *)&context.session_id, sizeof(uint32_t)); + if (copy_to_user((char *)buf, (void *)&context.session_id, sizeof(uint32_t))) + ret = -EFAULT; err_free_bin: kfree(ta_bin); @@ -251,9 +255,10 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size shared_buf = kzalloc(shared_buf_len, GFP_KERNEL); if (!shared_buf) ret = -ENOMEM; - ret = copy_from_user((void *)shared_buf, &buf[copy_pos], shared_buf_len); - if (ret) + if (copy_from_user((void *)shared_buf, &buf[copy_pos], shared_buf_len)) { + ret = -EFAULT; goto err_free_shared_buf; + } context.session_id = ta_id; @@ -264,10 +269,13 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size if (ret || context.resp_status) { dev_err(adev->dev, "TA invoke via debugfs failed (%d) status %d\n", ret, context.resp_status); + if (!ret) + ret = -EINVAL; goto err_free_ta_shared_buf; } - ret = copy_to_user((char *)buf, context.mem_context.shared_buf, shared_buf_len); + if (copy_to_user((char *)buf, context.mem_context.shared_buf, shared_buf_len)) + ret = -EFAULT; err_free_ta_shared_buf: psp_ta_free_shared_buf(&context.mem_context); -- 2.35.1

3 3

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dri-devel April 2022