>From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
DRM driver do a proper work of calling
drm_bridge_connector_en/disable_hpd() in right places. Rather than
teaching each and every driver how to properly handle
drm_bridge_connector's HPD, make that automatic.
Add two additional drm_connector helper funcs: enable_hpd() and
disable_hpd(). Make drm_kms_helper_poll_* functions call them (as this
is the time where the drm_bridge_connector's functions are called by the
…
[View More]drivers too).
Dmitry Baryshkov (7):
drm/poll-helper: merge drm_kms_helper_poll_disable() and _fini()
drm/probe-helper: enable and disable HPD on connectors
drm/bridge_connector: rely on drm_kms_helper_poll_* for HPD enablement
drm/imx/dcss: stop using drm_bridge_connector_en/disable_hpd()
drm/msm/hdmi: stop using drm_bridge_connector_en/disable_hpd()
drm/omap: stop using drm_bridge_connector_en/disable_hpd()
drm/bridge_connector: drop drm_bridge_connector_en/disable_hpd()
drivers/gpu/drm/drm_bridge_connector.c | 23 +++----------
drivers/gpu/drm/drm_probe_helper.c | 40 ++++++++++++++++++-----
drivers/gpu/drm/imx/dcss/dcss-dev.c | 4 ---
drivers/gpu/drm/imx/dcss/dcss-kms.c | 4 ---
drivers/gpu/drm/msm/hdmi/hdmi.c | 2 --
drivers/gpu/drm/omapdrm/omap_drv.c | 41 ------------------------
include/drm/drm_bridge_connector.h | 2 --
include/drm/drm_modeset_helper_vtables.h | 22 +++++++++++++
8 files changed, 58 insertions(+), 80 deletions(-)
--
2.35.1
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The stuff never really worked, and leads to lots of fun because it
out-of-order frees atomic states. Which upsets KASAN, among other
things.
For async updates we now have a more solid solution with the
->atomic_async_check and ->atomic_async_commit hooks. Support for that
for msm and vc4 landed. nouveau and i915 have their own commit
routines, doing something similar.
For everyone else it's probably better to remove the use-after-free
bug, and encourage folks to use the async support …
[View More]instead. The
affected drivers which register a legacy cursor plane and don't either
use the new async stuff or their own commit routine are: amdgpu,
atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx.
Inspired by an amdgpu bug report.
v2: Drop RFC, I think with amdgpu converted over to use
atomic_async_check/commit done in
commit 674e78acae0dfb4beb56132e41cbae5b60f7d662
Author: Nicholas Kazlauskas <nicholas.kazlauskas(a)amd.com>
Date: Wed Dec 5 14:59:07 2018 -0500
drm/amd/display: Add fast path for cursor plane updates
we don't have any driver anymore where we have userspace expecting
solid legacy cursor support _and_ they are using the atomic helpers in
their fully glory. So we can retire this.
v3: Paper over msm and i915 regression. The complete_all is the only
thing missing afaict.
v4: Fixup i915 fixup ...
References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
References: https://lore.kernel.org/all/20220221134155.125447-9-maxime@cerno.tech/
References: https://bugzilla.kernel.org/show_bug.cgi?id=199425
Cc: Maxime Ripard <maxime(a)cerno.tech>
Tested-by: Maxime Ripard <maxime(a)cerno.tech>
Cc: mikita.lipski(a)amd.com
Cc: Michel Dänzer <michel(a)daenzer.net>
Cc: harry.wentland(a)amd.com
Cc: Rob Clark <robdclark(a)gmail.com>
Cc: "Kazlauskas, Nicholas" <nicholas.kazlauskas(a)amd.com>
Cc: Dmitry Osipenko <dmitry.osipenko(a)collabora.com>
Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com>
---
drivers/gpu/drm/drm_atomic_helper.c | 13 -------------
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++++
drivers/gpu/drm/msm/msm_atomic.c | 2 ++
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 9603193d2fa1..a2899af82b4a 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1498,13 +1498,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
int i, ret;
unsigned int crtc_mask = 0;
- /*
- * Legacy cursor ioctls are completely unsynced, and userspace
- * relies on that (by doing tons of cursor updates).
- */
- if (old_state->legacy_cursor_update)
- return;
-
for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) {
if (!new_crtc_state->active)
continue;
@@ -2135,12 +2128,6 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state,
continue;
}
- /* Legacy cursor updates are fully unsynced. */
- if (state->legacy_cursor_update) {
- complete_all(&commit->flip_done);
- continue;
- }
-
if (!new_crtc_state->event) {
commit->event = kzalloc(sizeof(*commit->event),
GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d2abe0e430bf..6ca5a6e7703b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8799,6 +8799,20 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
return ret;
}
+
+ /*
+ * FIXME: Cut over to (async) commit helpers instead of hand-rolling
+ * everything.
+ */
+ if (state->base.legacy_cursor_update) {
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+ complete_all(&new_crtc_state->uapi.commit->flip_done);
+ }
+
intel_shared_dpll_swap_state(state);
intel_atomic_track_fbs(state);
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 1686fbb611fd..b3cfabebe5d6 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -222,6 +222,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state)
/* async updates are limited to single-crtc updates: */
WARN_ON(crtc_mask != drm_crtc_mask(async_crtc));
+ complete_all(&async_crtc->state->commit->flip_done);
+
/*
* Start timer if we don't already have an update pending
* on this crtc:
--
2.34.1
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Currently the DSI driver has two separate paths: one if the next device
in a chain is a bridge and another one if the panel is connected
directly to the DSI host.
The later functionality is already suppurted by the panel-bridge driver,
which wraps drm panel into the drm bridge instance. Using it will remove
the need for special handling of drm_panel and drm_connector inside the
DSI driver. With these patches in all cases the DSI driver will see the
chain bridges which either support bridge-…
[View More]connector or allocate the
connector on their own.
----------------------------------------------------------------
Dmitry Baryshkov (2):
drm/msm/dsi: move DSI host powerup to modeset time
drm/msm/dsi: switch to DRM_PANEL_BRIDGE
drivers/gpu/drm/msm/dsi/dsi.c | 32 +---
drivers/gpu/drm/msm/dsi/dsi.h | 10 +-
drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +--
drivers/gpu/drm/msm/dsi/dsi_manager.c | 296 ++++++----------------------------
4 files changed, 61 insertions(+), 297 deletions(-)
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Refactor the confusing logic to make it both clearer and more robust. If
the host1x parent device does have an IOMMU domain then iommu_present()
is redundantly true, while otherwise for the 32-bit DMA mask case it
still doesn't say whether the IOMMU driver actually knows about the DRM
device or not.
Signed-off-by: Robin Murphy <robin.murphy(a)arm.com>
---
v2: Fix logic for older SoCs and clarify.
drivers/gpu/drm/tegra/drm.c | 28 ++++++++++++++++++++--------
1 file changed, 20 …
[View More]insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 9464f522e257..4f2bdab31064 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -1092,6 +1092,19 @@ static bool host1x_drm_wants_iommu(struct host1x_device *dev)
struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
struct iommu_domain *domain;
+ /* For starters, this is moot if no IOMMU is available */
+ if (!device_iommu_mapped(&dev->dev))
+ return false;
+
+ /*
+ * Tegra20 and Tegra30 don't support addressing memory beyond the
+ * 32-bit boundary, so the regular GATHER opcodes will always be
+ * sufficient and whether or not the host1x is attached to an IOMMU
+ * doesn't matter.
+ */
+ if (host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
+ return true;
+
/*
* If the Tegra DRM clients are backed by an IOMMU, push buffers are
* likely to be allocated beyond the 32-bit boundary if sufficient
@@ -1122,14 +1135,13 @@ static bool host1x_drm_wants_iommu(struct host1x_device *dev)
domain = iommu_get_domain_for_dev(dev->dev.parent);
/*
- * Tegra20 and Tegra30 don't support addressing memory beyond the
- * 32-bit boundary, so the regular GATHER opcodes will always be
- * sufficient and whether or not the host1x is attached to an IOMMU
- * doesn't matter.
+ * At the moment, the exact type of domain doesn't actually matter.
+ * Only for 64-bit kernels might this be a managed DMA API domain, and
+ * then only on newer SoCs using arm-smmu, since tegra-smmu doesn't
+ * support default domains at all, and since those SoCs are the same
+ * ones with extended GATHER support, even if it's a passthrough domain
+ * it can still work out OK.
*/
- if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
- return true;
-
return domain != NULL;
}
@@ -1149,7 +1161,7 @@ static int host1x_drm_probe(struct host1x_device *dev)
goto put;
}
- if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
+ if (host1x_drm_wants_iommu(dev)) {
tegra->domain = iommu_domain_alloc(&platform_bus_type);
if (!tegra->domain) {
err = -ENOMEM;
--
2.28.0.dirty
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