dri-devel June 2022

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697 discussions

[PATCH][next] drm/amdgpu/display: Fix spelling mistake "supporing" -> "supporting"
by Colin Ian King 23 Jun '22

23 Jun '22

There is a spelling mistake in a dml_print message. Fix it. Signed-off-by: Colin Ian King <colin.i.king(a)gmail.com> --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 7f144adb1e36..7d536c2f4477 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1098,7 +1098,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) { v->ImmediateFlipSupported = false; #ifdef __DML_VBA_DEBUG__ - dml_print("DML::%s: Pipe %0d not supporing iflip\n", __func__, k); + dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k); #endif } } -- 2.35.3

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[PATCH] drm/amdgpu: drop unexpected word 'for' in comments
by Jiang Jian 23 Jun '22

23 Jun '22

there is an unexpected word 'for' in the comments that need to be dropped file - drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c line - 245 * position and also advance the position for for Vega10 changed to: * position and also advance the position for Vega10 Signed-off-by: Jiang Jian <jiangjian(a)cdjrlc.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 3df146579ad9..1d5af50331e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -242,7 +242,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) * @entry: IV entry * * Decodes the interrupt vector at the current rptr - * position and also advance the position for for Vega10 + * position and also advance the position for Vega10 * and later GPUs. */ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, -- 2.17.1

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[PATCH][next] drm/amdkfd: Fix spelling mistake "mechanim" -> "mechanism"
by Colin Ian King 23 Jun '22

23 Jun '22

There is a spelling mistake in a pr_debug message. Fix it. Signed-off-by: Colin Ian King <colin.i.king(a)gmail.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8805bd1eed37..f5f1368c0c54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -914,7 +914,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) goto unwind; - pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); + pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; -- 2.35.3

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[PATCH 0/2] drm/i915/display: stop HPD workers before display driver unregister
by Andrzej Hajda 23 Jun '22

23 Jun '22

Hi Jani, Ville, This patchset is replacement of patch "drm/i915/display: disable HPD workers before display driver unregister" [1]. Ive decided to split patch into two parts - fbdev and MST, there are different issues. Ive also dropped shutdown path, as it has slightly different requirements, and more importantly I am not able to test properly. [1]: https://patchwork.freedesktop.org/series/103811/ Regards Andrzej Andrzej Hajda (2): drm/i915/hpd: postpone HPD cancel work after last user suspension drm/i915/fbdev: suspend HPD before fbdev unregistration drivers/gpu/drm/i915/display/intel_display.c | 3 ++ drivers/gpu/drm/i915/display/intel_fbdev.c | 44 ++++++++++---------- drivers/gpu/drm/i915/i915_irq.c | 1 - 3 files changed, 26 insertions(+), 22 deletions(-) -- 2.25.1

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[PATCH v2 00/12] small BAR uapi bits
by Matthew Auld 23 Jun '22

23 Jun '22

Test-with: 20220621103001.184373-1-matthew.auld(a)intel.com IGT: https://patchwork.freedesktop.org/series/104368/#rev2 Mesa: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16739 (WIP) -- 2.36.1

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[PATCH v2] drm/sun4i: Enable output signal premultiplication for DE2/DE3
by Roman Stratiienko 23 Jun '22

23 Jun '22

Otherwise alpha value is discarded, resulting incorrect pixel apperance on the display. This also fixes missing transparency for the most bottom layer. Test applications and videos w/ w/o this patch are available at [1]. [1]: https://github.com/GloDroid/glodroid_tests/issues/1 Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- Changelog: V2: Added code hunk missing in v1 --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 5 +++-- drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 6b1711a9a71f..ba2932aaed08 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -320,8 +320,9 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, else val = 0; - regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), - SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); + val |= SUN8I_MIXER_BLEND_OUTCTL_PREMULTIPLY; + + regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), val); DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", interlaced ? "on" : "off"); diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index ebfc276b2464..bc12c95af6f3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -65,6 +65,7 @@ #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) +#define SUN8I_MIXER_BLEND_OUTCTL_PREMULTIPLY BIT(0) #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) -- 2.30.2

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[PATCH] drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch
by Imre Deak 23 Jun '22

23 Jun '22

The driver expects the pitch of the Intel CCS CC color planes to be 64 bytes aligned, adjust the modifier descriptions accordingly. Cc: Nanley Chery <nanley.g.chery(a)intel.com> Signed-off-by: Imre Deak <imre.deak(a)intel.com> --- include/uapi/drm/drm_fourcc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f1972154a5940..c1b4cfda75075 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -559,7 +559,7 @@ extern "C" { * * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear * and at index 1. The clear color is stored at index 2, and the pitch should - * be ignored. The clear color structure is 256 bits. The first 128 bits + * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits * represents Raw Clear Color Red, Green, Blue and Alpha color each represented * by 32 bits. The raw clear color is consumed by the 3d engine and generates * the converted clear color of size 64 bits. The first 32 bits store the Lower @@ -612,9 +612,9 @@ extern "C" { * outside of the GEM object in a reserved memory area dedicated for the * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The * main surface pitch is required to be a multiple of four Tile 4 widths. The - * clear color is stored at plane index 1 and the pitch should be ignored. The - * format of the 256 bits of clear color data matches the one used for the - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description + * clear color is stored at plane index 1 and the pitch should be 64 bytes + * aligned. The format of the 256 bits of clear color data matches the one used + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description * for details. */ #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) -- 2.30.2

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[PATCH v3 -next] drm/display: Fix build error without CONFIG_OF
by YueHaibing 23 Jun '22

23 Jun '22

While CONFIG_OF is n but COMPILE_TEST is y, we got this: WARNING: unmet direct dependencies detected for DRM_DP_AUX_BUS Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && OF [=n] Selected by [y]: - DRM_MSM [=y] && HAS_IOMEM [=y] && DRM [=y] && (ARCH_QCOM || SOC_IMX5 || COMPILE_TEST [=y]) && COMMON_CLK [=y] && IOMMU_SUPPORT [=y] && (QCOM_OCMEM [=n] || QCOM_OCMEM [=n]=n) && (QCOM_LLCC [=y] || QCOM_LLCC [=y]=n) && (QCOM_COMMAND_DB [=n] || QCOM_COMMAND_DB [=n]=n) Make DRM_DP_AUX_BUS depends on OF || COMPILE_TEST to fix this warning. Fixes: 1e0f66420b13 ("drm/display: Introduce a DRM display-helper module") Signed-off-by: YueHaibing <yuehaibing(a)huawei.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk(a)quicinc.com> Acked-by: Linus Walleij <linus.walleij(a)linaro.org> --- v3: use correct Fixes tag v2: fix this in DRM_DP_AUX_BUS dependencies --- drivers/gpu/drm/display/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/display/Kconfig b/drivers/gpu/drm/display/Kconfig index 1b6e6af37546..09712b88a5b8 100644 --- a/drivers/gpu/drm/display/Kconfig +++ b/drivers/gpu/drm/display/Kconfig @@ -3,7 +3,7 @@ config DRM_DP_AUX_BUS tristate depends on DRM - depends on OF + depends on OF || COMPILE_TEST config DRM_DISPLAY_HELPER tristate -- 2.17.1

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[PATCH -next] drm/logicvc: Fix error return code in logicvc_layer_init()
by Yang Yingliang 23 Jun '22

23 Jun '22

Fix error return code when logicvc_layer_formats_lookup() fails. Fixes: efeeaefe9be5 ("drm: Add support for the LogiCVC display controller") Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- drivers/gpu/drm/logicvc/logicvc_layer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/logicvc/logicvc_layer.c b/drivers/gpu/drm/logicvc/logicvc_layer.c index fbebe966f93a..54b5931d879f 100644 --- a/drivers/gpu/drm/logicvc/logicvc_layer.c +++ b/drivers/gpu/drm/logicvc/logicvc_layer.c @@ -489,6 +489,7 @@ static int logicvc_layer_init(struct logicvc_drm *logicvc, formats = logicvc_layer_formats_lookup(layer); if (!formats) { + ret = -EINVAL; drm_err(drm_dev, "Failed to lookup formats for layer #%d\n", index); goto error; -- 2.25.1

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[PATCH] drm: i915: fix a possible refcount leak in intel_dp_add_mst_connector()
by Hangyu Hua 23 Jun '22

23 Jun '22

If drm_connector_init fails, intel_connector_free will be called to take care of proper free. So it is necessary to drop the refcount of port before intel_connector_free. Fixes: 091a4f91942a ("drm/i915: Handle drm-layer errors in intel_dp_add_mst_connector") Signed-off-by: Hangyu Hua <hbh25y(a)gmail.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e30e698aa684..f7d46ea3afb9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -841,6 +841,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); if (ret) { + drm_dp_mst_put_port_malloc(port); intel_connector_free(intel_connector); return NULL; } -- 2.25.1

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dri-devel June 2022