dri-devel June 2022

dri-devel@lists.freedesktop.org

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697 discussions

[PATCH] drm/i915/dg2: Catch and log more unexpected values in DG1_MSTR_TILE_INTR
by Tvrtko Ursulin 07 Jun '22

07 Jun '22

From: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Catch and log any garbage in the register, including no tiles marked, or multiple tiles marked. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin(a)intel.com> Cc: Matt Roper <matthew.d.roper(a)intel.com> --- We caught garbage in DG1_MSTR_TILE_INTR with DG2 (actual value 0xF9D2C008) during glmark and more badness. So I thought lets log all possible failure modes from here and also use per device logging. --- drivers/gpu/drm/i915/i915_irq.c | 33 ++++++++++++++++++++++----------- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 73cebc6aa650..79853d3fc1ed 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2778,24 +2778,30 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) u32 gu_misc_iir; if (!intel_irqs_enabled(i915)) - return IRQ_NONE; + goto none; master_tile_ctl = dg1_master_intr_disable(regs); - if (!master_tile_ctl) { - dg1_master_intr_enable(regs); - return IRQ_NONE; + if (!master_tile_ctl) + goto enable_none; + + if (master_tile_ctl & ~(DG1_MSTR_IRQ | DG1_MSTR_TILE_MASK)) { + drm_warn(&i915->drm, "Garbage in master_tile_ctl: 0x%08x!\n", + master_tile_ctl); + goto enable_none; } /* FIXME: we only support tile 0 for now. */ - if (master_tile_ctl & DG1_MSTR_TILE(0)) { - master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); - raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); - } else { - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); - dg1_master_intr_enable(regs); - return IRQ_NONE; + if (REG_FIELD_GET(DG1_MSTR_TILE_MASK, master_tile_ctl) != + DG1_MSTR_TILE(0)) { + drm_warn(&i915->drm, "Unexpected irq from tile %u!\n", + ilog2(REG_FIELD_GET(DG1_MSTR_TILE_MASK, + master_tile_ctl))); + goto enable_none; } + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); + gen11_gt_irq_handler(gt, master_ctl); if (master_ctl & GEN11_DISPLAY_IRQ) @@ -2810,6 +2816,11 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) pmu_irq_stats(i915, IRQ_HANDLED); return IRQ_HANDLED; + +enable_none: + dg1_master_intr_enable(regs); +none: + return IRQ_NONE; } /* Called from drm generic code, passed 'crtc' which diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d8579ab9384c..eefa301c6430 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5774,6 +5774,7 @@ #define DG1_MSTR_TILE_INTR _MMIO(0x190008) #define DG1_MSTR_IRQ REG_BIT(31) +#define DG1_MSTR_TILE_MASK REG_GENMASK(3, 0) #define DG1_MSTR_TILE(t) REG_BIT(t) #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) -- 2.32.0

3 10

[PATCH v3 0/5] drm/ast: Connector cleanups and polling
by Thomas Zimmermann 07 Jun '22

07 Jun '22

Various cleanups to ast's connector code. Simplifies the code, adds support for using VGA and ASTDP connectors at the same time, and initializes polling of the connector status. Patch 1 was first posted at [1], so this patchset starts at version 2. The implementation of detect_ctx in patch 3 has been added to DRM helpers as it will be useful for other drivers, such as mgag200 and udl. v3: * clarify docs for .detext_ctx helper (Patrik) * use macros for TX-chip BITS() (Patrik) Thomas Zimmermann (5): drm/ast: Support multiple outputs drm/ast: Fix updating the connector's EDID property drm/ast: Support output polling drm/ast: Fail probing if DCC channel could not be initialized drm/ast: Remove struct ast_{vga,sil164}_connector drivers/gpu/drm/ast/ast_dp.c | 5 +- drivers/gpu/drm/ast/ast_dp501.c | 2 +- drivers/gpu/drm/ast/ast_drv.h | 35 ++---- drivers/gpu/drm/ast/ast_i2c.c | 7 +- drivers/gpu/drm/ast/ast_main.c | 21 ++-- drivers/gpu/drm/ast/ast_mode.c | 165 ++++++++++------------------- drivers/gpu/drm/ast/ast_post.c | 2 +- drivers/gpu/drm/drm_probe_helper.c | 40 +++++++ include/drm/drm_probe_helper.h | 3 + 9 files changed, 126 insertions(+), 154 deletions(-) base-commit: 6034ccb11971698ace6b3af2f6ac02de120a2dc2 -- 2.36.1

1 5

[PATCH v4 0/8] Add a panel API to return panel orientation
by Hsin-Yi Wang 07 Jun '22

07 Jun '22

Panels usually call drm_connector_set_panel_orientation(), which is later than drm/kms driver calling drm_dev_register(). This leads to a WARN()[1]. The orientation property is known earlier. For example, some panels parse the property through device tree during probe. The series add a panel API drm_panel_get_orientation() for drm/kms drivers. The drivers can use the API to get panel's orientation, so they can call drm_connector_set_panel_orientation() before drm_dev_register(). Panel needs to implement .get_orientation callback to return the property. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220530081910.39… Hsin-Yi Wang (8): drm/panel: Add an API drm_panel_get_orientation() to return panel orientation drm/panel: boe-tv101wum-nl6: Implement .get_orientation callback drm/panel: panel-edp: Implement .get_orientation callback drm/panel: lvds: Implement .get_orientation callback drm/panel: panel-simple: Implement .get_orientation callback drm/panel: ili9881c: Implement .get_orientation callback drm/panel: elida-kd35t133: Implement .get_orientation callback drm/mediatek: Config orientation property if panel provides it drivers/gpu/drm/drm_panel.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 14 ++++++++++++++ drivers/gpu/drm/panel/panel-edp.c | 15 ++++++++++++++- drivers/gpu/drm/panel/panel-elida-kd35t133.c | 14 ++++++++++++++ drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 14 ++++++++++++++ drivers/gpu/drm/panel/panel-lvds.c | 15 +++++++++++++++ drivers/gpu/drm/panel/panel-simple.c | 16 +++++++++++++++- include/drm/drm_panel.h | 10 ++++++++++ 9 files changed, 115 insertions(+), 2 deletions(-) -- 2.36.1.255.ge46751e96f-goog

4 21

[PATCH] drm/amdgpu: Fix reference leak in psp_xgmi_reflect_topology_info()
by Jianglei Nie 07 Jun '22

07 Jun '22

amdgpu_get_xgmi_hive() increases the kobject reference counter of the hive it returned. The hive returned by amdgpu_get_xgmi_hive() should be released with the help of amdgpu_put_xgmi_hive() to balance its kobject reference counter properly. Forgetting the amdgpu_put_xgmi_hive() operation will result in reference leak. We can fix it by calling amdgpu_put_xgmi_hive() before the end of the function. Signed-off-by: Jianglei Nie <niejianglei2021(a)163.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e9411c28d88b..7b3a78da1684 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1292,6 +1292,7 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp, break; } + amdgpu_put_xgmi_hive(hive); } int psp_xgmi_get_topology_info(struct psp_context *psp, -- 2.25.1

1 0

[PATCH v1 0/2] Add 1024x768 timing for AST2600
by Tommy Haung 07 Jun '22

07 Jun '22

v1: Add 1024x768@70Hz for AST2600 soc display timing selection. Add gfx flag for future usage. Testing steps: 1. Add below config to turn VT and LOGO on. CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LDISC_AUTOLOAD=y CONFIG_DEVMEM=y CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_CLUT224=y 2. The Linux logo will be shown on the screen, when the BMC boot in Linux. 3. Check the display mode is 1024x768@70Hz at AST2600. 4. Check the display mode is 800x600@60Hz at AST2500. Tommy Haung (2): drm/aspeed: Add gfx flags and clock selection for AST2600 drm/aspeed: Add 1024x768 mode for AST2600 drivers/gpu/drm/aspeed/aspeed_gfx.h | 15 ++++++++++ drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 35 ++++++++++++++++++++++++ drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 20 ++++++++++++-- drivers/gpu/drm/aspeed/aspeed_gfx_out.c | 14 +++++++++- 4 files changed, 81 insertions(+), 3 deletions(-) -- 2.17.1

3 7

[PATCH v2 0/2] drm/bridge: analogix_dp: Self-refresh state machine fixes
by Brian Norris 07 Jun '22

07 Jun '22

Hi, I've been investigating several eDP issues on a Rockchip RK3399 system and have two proposed bugfixes. RK3399 has two CRTCs, either of which can be used for eDP output. For both fixes, we have bugs due to the relationship between the generalized "self refresh helpers" and the analogix-dp bridge driver which controls much of the PSR mechanics. These bugs are most visible when switching between CRTCs. I'm not a DRM expert, but I've been poking at a lot of Rockchip display drivers recently. I'd love some skeptical eyes, so feel free to ask questions if I haven't explained issues well, or the proposals look fishy. Regards, Brian Changes in v2: - Drop "->enable" condition in crtc_needs_disable(); this could possibly be "->active" to reflect the intended hardware state, but it also is a little over-specific. We want to make a transition through "disabled" any time we're exiting PSR at the same time as a CRTC switch. (Thanks Liu Ying) Brian Norris (2): drm/bridge: analogix_dp: Support PSR-exit to disable transition drm/atomic: Force bridge self-refresh-exit on CRTC switch .../drm/bridge/analogix/analogix_dp_core.c | 42 +++++++++++++++++-- drivers/gpu/drm/drm_atomic_helper.c | 16 +++++-- 2 files changed, 51 insertions(+), 7 deletions(-) -- 2.35.1.574.g5d30c73bfb-goog

4 9

[PATCH 0/2] Remove the VFIO_IOMMU_NOTIFY_DMA_UNMAP notifier
by Jason Gunthorpe 07 Jun '22

07 Jun '22

This is the last notifier toward the drivers, replace it with a simple op callback in the vfio_device_ops. Jason Gunthorpe (2): vfio: Replace the DMA unmapping notifier with a callback vfio: Replace the iommu notifier with a device list drivers/gpu/drm/i915/gvt/gvt.h | 1 - drivers/gpu/drm/i915/gvt/kvmgt.c | 75 +++++------------- drivers/s390/cio/vfio_ccw_ops.c | 41 +++------- drivers/s390/cio/vfio_ccw_private.h | 1 - drivers/s390/crypto/vfio_ap_ops.c | 54 +++---------- drivers/s390/crypto/vfio_ap_private.h | 3 - drivers/vfio/vfio.c | 105 +++++--------------------- drivers/vfio/vfio.h | 9 +-- drivers/vfio/vfio_iommu_type1.c | 74 ++++++++++-------- include/linux/vfio.h | 21 +----- 10 files changed, 114 insertions(+), 270 deletions(-) base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56 -- 2.36.1

1 2

[PATCH] drm/sun4i: sun8i: Add support for pixel blend mode property
by Roman Stratiienko 06 Jun '22

06 Jun '22

Allwinner DE2 and DE3 hardware support 3 pixel blend modes: "None", "Pre-multiplied", "Coverage" Add the blend mode property and route it to the appropriate registers. Note: "force_premulti" parameter was added to handle multi-overlay channel cases in future changes. It must be set to true for cases when more than 1 overlay layer is used within a channel and at least one of the overlay layers within a group uses premultiplied blending mode. Test: Manually tested all the modes using kmsxx python wrapper with and without 'force_premulti' flag enabled. Signed-off-by: Roman Stratiienko <roman.o.stratiienko(a)globallogic.com> --- drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 48 ++++++++++++++++++++----- drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 5 +++ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 49 ++++++++++++++++++++++---- drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 5 +++ 5 files changed, 94 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index ebfc276b2464..5c05907e26fb 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -65,6 +65,8 @@ #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2)) #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2) +#define SUN8I_MIXER_BLEND_PREMULTIPLY_EN(pipe) BIT(pipe) + #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1) #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch) BIT(ch) diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 6ccbbca3176d..29c0d9cca19a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -58,24 +58,46 @@ static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, } static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, - int overlay, struct drm_plane *plane) + int overlay, struct drm_plane *plane, + unsigned int zpos, bool force_premulti) { - u32 mask, val, ch_base; + u32 mask, val, ch_base, bld_base; + bool in_premulti, out_premulti; + bld_base = sun8i_blender_base(mixer); ch_base = sun8i_channel_base(mixer, channel); + in_premulti = plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI; + out_premulti = force_premulti || in_premulti; + mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK | - SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK; + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK | + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_MASK; val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA(plane->state->alpha >> 8); - val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? - SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_PIXEL : - SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED; + if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { + val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_LAYER; + } else { + val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_PIXEL : + SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED; + + if (in_premulti) + val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_PREMULTI; + } + + if (!in_premulti && out_premulti) + val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_COV2PREM; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), mask, val); + + regmap_update_bits( + mixer->engine.regs, SUN8I_MIXER_BLEND_PREMULTIPLY(bld_base), + SUN8I_MIXER_BLEND_PREMULTIPLY_EN(zpos), + out_premulti ? SUN8I_MIXER_BLEND_PREMULTIPLY_EN(zpos) : 0); } static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -274,7 +296,7 @@ static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, sun8i_ui_layer_update_coord(mixer, layer->channel, layer->overlay, plane, zpos); sun8i_ui_layer_update_alpha(mixer, layer->channel, - layer->overlay, plane); + layer->overlay, plane, zpos, false); sun8i_ui_layer_update_formats(mixer, layer->channel, layer->overlay, plane); sun8i_ui_layer_update_buffer(mixer, layer->channel, @@ -332,8 +354,8 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, { enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; int channel = mixer->cfg->vi_num + index; + unsigned int plane_cnt, blend_modes; struct sun8i_ui_layer *layer; - unsigned int plane_cnt; int ret; layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); @@ -362,6 +384,16 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, return ERR_PTR(ret); } + blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE); + + ret = drm_plane_create_blend_mode_property(&layer->plane, blend_modes); + if (ret) { + dev_err(drm->dev, "Couldn't add blend mode property\n"); + return ERR_PTR(ret); + } + ret = drm_plane_create_zpos_property(&layer->plane, channel, 0, plane_cnt - 1); if (ret) { diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h index 43c48cf7bc51..bd3c30e8058d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h @@ -46,6 +46,11 @@ #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_LAYER ((1) << 1) #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED ((2) << 1) +#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_MASK GENMASK(17, 16) +#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_COVERAGE ((0) << 16) +#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_COV2PREM ((1) << 16) +#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_BLEND_PREMULTI ((2) << 16) + struct sun8i_mixer; struct sun8i_ui_layer { diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index 662ba1018cc4..6581fc7d9668 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -52,21 +52,38 @@ static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel, } static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, - int overlay, struct drm_plane *plane) + int overlay, struct drm_plane *plane, + unsigned int zpos, bool force_premulti) { - u32 mask, val, ch_base; + u32 mask, val, ch_base, bld_base; + bool in_premulti = false, out_premulti = false; ch_base = sun8i_channel_base(mixer, channel); + bld_base = sun8i_blender_base(mixer); if (mixer->cfg->is_de3) { + in_premulti = plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI; + out_premulti = force_premulti || in_premulti; + mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK | - SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK; + SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK | + SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_MASK; val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA (plane->state->alpha >> 8); - val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? - SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL : - SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED; + if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) { + val |= SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_LAYER; + } else { + val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? + SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL : + SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED; + + if (in_premulti) + val |= SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_PREMULTI; + } + + if (!in_premulti && out_premulti) + val |= SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_COV2PREM; regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, @@ -79,6 +96,11 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, SUN8I_MIXER_FCC_GLOBAL_ALPHA (plane->state->alpha >> 8)); } + + regmap_update_bits( + mixer->engine.regs, SUN8I_MIXER_BLEND_PREMULTIPLY(bld_base), + SUN8I_MIXER_BLEND_PREMULTIPLY_EN(zpos), + out_premulti ? SUN8I_MIXER_BLEND_PREMULTIPLY_EN(zpos) : 0); } static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, @@ -408,7 +430,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane, sun8i_vi_layer_update_coord(mixer, layer->channel, layer->overlay, plane, zpos); sun8i_vi_layer_update_alpha(mixer, layer->channel, - layer->overlay, plane); + layer->overlay, plane, zpos, false); sun8i_vi_layer_update_formats(mixer, layer->channel, layer->overlay, plane); sun8i_vi_layer_update_buffer(mixer, layer->channel, @@ -563,6 +585,19 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm, } } + if (mixer->cfg->is_de3) { + unsigned int blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE); + + ret = drm_plane_create_blend_mode_property(&layer->plane, + blend_modes); + if (ret) { + dev_err(drm->dev, "Couldn't add blend mode property\n"); + return ERR_PTR(ret); + } + } + ret = drm_plane_create_zpos_property(&layer->plane, index, 0, plane_cnt - 1); if (ret) { diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h index 9939a4cc7a52..ccf91f09f1fe 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h @@ -44,6 +44,11 @@ #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24) #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(x) ((x) << 24) +#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_MASK GENMASK(17, 16) +#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_COVERAGE ((0) << 16) +#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_COV2PREM ((1) << 16) +#define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_BLEND_PREMULTI ((2) << 16) + #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL ((0) << 1) #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_LAYER ((1) << 1) #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED ((2) << 1) -- 2.30.2

3 6

[PATCH] drm/msm: Fix double pm_runtime_disable() call
by Maximilian Luz 06 Jun '22

06 Jun '22

Following commit 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}"), any call to adreno_unbind() will disable runtime PM twice, as indicated by the call trees below: adreno_unbind() -> pm_runtime_force_suspend() -> pm_runtime_disable() adreno_unbind() -> gpu->funcs->destroy() [= aNxx_destroy()] -> adreno_gpu_cleanup() -> pm_runtime_disable() Note that pm_runtime_force_suspend() is called right before gpu->funcs->destroy() and both functions are called unconditionally. With recent addition of the eDP AUX bus code, this problem manifests itself when the eDP panel cannot be found yet and probing is deferred. On the first probe attempt, we disable runtime PM twice as described above. This then causes any later probe attempt to fail with [drm:adreno_load_gpu [msm]] *ERROR* Couldn't power up the GPU: -13 preventing the driver from loading. As there seem to be scenarios where the aNxx_destroy() functions are not called from adreno_unbind(), simply removing pm_runtime_disable() from inside adreno_unbind() does not seem to be the proper fix. This is what commit 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}") intended to fix. Therefore, instead check whether runtime PM is still enabled, and only disable it in that case. Fixes: 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in adreno_gpu_{init, cleanup}") Signed-off-by: Maximilian Luz <luzmaximilian(a)gmail.com> --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 4e665c806a14..f944b69e2a25 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1057,7 +1057,8 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) release_firmware(adreno_gpu->fw[i]); - pm_runtime_disable(&priv->gpu_pdev->dev); + if (pm_runtime_enabled(&priv->gpu_pdev->dev)) + pm_runtime_disable(&priv->gpu_pdev->dev); msm_gpu_cleanup(&adreno_gpu->base); } -- 2.36.1

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[PATCH v4] drm/probe-helper: Default to 640x480 if no EDID on DP
by Douglas Anderson 06 Jun '22

06 Jun '22

If we're unable to read the EDID for a display because it's corrupt / bogus / invalid then we'll add a set of standard modes for the display. Since we have no true information about the connected display, these modes are essentially guesses but better than nothing. At the moment, none of the modes returned is marked as preferred, but the modes are sorted such that the higher resolution modes are listed first. When userspace sees these modes presented by the kernel it needs to figure out which one to pick. At least one userspace, ChromeOS [1] seems to use the rules (which seem pretty reasonable): 1. Try to pick the first mode marked as preferred. 2. Try to pick the mode which matches the first detailed timing descriptor in the EDID. 3. If no modes were marked as preferred then pick the first mode. Unfortunately, userspace's rules combined with what the kernel is doing causes us to fail section 4.2.2.6 (EDID Corruption Detection) of the DP 1.4a Link CTS. That test case says that, while it's OK to allow some implementation-specific fall-back modes if the EDID is bad that userspace should _default_ to 640x480. Let's fix this by marking 640x480 as default for DP in the no-EDID case. NOTES: - In the discussion around v3 of this patch [2] there was talk about solving this in userspace and I even implemented a patch that would have solved this for ChromeOS, but then the discussion turned back to solving this in the kernel. - Also in the discussion of v3 [2] it was requested to limit this 83;40900;0c change to just DP since folks were worried that it would break some subtle corner case on VGA or HDMI. [1] https://source.chromium.org/chromium/chromium/src/+/a051f741d0a15caff225130… [2] https://lore.kernel.org/r/20220513130533.v3.1.I31ec454f8d4ffce51a7708a8092f… Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk(a)quicinc.com> --- I put Abhinav's Reviewed-by tag from v2 here since this is nearly the same as v2. Hope this is OK. Changes in v4: - Code is back to v2, but limit to just DP. - Beefed up the commit message. Changes in v3: - Don't set preferred, just disable the sort. Changes in v2: - Don't modify drm_add_modes_noedid() 'cause that'll break others - Set 640x480 as preferred in drm_helper_probe_single_connector_modes() drivers/gpu/drm/drm_probe_helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index 425f56280d51..75a71649b64d 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -569,8 +569,17 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, count = drm_add_override_edid_modes(connector); if (count == 0 && (connector->status == connector_status_connected || - connector->status == connector_status_unknown)) + connector->status == connector_status_unknown)) { count = drm_add_modes_noedid(connector, 1024, 768); + + /* + * Section 4.2.2.6 (EDID Corruption Detection) of the DP 1.4a + * Link CTS specifies that 640x480 (the official "failsafe" + * mode) needs to be the default if there's no EDID. + */ + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) + drm_set_preferred_mode(connector, 640, 480); + } count += drm_helper_probe_add_cmdline_mode(connector); if (count != 0) { ret = __drm_helper_update_and_validate(connector, maxX, maxY, &ctx); -- 2.36.1.255.ge46751e96f-goog

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dri-devel June 2022