On Thu, Jul 09, 2020 at 07:47:32PM +0300, Laurentiu Palcu wrote:
From: Laurentiu Palcu laurentiu.palcu@nxp.com
Add bindings for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu laurentiu.palcu@nxp.com
.../bindings/display/imx/nxp,imx8mq-dcss.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml new file mode 100644 index 000000000000..a951409cf76d --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+title: iMX8MQ Display Controller Subsystem (DCSS)
+maintainers:
- Laurentiu Palcu laurentiu.palcu@nxp.com
+description:
- The DCSS (display controller sub system) is used to source up to three
- display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
- 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
- image processing capabilities are included to provide a solution capable of
- driving next generation high dynamic range displays.
+properties:
- compatible:
- const: nxp,imx8mq-dcss
- reg:
- items:
- description: DCSS base address and size, up to IRQ steer start- description: DCSS BLKCTL base address and size- interrupts:
- items:
- description: Context loader completion and error interrupt- description: DTG interrupt used to signal context loader trigger time- description: DTG interrupt for Vblank- interrupt-names:
- items:
- const: ctxld- const: ctxld_kick- const: vblank- clocks:
- items:
- description: Display APB clock for all peripheral PIO access interfaces- description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL- description: RTRAM clock- description: Pixel clock, can be driver either by HDMI phy clock or MIPI- description: DTRC clock, needed by video decompressor- clock-names:
- items:
- const: apb- const: axi- const: rtrm- const: pix- const: dtrc- port:
- type: object
- description:
A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
additionalProperties: false
With that,
Reviewed-by: Rob Herring robh@kernel.org