On Tue, Jun 10, 2014 at 05:14:21PM +0100, Russell King - ARM Linux wrote:
On Tue, Jun 10, 2014 at 04:13:06PM +0100, Russell King - ARM Linux wrote:
where 'M' is the IPU DI clock muxer. However, we're currently setting this up as:
LM --+---------------- LDB serial `- /7 -+-------- LDB DI clock IPM --- /N ---- IM --- IPU DI clock
and hoping that the LDB and IPU DI clocks are appropriately synchronised.
I've just found that we do indeed do this - but there's nothing to switch the configuration back when the LDB is no longer using a particular DI.
Also, I'm having a hard time working out why we have the LDB being given all sorts of clocks...
LM --+----------------- LDB serial (clks 33, aka di0_pll) `- /7 -+--------- LDB DI clock (clks 135, aka di0) `- IM --- IPU DI clock (clks 39, aka di0_sel)
The LDB is given all of these to play with, including reprogramming the IM, and there's nothing which ever programs IM to anything but the LDB DI clock once it's set there.
*Sigh*... is the clock tree represented in Linux even correct?
--|\ --| | --| |------------------+----------------------------------------- --| | ^ ldb_di0_sel | --|/ (clks 33) | `-- /3.5 ---- /2 ------------------ G -+-- ^ ^ ldb_di0_podf | ^ ldb_di0 ldb_di0_div_3_5 | .----------------------' | '------|\ (ldb_di1)------------| | (ipp_di0)------------| |--------- G ---- (ipp_di1)------------| | ^ ^ ipu1_di0 (ipu1_di0_pre)------------|/ ipu1_di0_sel
This diagram is drawn from the code in clk-imx6.c, and it does not agree with what is in the SoC manuals - this is the representation redrawn from the manuals:
--|\ --| | --| |------------------+---------------------------------- G ---- --| | ^ ldb_di0_sel | ^ ldb serial --|/ (clks 33) | `-- /3.5 ---- /2 -----------------+------- ^ ^ ldb_di0_podf | ^ ldb di ldb_di0_div_3_5 | .-----------------' | '------|\ (ldb_di1)------------| | (ipp_di0)------------| |--------- G ---- (ipp_di1)------------| | ^ ^ ipu1_di0 (ipu1_di0_pre)------------|/ ipu1_di0_sel
The difference is, there is no clock gate between the LDB DI clock and the /7 divider, but there is a clock gate on the LDB serial clock.
In another location, the iMX6QDL manual suggests that it may be more like this:
--|\ --| | --| |----------- cg ---+----------------------------------------- --| | ^ ldb_di0_sel | ^ ldb serial --|/ (clks 33) | `-- /3.5 ---- /2 -----------------+------- ^ ^ ldb_di0_podf | ^ ldb di ldb_di0_div_3_5 | .-----------------' | '------|\ (ldb_di1)------------| | (ipp_di0)------------| |---------------- (ipp_di1)------------| | ^ ^ ipu1_di0 (ipu1_di0_pre)-- cg ------|/ ipu1_di0_sel
although "cg" is not defined what it is. Another place seems to confirm the above diagram, saying that the "ldb_di0_clk_enable" gating bits controls both "ch_0_serial_clk" (presumably the ldb serial clock) and "di_0_clk_nc" (presumably the ldb di clock. If that's correct "cg" refers to the clock gating via the CCM_CCGR registers, which appear in the CCM clock tree diagram under LPCG.
So... I wonder which one of these three is actually the right one...