This adds the device nodes for 2D, 3D and VG GPU cores.
Signed-off-by: Lucas Stach l.stach@pengutronix.de --- arch/arm/boot/dts/imx6dl.dtsi | 5 +++++ arch/arm/boot/dts/imx6q.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/imx6qdl.dtsi | 19 +++++++++++++++++++ 3 files changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index f94bf72832af..188a2cfb3073 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -104,6 +104,11 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>; + }; };
&hdmi { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 93ec79bb6b35..94518103c544 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -153,6 +153,15 @@ status = "disabled"; };
+ gpu_vg: gpu@02204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + }; + ipu2: ipu@02800000 { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +234,11 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; + }; };
&hdmi { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d6c69ec44314..6fcd1138b532 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -118,6 +118,25 @@ status = "disabled"; };
+ gpu_3d: gpu@00130000 { + compatible = "vivante,gc"; + reg = <0x00130000 0x4000>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "bus", "core", "shader"; + }; + + gpu_2d: gpu@00134000 { + compatible = "vivante,gc"; + reg = <0x00134000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>; + clock-names = "bus", "core"; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>;