Hi Daniel,
Am Dienstag, den 02.02.2016, 16:10 +0800 schrieb Daniel Kurtz:
On Tue, Jan 5, 2016 at 1:36 AM, Philipp Zabel p.zabel@pengutronix.de wrote:
From: CK Hu ck.hu@mediatek.com
This patch adds the device nodes for the DISP function blocks comprising the display subsystem.
Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Cawa Cheng cawa.cheng@mediatek.com Signed-off-by: Jie Qiu jie.qiu@mediatek.com Signed-off-by: Daniel Kurtz djkurtz@chromium.org Signed-off-by: Philipp Zabel p.zabel@pengutronix.de
Changes since v7:
- Add 26 MHz PLL reference input clock and the high-speed output clock to the MIPI TX D-PHY nodes
- The HS output clock is routed to the DSI encoder module
- Add power-domains property to all nodes in the MM domain
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 237 +++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4901f13..68c1cb2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -25,6 +25,23 @@
[...]
dpi0: dpi@1401d000 {compatible = "mediatek,mt8173-dpi";reg = <0 0x1401d000 0 0x1000>;interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;clocks = <&mmsys CLK_MM_DPI_PIXEL>,<&mmsys CLK_MM_DPI_ENGINE>,<&apmixedsys CLK_APMIXED_TVDPLL>;clock-names = "pixel", "engine", "pll";port {dpi0_out: endpoint {remote-endpoint = <&hdmi0_in>;nit: At this point in the patch series, you haven't defined hdmi0_in yet. Move this port to "Add HDMI related nodes".
Thanks, will do in v10.
regards Philipp