We get 10 warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:65:6: warning: no previous prototype for 'cz_phm_is_safe_for_asic_block' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:71:5: warning: no previous prototype for 'cz_phm_enable_disable_gfx_power_gating' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:76:5: warning: no previous prototype for 'cz_phm_smu_power_up_down_pcie' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:82:5: warning: no previous prototype for 'cz_phm_initialize_display_phy_access' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:88:5: warning: no previous prototype for 'cz_phm_get_display_phy_access_info' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:94:5: warning: no previous prototype for 'cz_phm_gate_unused_display_phys' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:100:5: warning: no previous prototype for 'cz_phm_ungate_all_display_phys' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1278:5: warning: no previous prototype for 'smu7_disable_dpm_tasks' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:1336:5: warning: no previous prototype for 'smu7_reset_asic_tasks' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../powerplay/eventmgr/eventtasks.c:322:5: warning: no previous prototype for 'pem_task_enable_clock_power_gating' [-Wmissing-prototypes]
In fact, these functions are called by no one and not exported, so this patch removes them.
Signed-off-by: Baoyou Xie baoyou.xie@linaro.org --- .../gpu/drm/amd/powerplay/eventmgr/eventtasks.c | 7 - .../drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 42 ----- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 206 --------------------- .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 59 ------ .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h | 2 - 5 files changed, 316 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c index b6f45fd..03e5c02 100644 --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c @@ -319,13 +319,6 @@ int pem_task_disable_cgpg(struct pp_eventmgr *eventmgr, struct pem_event_data *e return 0; }
-int pem_task_enable_clock_power_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) -{ - /* TODO */ - return 0; -} - - int pem_task_enable_gfx_clock_gating(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) { /* TODO */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c index 2028980..0966fc8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c @@ -61,48 +61,6 @@ int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock bloc return ret; }
- -bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block) -{ - return true; -} - - -int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable) -{ - return 0; -} - -int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args) -{ - /* TODO */ - return 0; -} - -int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw) -{ - /* TODO */ - return 0; -} - -int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - -int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - -int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr) -{ - /* TODO */ - return 0; -} - static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result) { return 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 649fdd3..1c85925 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -409,34 +409,6 @@ static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) return 0; }
-static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) -{ - /* Reset voting clients before disabling DPM */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); - - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_0, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_1, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_2, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_3, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_4, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_5, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_6, 0); - cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_FREQ_TRAN_VOTING_7, 0); - - return 0; -} - /* Copy one arb setting to another and then switch the active set. * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. */ @@ -486,11 +458,6 @@ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, return 0; }
-static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) -{ - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); -} - /** * Initial switch from ARB F0->F1 * @@ -504,21 +471,6 @@ static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); }
-static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) -{ - uint32_t tmp; - - tmp = (cgs_read_ind_register(hwmgr->device, - CGS_IND_REG__SMC, ixSMC_SCRATCH9) & - 0x0000ff00) >> 8; - - if (tmp == MC_CG_ARB_FREQ_F0) - return 0; - - return smu7_copy_and_switch_arb_sets(hwmgr, - tmp, MC_CG_ARB_FREQ_F0); -} - static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -873,16 +825,6 @@ static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) return 0; }
-static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->ulv_supported) - return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV); - - return 0; -} - static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -903,21 +845,6 @@ static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) return 0; }
-static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) -{ - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep)) { - if (smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_MASTER_DeepSleep_OFF)) { - PP_ASSERT_WITH_CODE(false, - "Attempt to disable Master Deep Sleep switch failed!", - return -EINVAL); - } - } - - return 0; -} - static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -1025,58 +952,6 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr) return 0; }
-static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* disable SCLK dpm */ - if (!data->sclk_dpm_key_disabled) - PP_ASSERT_WITH_CODE( - (smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_DPM_Disable) == 0), - "Failed to disable SCLK DPM!", - return -EINVAL); - - /* disable MCLK dpm */ - if (!data->mclk_dpm_key_disabled) { - PP_ASSERT_WITH_CODE( - (smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_Disable) == 0), - "Failed to disable MCLK DPM!", - return -EINVAL); - } - - return 0; -} - -static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - /* disable general power management */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, - GLOBAL_PWRMGT_EN, 0); - /* disable sclk deep sleep */ - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, - DYNAMIC_PM_EN, 0); - - /* disable PCIE dpm */ - if (!data->pcie_dpm_key_disabled) { - PP_ASSERT_WITH_CODE( - (smum_send_msg_to_smc(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_Disable) == 0), - "Failed to disable pcie DPM during DPM Stop Function!", - return -EINVAL); - } - - if (smu7_disable_sclk_mclk_dpm(hwmgr)) { - printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!"); - return -EINVAL; - } - - return 0; -} - static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) { bool protection; @@ -1134,23 +1009,6 @@ static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); }
-static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, - PHM_AutoThrottleSource source) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - - if (data->active_auto_throttle_sources & (1 << source)) { - data->active_auto_throttle_sources &= ~(1 << source); - smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); - } - return 0; -} - -static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) -{ - return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); -} - static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -1275,70 +1133,6 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) return 0; }
-int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) -{ - int tmp_result, result = 0; - - tmp_result = (smum_is_dpm_running(hwmgr)) ? 0 : -1; - PP_ASSERT_WITH_CODE(tmp_result == 0, - "DPM is not running right now, no need to disable DPM!", - return 0); - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_ThermalController)) - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); - - tmp_result = smu7_disable_power_containment(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable power containment!", result = tmp_result); - - tmp_result = smu7_disable_smc_cac(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable SMC CAC!", result = tmp_result); - - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); - PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, - GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); - - tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable thermal auto throttle!", result = tmp_result); - - tmp_result = smu7_stop_dpm(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to stop DPM!", result = tmp_result); - - tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable deep sleep master switch!", result = tmp_result); - - tmp_result = smu7_disable_ulv(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to disable ULV!", result = tmp_result); - - tmp_result = smu7_clear_voting_clients(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to clear voting clients!", result = tmp_result); - - tmp_result = smu7_reset_to_default(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to reset to default!", result = tmp_result); - - tmp_result = smu7_force_switch_to_arbf0(hwmgr); - PP_ASSERT_WITH_CODE((tmp_result == 0), - "Failed to force to switch arbf0!", result = tmp_result); - - return result; -} - -int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr) -{ - - return 0; -} - static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c index 260fce050..77d79b4 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c @@ -575,23 +575,6 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) return result; }
-int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int result = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_CAC) && data->cac_enabled) { - int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_DisableCac)); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable CAC in SMC.", result = -1); - - data->cac_enabled = false; - } - return result; -} - int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); @@ -657,48 +640,6 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) return result; }
-int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) -{ - struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); - int result = 0; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_PowerContainment) && - data->power_containment_features) { - int smc_result; - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_TDCLimit) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_TDCLimitDisable)); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable TDCLimit in SMC.", - result = smc_result); - } - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_DTE) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_DisableDTE)); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable DTE in SMC.", - result = smc_result); - } - - if (data->power_containment_features & - POWERCONTAINMENT_FEATURE_PkgPwrLimit) { - smc_result = smum_send_msg_to_smc(hwmgr->smumgr, - (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable)); - PP_ASSERT_WITH_CODE((smc_result == 0), - "Failed to disable PkgPwrTracking in SMC.", - result = smc_result); - } - data->power_containment_features = 0; - } - - return result; -} - int smu7_power_control_set_level(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *table_info = diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h index 22f86b6..e995fd3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h @@ -51,9 +51,7 @@
int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr); -int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr); int smu7_enable_power_containment(struct pp_hwmgr *hwmgr); -int smu7_disable_power_containment(struct pp_hwmgr *hwmgr); int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); int smu7_power_control_set_level(struct pp_hwmgr *hwmgr); int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);