This patch adds the bindings for the Page-based Address Translator (PAT) present on various TI SoCs. A Page-based Address Translator (PAT) device performs address translation using tables stored in an internal SRAM. Each PAT supports a set number of pages, each occupying a programmable 4KB, 16KB, 64KB, or 1MB of addresses in a window for which an incoming transaction will be translated.
Signed-off-by: Andrew F. Davis afd@ti.com --- .../devicetree/bindings/misc/ti,pat.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/ti,pat.txt
diff --git a/Documentation/devicetree/bindings/misc/ti,pat.txt b/Documentation/devicetree/bindings/misc/ti,pat.txt new file mode 100644 index 000000000000..fac20d45ad4c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,pat.txt @@ -0,0 +1,34 @@ +Texas Instruments Page-based Address Translator (PAT) driver binding +-------------------------------------------------------------------- + +A Page-based Address Translator (PAT) device performs address translation +using tables stored in an internal SRAM. Each PAT supports a set number of +pages, each occupying a programmable 4KB, 16KB, 64KB, or 1MB of addresses +in a window for which an incoming transaction will be translated. + +TI-PAT controller Device Node +============================= + +The TI-PAT node describes the Texas Instrument's Page-based Address +Translator (PAT). + +Required properties: +------------------- +- compatible: should be "ti,j721e-pat" +- reg-names: + mmrs - Memory mapped registers region + table - Location of the table of translation pages + window - Window of memory addresses translated by this PAT +- reg: register addresses corresponding to the above + +Example: + +navss_pat0: pat@31010000 { + compatible = "ti,j721e-pat"; + reg = <0x00 0x31010000 0x00 0x00000100>, + <0x00 0x36400000 0x00 0x00040000>, + <0x48 0x00000000 0x00 0x40000000>; + reg-names = "mmrs", + "table", + "window"; +};