Hi Biju,
On Mon, Mar 28, 2022 at 8:49 AM Biju Das biju.das.jz@bp.renesas.com wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
Thanks for your patch!
--- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the Renesas
- RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
- up to four data lanes.
+allOf:
- $ref: /schemas/display/dsi-controller.yaml#
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
Do you want to define SoC-specific compatible values, or can the IP revision be read from the hardware?
The rest LGTM (I'm no MIPI-DSI expert), so Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds