Hi Laurent,
On Thu, 2022-06-09 at 12:32 +0300, Laurent Pinchart wrote:
Hi Liu,
On Thu, Jun 09, 2022 at 02:49:17PM +0800, Liu Ying wrote:
Hi,
This is the v8 series to add some DRM bridge drivers support for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support LVDS displays. The relevant display controller is DPU embedded in i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork....
This series supports the following display pipes:
- i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)
- i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)
Patch 1/14 and 2/14 add bus formats used by pixel combiner.
Patch 9/14 adds a helper for LDB bridge drivers.
Patch 3/14 ~ 8/14 and 10/14 ~ 12/14 add drm bridge drivers and dt-bindings support for the bridges.
Patch 13/14 adds dt-binding for Control and Status Registers module(a syscon used by PXL2DPI and LDB), which references the PXL2DPI and LDB schemas.
Patch 14/14 updates MAINTAINERS.
I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and a LVDS to HDMI bridge(with a downstream drm bridge driver).
Marcel Ziswiler has tested v6 with two LVDS panels(single link LT170410-2WHC and dual link LP156WF1) on Toradex Colibri iMX8X.
Welcome comments, thanks.
I'm not sure if this comment will be welcome, but what's the reason to handle the pixel combiner and pixel link (DPL) as bridges ? They seem very tightly couple with the display controller, wouldn't it be better to handle them in the display controller driver ?
i.MX8qxp display controller, pixel combiner and pixel link are standalone IPs. i.MX8qxp reference manual has separate chapters for them. Not sure if pixel combiner and/or pixel link will be used to work with other display controllers in future SoCs. So, it looks appropriate to take them as separate bridges.
Regards, Liu Ying