Re: [Intel-gfx] [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats

On Thu, Aug 30, 2018 at 03:41:13PM +0300, Juha-Pekka Heikkila wrote:

Preparations for enabling P010, P012 and P016 formats. These formats will extend NV12 for larger bit depths.

(Sharma, Swati2): removed unnecessary checks, changed debug error message to be more generic.

Signed-off-by: Juha-Pekka Heikkila juhapekka.heikkila@gmail.com

drivers/gpu/drm/i915/intel_atomic.c | 3 +-- drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 41 +++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 19 +++++++------- drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++++- 6 files changed, 63 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index b04952b..ab76b72 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* set scaler mode */ if ((INTEL_GEN(dev_priv) >= 9) && plane_state && plane_state->base.fb &&

•     plane_state->base.fb->format->format ==
  

•     DRM_FORMAT_NV12) {
  

•     is_planar_yuv_format(plane_state->base.fb->format->format)) {
  

Since there is .is_yuv now it might make sense to stick this into some common place (drm_fourcc.h perhaps) as something like 'is_yuv && num_planes > 1'

	if (INTEL_GEN(dev_priv) == 9 &&
	    !IS_GEMINILAKE(dev_priv) &&
	    !IS_SKYLAKE(dev_priv))

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index fa7df5f..d64d993 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -184,7 +184,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ else crtc_state->active_planes &= ~BIT(intel_plane->id);

• if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)

• if (state->visible && is_planar_yuv_format(state->fb->format->format)) crtc_state->nv12_planes |= BIT(intel_plane->id); else crtc_state->nv12_planes &= ~BIT(intel_plane->id);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4bb46f2..43efeb4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2672,6 +2672,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12;

• case PLANE_CTL_FORMAT_P010:

• return DRM_FORMAT_P010;
  

• case PLANE_CTL_FORMAT_P012:

• return DRM_FORMAT_P012;
  

• case PLANE_CTL_FORMAT_P016:

• return DRM_FORMAT_P016;
  

  default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) {

@@ -3187,7 +3193,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state, * Handle the AUX surface first since * the main surface setup depends on it. */

• if (fb->format->format == DRM_FORMAT_NV12) {

• if (is_planar_yuv_format(fb->format->format)) { ret = skl_check_nv12_surface(crtc_state, plane_state); if (ret) return ret;

@@ -3511,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12;

• case DRM_FORMAT_P010:

• return PLANE_CTL_FORMAT_P010;
  

• case DRM_FORMAT_P012:

• return PLANE_CTL_FORMAT_P012;
  

• case DRM_FORMAT_P016:

• return PLANE_CTL_FORMAT_P016;
  

  default: MISSING_CASE(pixel_format); }

@@ -4812,8 +4824,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, need_scaling = src_w != dst_w || src_h != dst_h;

if (plane_scaler_check)

• if (pixel_format == DRM_FORMAT_NV12)
  

• 	need_scaling = true;
  

• need_scaling = is_planar_yuv_format(pixel_format);
  
  

  if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) need_scaling = true;

@@ -4854,9 +4865,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; }

• if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&

• if (plane_scaler_check && is_planar_yuv_format(pixel_format) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {

• DRM_DEBUG_KMS("NV12: src dimensions not met\n");
  

• DRM_DEBUG_KMS("planar yuv: src dimensions not met\n");
  

  return -EINVAL; }

@@ -4959,6 +4970,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12:

• case DRM_FORMAT_P010:
• case DRM_FORMAT_P012:
• case DRM_FORMAT_P016: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",

@@ -13182,7 +13196,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, * or * cdclk/crtc_clock */

• mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;

• mult = is_planar_yuv_format(pixel_format) ? 2 : 3; tmpclk1 = (1 << 16) * mult - 1; tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock); max_scale = min(tmpclk1, tmpclk2);

@@ -13413,6 +13427,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12:

• case DRM_FORMAT_P010:
• case DRM_FORMAT_P012:
• case DRM_FORMAT_P016: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */

@@ -14556,6 +14573,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err; } break;

• case DRM_FORMAT_P010:
• case DRM_FORMAT_P012:
• case DRM_FORMAT_P016:

• if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
  

• 	DRM_DEBUG_KMS("unsupported pixel format: %s\n",
  

• 		      drm_get_format_name(mode_cmd->pixel_format,
  

• 					  &format_name));
  

• 	goto err;
  

• }
  

• break;
  

  default: DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name));

@@ -14568,7 +14595,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,

drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);

• if (fb->format->format == DRM_FORMAT_NV12 &&

• if (is_planar_yuv_format(fb->format->format) && (fb->width < SKL_MIN_YUV_420_SRC_W || fb->height < SKL_MIN_YUV_420_SRC_H || (fb->width % 4) != 0 || (fb->height % 4) != 0)) {

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f573121..b4701ca 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2114,6 +2114,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,

/* intel_sprite.c */ +bool is_planar_yuv_format(uint32_t pixelformat); int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, int usecs); struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d99e5fa..e1292b2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) < 11) val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));

• if (fourcc == DRM_FORMAT_NV12) {

• if (is_planar_yuv_format(fourcc)) { skl_ddb_entry_init_from_hw(dev_priv, &ddb->plane[pipe][plane_id], val2); skl_ddb_entry_init_from_hw(dev_priv,

@@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,

if (intel_plane->id == PLANE_CURSOR) return 0;

• if (plane == 1 && format != DRM_FORMAT_NV12)

• if (plane == 1 && !is_planar_yuv_format(format)) return 0;

  /*

@@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, height = drm_rect_height(&intel_pstate->base.src) >> 16;

/* UV plane does 1/2 pixel sub-sampling */

• if (plane == 1 && format == DRM_FORMAT_NV12) {

• if (plane == 1 && is_planar_yuv_format(format)) { width /= 2; height /= 2; }

@@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane) return 0;

/* For packed formats, and uv-plane, return 0 */

• if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)

• if (plane == 1 && !is_planar_yuv_format(fb->format->format)) return 0;

  /* For Non Y-tile return 8-blocks */

@@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane) src_w = drm_rect_width(&intel_pstate->base.src) >> 16; src_h = drm_rect_height(&intel_pstate->base.src) >> 16;

• /* Halve UV plane width and height for NV12 */

• /* Halve UV plane width and height for NV12 and other planar yuv */ if (plane == 1) { src_w /= 2; src_h /= 2;

@@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, return 0;

/* only NV12 format has two planes */

• if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {

• DRM_DEBUG_KMS("Non NV12 format have single plane\n");
  

• if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {

• DRM_DEBUG_KMS("Non planar format have single plane\n");
  

  return -EINVAL; }

@@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;

• wp->is_planar = fb->format->format == DRM_FORMAT_NV12;

• wp->is_planar = is_planar_yuv_format(fb->format->format);

  if (plane->id == PLANE_CURSOR) { wp->width = intel_pstate->base.crtc_w;

@@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv, return ret; }

• if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)

• wm->is_planar = true;
  

• wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);

  return 0;

} diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9600ccf..1f1276f 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -41,6 +41,19 @@ #include <drm/i915_drm.h> #include "i915_drv.h"

+bool is_planar_yuv_format(uint32_t pixelformat) +{

• switch (pixelformat) {
• case DRM_FORMAT_NV12:
• case DRM_FORMAT_P010:
• case DRM_FORMAT_P012:
• case DRM_FORMAT_P016:

• return true;
  

• default:

• return false;
  

• }

+}

int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, int usecs) { @@ -1041,7 +1054,7 @@ intel_check_sprite_plane(struct intel_crtc_state *crtc_state, src->y2 = (src_y + src_h) << 16;

if (fb->format->is_yuv &&

• 	    fb->format->format != DRM_FORMAT_NV12 &&
  

•     !is_planar_yuv_format(fb->format->format) &&
  

  (src_x % 2 || src_w % 2)) { DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n", src_x, src_w);

@@ -1420,6 +1433,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12:

• case DRM_FORMAT_P010:
• case DRM_FORMAT_P012:
• case DRM_FORMAT_P016: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */

-- 2.7.4

---

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