Thank's for your comment.
please check my answer.
BR Eunchul Kim
On 12/13/2012 11:29 AM, Joonyoung Shim wrote:
Hi,
I can't review about logic of driver because i don't know well but i feel there are too many checking codes and unused or big size defines.
- I think error handling need. and What is unused defines ? What is big size define ? you mean the coefficient value ?
Please refer v4l2 exynos gsc driver in drivers/media/platform/exynos-gsc/.
- I will check exynos gsc.
This v3 patch seems to add many codes than v2. Please write changelog in future.
- Thank's I don't have a lot of experience about posting.
Even if line is short, many lines are split to two lines. Please check it overall.
- PATCH description ?
Thanks.
On 12/12/2012 04:34 PM, Eunchul Kim wrote:
GSC is stand for General SCaler and supports supports
supports supports
- Thank's, done.
image scaler/rotator/crop/flip/csc and input/output DMA operations. input DMA reads image data from the memory. output DMA writes image data to memory. GSC supports image rotation and imag effect functions.
s/imag/image
- done.
also supports writeback and display output operations.
There are to begin a new line unnecessarily. Could you rewrite detailedly how this driver operates?
- What kind of ? writeback ? output operation ?
Signed-off-by: Eunchul Kim chulspro.kim@samsung.com Signed-off-by: Jinyoung Jeon jy0.jeon@samsung.com
drivers/gpu/drm/exynos/Kconfig | 5 + drivers/gpu/drm/exynos/Makefile | 1 + drivers/gpu/drm/exynos/exynos_drm_drv.c | 15 + drivers/gpu/drm/exynos/exynos_drm_drv.h | 1 + drivers/gpu/drm/exynos/exynos_drm_gsc.c | 1927 +++++++++++++++++++++++++++++++ drivers/gpu/drm/exynos/exynos_drm_gsc.h | 34 + drivers/gpu/drm/exynos/regs-gsc.h | 295 +++++ 7 files changed, 2278 insertions(+), 0 deletions(-) create mode 100644 drivers/gpu/drm/exynos/exynos_drm_gsc.c create mode 100644 drivers/gpu/drm/exynos/exynos_drm_gsc.h create mode 100644 drivers/gpu/drm/exynos/regs-gsc.h
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 4860835..c93d776 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -64,3 +64,8 @@ config DRM_EXYNOS_ROTATOR help Choose this option if you want to use Exynos Rotator for DRM. +config DRM_EXYNOS_GSC
- bool "Exynos DRM GSC"
- depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5
- help
Choose this option if you want to use Exynos GSC for DRM.diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 3b70668..639b49e 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -19,5 +19,6 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_G2D) += exynos_drm_g2d.o exynosdrm-$(CONFIG_DRM_EXYNOS_IPP) += exynos_drm_ipp.o exynosdrm-$(CONFIG_DRM_EXYNOS_FIMC) += exynos_drm_fimc.o exynosdrm-$(CONFIG_DRM_EXYNOS_ROTATOR) += exynos_drm_rotator.o +exynosdrm-$(CONFIG_DRM_EXYNOS_GSC) += exynos_drm_gsc.o obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index 09d884b..e0a8e80 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -384,6 +384,12 @@ static int __init exynos_drm_init(void) goto out_rotator; #endif +#ifdef CONFIG_DRM_EXYNOS_GSC
- ret = platform_driver_register(&gsc_driver);
- if (ret < 0)
goto out_gsc;+#endif
- #ifdef CONFIG_DRM_EXYNOS_IPP ret = platform_driver_register(&ipp_driver); if (ret < 0)
@@ -412,6 +418,11 @@ out_drm: out_ipp: #endif +#ifdef CONFIG_DRM_EXYNOS_GSC
- platform_driver_unregister(&gsc_driver);
+out_gsc: +#endif
- #ifdef CONFIG_DRM_EXYNOS_ROTATOR platform_driver_unregister(&rotator_driver); out_rotator:
@@ -462,6 +473,10 @@ static void __exit exynos_drm_exit(void) platform_driver_unregister(&ipp_driver); #endif +#ifdef CONFIG_DRM_EXYNOS_GSC
- platform_driver_unregister(&gsc_driver);
+#endif
- #ifdef CONFIG_DRM_EXYNOS_ROTATOR platform_driver_unregister(&rotator_driver); #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index a74e37c..afe556c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -354,5 +354,6 @@ extern struct platform_driver vidi_driver; extern struct platform_driver g2d_driver; extern struct platform_driver fimc_driver; extern struct platform_driver rotator_driver; +extern struct platform_driver gsc_driver; extern struct platform_driver ipp_driver; #endif diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c new file mode 100644 index 0000000..a4475b0 --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -0,0 +1,1927 @@ +/*
- Copyright (C) 2012 Samsung Electronics Co.Ltd
- Authors:
- Eunchul Kim chulspro.kim@samsung.com
- Jinyoung Jeon jy0.jeon@samsung.com
- Sangmin Lee lsmin.lee@samsung.com
- This program is free software; you can redistribute it and/or
modify it
- under the terms of the GNU General Public License as published
by the
- Free Software Foundation; either version 2 of the License, or
(at your
- option) any later version.
- */
+#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/pm_runtime.h> +#include <plat/map-base.h>
+#include <drm/drmP.h> +#include <drm/exynos_drm.h> +#include "regs-gsc.h" +#include "exynos_drm_ipp.h" +#include "exynos_drm_gsc.h"
+/*
- GSC is stand for General SCaler and
- supports image scaler/rotator and input/output DMA operations.
- input DMA reads image data from the memory.
- output DMA writes image data to memory.
- GSC supports image rotation and image effect functions.
- */
Please see my comments about commit description.
- operation description ?
+#define GSC_MAX_DEVS 4 +#define GSC_MAX_SRC 4 +#define GSC_MAX_DST 16 +#define GSC_RESET_TIMEOUT 50 +#define GSC_BUF_STOP 1 +#define GSC_BUF_START 2 +#define GSC_REG_SZ 16 +#define GSC_WIDTH_ITU_709 1280 +#define GSC_SC_UP_MAX_RATIO 65536 +#define GSC_SC_DOWN_RATIO_7_8 74898 +#define GSC_SC_DOWN_RATIO_6_8 87381 +#define GSC_SC_DOWN_RATIO_5_8 104857 +#define GSC_SC_DOWN_RATIO_4_8 131072 +#define GSC_SC_DOWN_RATIO_3_8 174762 +#define GSC_SC_DOWN_RATIO_2_8 262144 +#define GSC_REFRESH_MIN 12 +#define GSC_REFRESH_MAX 60 +#define GSC_CROP_MAX 8192 +#define GSC_CROP_MIN 32 +#define GSC_SCALE_MAX 4224 +#define GSC_SCALE_MIN 32
+#define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) +#define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
struct gsc_context, ippdrv);+#define gsc_read(offset) readl(ctx->regs + (offset)) +#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
+/*
- A structure of scaler.
- @range: narrow, wide.
- @pre_shfactor: pre sclaer shift factor.
- @pre_hratio: horizontal ratio of the prescaler.
- @pre_vratio: vertical ratio of the prescaler.
- @main_hratio: the main scaler's horizontal ratio.
- @main_vratio: the main scaler's vertical ratio.
- */
+struct gsc_scaler {
- bool range;
- u32 pre_shfactor;
- u32 pre_hratio;
- u32 pre_vratio;
- unsigned long main_hratio;
- unsigned long main_vratio;
+};
+/*
- A structure of scaler capability.
- find user manual 49.2 features.
- @tile_w: tile mode or rotation width.
- @tile_h: tile mode or rotation height.
- @w: other cases width.
- @h: other cases height.
- */
+struct gsc_capability {
- /* tile or rotation */
- u32 tile_w;
- u32 tile_h;
- /* other cases */
- u32 w;
- u32 h;
+};
+/*
- A structure of gsc context.
- @ippdrv: prepare initialization using ippdrv.
- @regs_res: register resources.
- @regs: memory mapped io registers.
- @lock: locking of operations.
- @gsc_clk: gsc gate clock.
- @parent_clk: parent clock e.g aclk_300.
- @child_clk: child clock e.g dout_aclk_300.
- @sc: scaler infomations.
- @id: gsc id.
- @irq: irq number.
- @rotation: supports rotation of src.
- @suspended: qos operations.
- */
+struct gsc_context {
- struct exynos_drm_ippdrv ippdrv;
- struct resource *regs_res;
- void __iomem *regs;
- struct mutex lock;
- struct clk *gsc_clk;
- struct clk *parent_clk;
- struct clk *child_clk;
- struct gsc_scaler sc;
- int id;
- int irq;
- bool rotation;
- bool suspended;
+};
+/* 8-tap Filter Coefficient */ +const int h_coef_8t[7][16][8] = {
static? and it is unnecessary to be size of array.
- static OK. if remove size, build error. what do you want ?
- { /* Ratio <= 65536 (~8:8) */
{ 0, 0, 0, 128, 0, 0, 0, 0 },/* 0 */{ -1, 2, -6, 127, 7, -2, 1, 0 },/* 1 */{ -1, 4, -12, 125, 16, -5, 1, 0 },/* 2 */{ -1, 5, -15, 120, 25, -8, 2, 0 },/* 3 */{ -1, 6, -18, 114, 35, -10, 3, -1 },/* 4 */{ -1, 6, -20, 107, 46, -13, 4, -1 },/* 5 */{ -2, 7, -21, 99, 57, -16, 5, -1 },/* 6 */{ -1, 6, -20, 89, 68, -18, 5, -1 },/* 7 */{ -1, 6, -20, 79, 79, -20, 6, -1 },/* 8 */{ -1, 5, -18, 68, 89, -20, 6, -1 },/* 9 */{ -1, 5, -16, 57, 99, -21, 7, -2 },/* 10 */{ -1, 4, -13, 46, 107, -20, 6, -1 },/* 11 */{ -1, 3, -10, 35, 114, -18, 6, -1 },/* 12 */{ 0, 2, -8, 25, 120, -15, 5, -1 },/* 13 */{ 0, 1, -5, 16, 125, -12, 4, -1 },/* 14 */{ 0, 1, -2, 7, 127, -6, 2, -1 } /* 15 */The comments for index seem unnecessary.
- done.
- }, { /* 65536 < Ratio <= 74898 (~8:7) */
{ 3, -8, 14, 111, 13, -8, 3, 0 },/* 0 */{ 2, -6, 7, 112, 21, -10, 3, -1 },/* 1 */{ 2, -4, 1, 110, 28, -12, 4, -1 },/* 2 */{ 1, -2, -3, 106, 36, -13, 4, -1 },/* 3 */{ 1, -1, -7, 103, 44, -15, 4, -1 },/* 4 */{ 1, 1, -11, 97, 53, -16, 4, -1 },/* 5 */{ 0, 2, -13, 91, 61, -16, 4, -1 },/* 6 */{ 0, 3, -15, 85, 69, -17, 4, -1 },/* 7 */{ 0, 3, -16, 77, 77, -16, 3, 0 },/* 8 */{ -1, 4, -17, 69, 85, -15, 3, 0 },/* 9 */{ -1, 4, -16, 61, 91, -13, 2, 0 },/* 10 */{ -1, 4, -16, 53, 97, -11, 1, 1 },/* 11 */{ -1, 4, -15, 44, 103, -7, -1, 1 },/* 12 */{ -1, 4, -13, 36, 106, -3, -2, 1 },/* 13 */{ -1, 4, -12, 28, 110, 1, -4, 2 },/* 14 */{ -1, 3, -10, 21, 112, 7, -6, 2 } /* 15 */- }, { /* 74898 < Ratio <= 87381 (~8:6) */
{ 2, -11, 25, 96, 25, -11, 2, 0 },/* 0 */{ 2, -10, 19, 96, 31, -12, 2, 0 },/* 1 */{ 2, -9, 14, 94, 37, -12, 2, 0 },/* 2 */{ 2, -8, 10, 92, 43, -12, 1, 0 },/* 3 */{ 2, -7, 5, 90, 49, -12, 1, 0 },/* 4 */{ 2, -5, 1, 86, 55, -12, 0, 1 },/* 5 */{ 2, -4, -2, 82, 61, -11, -1, 1 },/* 6 */{ 1, -3, -5, 77, 67, -9, -1, 1 },/* 7 */{ 1, -2, -7, 72, 72, -7, -2, 1 },/* 8 */{ 1, -1, -9, 67, 77, -5, -3, 1 },/* 9 */{ 1, -1, -11, 61, 82, -2, -4, 2 },/* 10 */{ 1, 0, -12, 55, 86, 1, -5, 2 },/* 11 */{ 0, 1, -12, 49, 90, 5, -7, 2 },/* 12 */{ 0, 1, -12, 43, 92, 10, -8, 2 },/* 13 */{ 0, 2, -12, 37, 94, 14, -9, 2 },/* 14 */{ 0, 2, -12, 31, 96, 19, -10, 2 } /* 15 */- }, { /* 87381 < Ratio <= 104857 (~8:5) */
{ -1, -8, 33, 80, 33, -8, -1, 0 },/* 0 */{ -1, -8, 28, 80, 37, -7, -2, 1 },/* 1 */{ 0, -8, 24, 79, 41, -7, -2, 1 },/* 2 */{ 0, -8, 20, 78, 46, -6, -3, 1 },/* 3 */{ 0, -8, 16, 76, 50, -4, -3, 1 },/* 4 */{ 0, -7, 13, 74, 54, -3, -4, 1 },/* 5 */{ 1, -7, 10, 71, 58, -1, -5, 1 },/* 6 */{ 1, -6, 6, 68, 62, 1, -5, 1 },/* 7 */{ 1, -6, 4, 65, 65, 4, -6, 1 },/* 8 */{ 1, -5, 1, 62, 68, 6, -6, 1 },/* 9 */{ 1, -5, -1, 58, 71, 10, -7, 1 },/* 10 */{ 1, -4, -3, 54, 74, 13, -7, 0 },/* 11 */{ 1, -3, -4, 50, 76, 16, -8, 0 },/* 12 */{ 1, -3, -6, 46, 78, 20, -8, 0 },/* 13 */{ 1, -2, -7, 41, 79, 24, -8, 0 },/* 14 */{ 1, -2, -7, 37, 80, 28, -8, -1 } /* 15 */- }, { /* 104857 < Ratio <= 131072 (~8:4) */
{ -3, 0, 35, 64, 35, 0, -3, 0 },/* 0 */{ -3, -1, 32, 64, 38, 1, -3, 0 },/* 1 */{ -2, -2, 29, 63, 41, 2, -3, 0 },/* 2 */{ -2, -3, 27, 63, 43, 4, -4, 0 },/* 3 */{ -2, -3, 24, 61, 46, 6, -4, 0 },/* 4 */{ -2, -3, 21, 60, 49, 7, -4, 0 },/* 5 */{ -1, -4, 19, 59, 51, 9, -4, -1 },/* 6 */{ -1, -4, 16, 57, 53, 12, -4, -1 },/* 7 */{ -1, -4, 14, 55, 55, 14, -4, -1 },/* 8 */{ -1, -4, 12, 53, 57, 16, -4, -1 },/* 9 */{ -1, -4, 9, 51, 59, 19, -4, -1 },/* 10 */{ 0, -4, 7, 49, 60, 21, -3, -2 },/* 11 */{ 0, -4, 6, 46, 61, 24, -3, -2 },/* 12 */{ 0, -4, 4, 43, 63, 27, -3, -2 },/* 13 */{ 0, -3, 2, 41, 63, 29, -2, -2 },/* 14 */{ 0, -3, 1, 38, 64, 32, -1, -3 } /* 15 */- }, { /* 131072 < Ratio <= 174762 (~8:3) */
{ -1, 8, 33, 48, 33, 8, -1, 0 },/* 0 */{ -1, 7, 31, 49, 35, 9, -1, -1 },/* 1 */{ -1, 6, 30, 49, 36, 10, -1, -1 },/* 2 */{ -1, 5, 28, 48, 38, 12, -1, -1 },/* 3 */{ -1, 4, 26, 48, 39, 13, 0, -1 },/* 4 */{ -1, 3, 24, 47, 41, 15, 0, -1 },/* 5 */{ -1, 2, 23, 47, 42, 16, 0, -1 },/* 6 */{ -1, 2, 21, 45, 43, 18, 1, -1 },/* 7 */{ -1, 1, 19, 45, 45, 19, 1, -1 },/* 8 */{ -1, 1, 18, 43, 45, 21, 2, -1 },/* 9 */{ -1, 0, 16, 42, 47, 23, 2, -1 },/* 10 */{ -1, 0, 15, 41, 47, 24, 3, -1 },/* 11 */{ -1, 0, 13, 39, 48, 26, 4, -1 },/* 12 */{ -1, -1, 12, 38, 48, 28, 5, -1 },/* 13 */{ -1, -1, 10, 36, 49, 30, 6, -1 },/* 14 */{ -1, -1, 9, 35, 49, 31, 7, -1 } /* 15 */- }, { /* 174762 < Ratio <= 262144 (~8:2) */
{ 2, 13, 30, 38, 30, 13, 2, 0 },/* 0 */{ 2, 12, 29, 38, 30, 14, 3, 0 },/* 1 */{ 2, 11, 28, 38, 31, 15, 3, 0 },/* 2 */{ 2, 10, 26, 38, 32, 16, 4, 0 },/* 3 */{ 1, 10, 26, 37, 33, 17, 4, 0 },/* 4 */{ 1, 9, 24, 37, 34, 18, 5, 0 },/* 5 */{ 1, 8, 24, 37, 34, 19, 5, 0 },/* 6 */{ 1, 7, 22, 36, 35, 20, 6, 1 },/* 7 */{ 1, 6, 21, 36, 36, 21, 6, 1 },/* 8 */{ 1, 6, 20, 35, 36, 22, 7, 1 },/* 9 */{ 0, 5, 19, 34, 37, 24, 8, 1 },/* 10 */{ 0, 5, 18, 34, 37, 24, 9, 1 },/* 11 */{ 0, 4, 17, 33, 37, 26, 10, 1 },/* 12 */{ 0, 4, 16, 32, 38, 26, 10, 2 },/* 13 */{ 0, 3, 15, 31, 38, 28, 11, 2 },/* 14 */{ 0, 3, 14, 30, 38, 29, 12, 2 } /* 15 */- }
+};
+/* 4-tap Filter Coefficient */ +const int v_coef_4t[7][16][4] = {
- { /* Ratio <= 65536 (~8:8) */
{ 0, 128, 0, 0 },/* 0 */{ -4, 127, 5, 0 },/* 1 */{ -6, 124, 11, -1 },/* 2 */{ -8, 118, 19, -1 },/* 3 */{ -8, 111, 27, -2 },/* 4 */{ -8, 102, 37, -3 },/* 5 */{ -8, 92, 48, -4 },/* 6 */{ -7, 81, 59, -5 },/* 7 */{ -6, 70, 70, -6 },/* 8 */{ -5, 59, 81, -7 },/* 9 */{ -4, 48, 92, -8 },/* 10 */{ -3, 37, 102, -8 },/* 11 */{ -2, 27, 111, -8 },/* 12 */{ -1, 19, 118, -8 },/* 13 */{ -1, 11, 124, -6 },/* 14 */{ 0, 5, 127, -4 } /* 15 */- }, { /* 65536 < Ratio <= 74898 (~8:7) */
{ 8, 112, 8, 0 },/* 0 */{ 4, 111, 14, -1 },/* 1 */{ 1, 109, 20, -2 },/* 2 */{ -2, 105, 27, -2 },/* 3 */{ -3, 100, 34, -3 },/* 4 */{ -5, 93, 43, -3 },/* 5 */{ -5, 86, 51, -4 },/* 6 */{ -5, 77, 60, -4 },/* 7 */{ -5, 69, 69, -5 },/* 8 */{ -4, 60, 77, -5 },/* 9 */{ -4, 51, 86, -5 },/* 10 */{ -3, 43, 93, -5 },/* 11 */{ -3, 34, 100, -3 },/* 12 */{ -2, 27, 105, -2 },/* 13 */{ -2, 20, 109, 1 },/* 14 */{ -1, 14, 111, 4 } /* 15 */- }, { /* 74898 < Ratio <= 87381 (~8:6) */
{ 16, 96, 16, 0 },/* 0 */{ 12, 97, 21, -2 },/* 1 */{ 8, 96, 26, -2 },/* 2 */{ 5, 93, 32, -2 },/* 3 */{ 2, 89, 39, -2 },/* 4 */{ 0, 84, 46, -2 },/* 5 */{ -1, 79, 53, -3 },/* 6 */{ -2, 73, 59, -2 },/* 7 */{ -2, 66, 66, -2 },/* 8 */{ -2, 59, 73, -2 },/* 9 */{ -3, 53, 79, -1 },/* 10 */{ -2, 46, 84, 0 },/* 11 */{ -2, 39, 89, 2 },/* 12 */{ -2, 32, 93, 5 },/* 13 */{ -2, 26, 96, 8 },/* 14 */{ -2, 21, 97, 12 } /* 15 */- }, { /* 87381 < Ratio <= 104857 (~8:5) */
{ 22, 84, 22, 0 },/* 0 */{ 18, 85, 26, -1 },/* 1 */{ 14, 84, 31, -1 },/* 2 */{ 11, 82, 36, -1 },/* 3 */{ 8, 79, 42, -1 },/* 4 */{ 6, 76, 47, -1 },/* 5 */{ 4, 72, 52, 0 },/* 6 */{ 2, 68, 58, 0 },/* 7 */{ 1, 63, 63, 1 },/* 8 */{ 0, 58, 68, 2 },/* 9 */{ 0, 52, 72, 4 },/* 10 */{ -1, 47, 76, 6 },/* 11 */{ -1, 42, 79, 8 },/* 12 */{ -1, 36, 82, 11 },/* 13 */{ -1, 31, 84, 14 },/* 14 */{ -1, 26, 85, 18 } /* 15 */- }, { /* 104857 < Ratio <= 131072 (~8:4) */
{ 26, 76, 26, 0 },/* 0 */{ 22, 76, 30, 0 },/* 1 */{ 19, 75, 34, 0 },/* 2 */{ 16, 73, 38, 1 },/* 3 */{ 13, 71, 43, 1 },/* 4 */{ 10, 69, 47, 2 },/* 5 */{ 8, 66, 51, 3 },/* 6 */{ 6, 63, 55, 4 },/* 7 */{ 5, 59, 59, 5 },/* 8 */{ 4, 55, 63, 6 },/* 9 */{ 3, 51, 66, 8 },/* 10 */{ 2, 47, 69, 10 },/* 11 */{ 1, 43, 71, 13 },/* 12 */{ 1, 38, 73, 16 },/* 13 */{ 0, 34, 75, 19 },/* 14 */{ 0, 30, 76, 22 } /* 15 */- }, { /* 131072 < Ratio <= 174762 (~8:3) */
{ 29, 70, 29, 0 },/* 0 */{ 26, 68, 32, 2 },/* 1 */{ 23, 67, 36, 2 },/* 2 */{ 20, 66, 39, 3 },/* 3 */{ 17, 65, 43, 3 },/* 4 */{ 15, 63, 46, 4 },/* 5 */{ 12, 61, 50, 5 },/* 6 */{ 10, 58, 53, 7 },/* 7 */{ 8, 56, 56, 8 },/* 8 */{ 7, 53, 58, 10 },/* 9 */{ 5, 50, 61, 12 },/* 10 */{ 4, 46, 63, 15 },/* 11 */{ 3, 43, 65, 17 },/* 12 */{ 3, 39, 66, 20 },/* 13 */{ 2, 36, 67, 23 },/* 14 */{ 2, 32, 68, 26 } /* 15 */- }, { /* 174762 < Ratio <= 262144 (~8:2) */
{ 32, 64, 32, 0 },/* 0 */{ 28, 63, 34, 3 },/* 1 */{ 25, 62, 37, 4 },/* 2 */{ 22, 62, 40, 4 },/* 3 */{ 19, 61, 43, 5 },/* 4 */{ 17, 59, 46, 6 },/* 5 */{ 15, 58, 48, 7 },/* 6 */{ 13, 55, 51, 9 },/* 7 */{ 11, 53, 53, 11 },/* 8 */{ 9, 51, 55, 13 },/* 9 */{ 7, 48, 58, 15 },/* 10 */{ 6, 46, 59, 17 },/* 11 */{ 5, 43, 61, 19 },/* 12 */{ 4, 40, 62, 22 },/* 13 */{ 4, 37, 62, 25 },/* 14 */{ 3, 34, 63, 28 } /* 15 */- }
+};
+static int gsc_sw_reset(struct gsc_context *ctx) +{
- u32 cfg;
- int count = GSC_RESET_TIMEOUT;
- DRM_DEBUG_KMS("%s\n", __func__);
- /* s/w reset */
- cfg = (GSC_SW_RESET_SRESET);
- gsc_write(cfg, GSC_SW_RESET);
- /* wait s/w reset complete */
- while (count--) {
cfg = gsc_read(GSC_SW_RESET);if (!cfg)break;usleep_range(1000, 2000);- }
- if (cfg) {
DRM_ERROR("failed to reset gsc h/w.\n");return -EBUSY;- }
- /* display fifo reset */
- cfg = readl(SYSREG_GSCBLK_CFG0);
- /*
* GSCBLK Pixel asyncy FIFO S/W reset sequence* set PXLASYNC_SW_RESET as 0 then,* set PXLASYNC_SW_RESET as 1 again*/- cfg &= ~GSC_PXLASYNC_RST(ctx->id);
- writel(cfg, SYSREG_GSCBLK_CFG0);
- cfg |= GSC_PXLASYNC_RST(ctx->id);
- writel(cfg, SYSREG_GSCBLK_CFG0);
- /* pixel async reset */
- cfg = readl(SYSREG_DISP1BLK_CFG);
- /*
* DISPBLK1 FIFO S/W reset sequence* set FIFORST_DISP1 as 0 then,* set FIFORST_DISP1 as 1 again*/- cfg &= ~FIFORST_DISP1;
- writel(cfg, SYSREG_DISP1BLK_CFG);
- cfg |= FIFORST_DISP1;
- writel(cfg, SYSREG_DISP1BLK_CFG);
- /* reset sequence */
- cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
- cfg |= (GSC_IN_BASE_ADDR_MASK |
GSC_IN_BASE_ADDR_PINGPONG(0));- gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
- gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
- gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
- cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
- cfg |= (GSC_OUT_BASE_ADDR_MASK |
GSC_OUT_BASE_ADDR_PINGPONG(0));- gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
- gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
- gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
- return 0;
+}
+static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable) +{
- u32 gscblk_cfg;
- DRM_DEBUG_KMS("%s\n", __func__);
- gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
- if (enable)
gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |GSC_BLK_SW_RESET_WB_DEST(ctx->id);- else
gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);- writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
+}
+static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
bool overflow, bool done)Overflow and down argument are used to same value always in this driver. Is it right?
- It is handle irq flag API. I want to handle irq flags using this api. so, I added enable/overflow/done argument.
+{
- u32 cfg;
- DRM_DEBUG_KMS("%s:enable[%d]overflow[%d]level[%d]\n", __func__,
enable, overflow, done);- cfg = gsc_read(GSC_IRQ);
- cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
Unnecessary initialization.
- It is just clear cfg flag. I think that is need.
- if (enable)
cfg |= GSC_IRQ_ENABLE;- else
cfg &= ~GSC_IRQ_ENABLE;- if (overflow)
cfg &= ~GSC_IRQ_OR_MASK;- else
cfg |= GSC_IRQ_OR_MASK;- if (done)
cfg &= ~GSC_IRQ_FRMDONE_MASK;- else
cfg |= GSC_IRQ_FRMDONE_MASK;- gsc_write(cfg, GSC_IRQ);
+}
+static int gsc_src_set_fmt(struct device *dev, u32 fmt) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- u32 cfg;
- DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
- cfg = gsc_read(GSC_IN_CON);
- cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);- switch (fmt) {
- case DRM_FORMAT_RGB565:
cfg |= GSC_IN_RGB565;break;- case DRM_FORMAT_XRGB8888:
cfg |= GSC_IN_XRGB8888;break;- case DRM_FORMAT_BGRX8888:
cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);break;- case DRM_FORMAT_YUYV:
cfg |= (GSC_IN_YUV422_1P |GSC_IN_YUV422_1P_ORDER_LSB_Y |GSC_IN_CHROMA_ORDER_CBCR);break;- case DRM_FORMAT_YVYU:
cfg |= (GSC_IN_YUV422_1P |GSC_IN_YUV422_1P_ORDER_LSB_Y |GSC_IN_CHROMA_ORDER_CRCB);break;- case DRM_FORMAT_UYVY:
cfg |= (GSC_IN_YUV422_1P |GSC_IN_YUV422_1P_OEDER_LSB_C |GSC_IN_CHROMA_ORDER_CBCR);break;- case DRM_FORMAT_VYUY:
cfg |= (GSC_IN_YUV422_1P |GSC_IN_YUV422_1P_OEDER_LSB_C |GSC_IN_CHROMA_ORDER_CRCB);break;- case DRM_FORMAT_NV21:
- case DRM_FORMAT_NV61:
cfg |= (GSC_IN_CHROMA_ORDER_CRCB |GSC_IN_YUV420_2P);break;- case DRM_FORMAT_YUV422:
cfg |= GSC_IN_YUV422_3P;break;- case DRM_FORMAT_YUV420:
- case DRM_FORMAT_YVU420:
cfg |= GSC_IN_YUV420_3P;break;- case DRM_FORMAT_NV12:
- case DRM_FORMAT_NV16:
cfg |= (GSC_IN_CHROMA_ORDER_CBCR |GSC_IN_YUV420_2P);break;- case DRM_FORMAT_NV12MT:
cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);break;- default:
dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);return -EINVAL;- }
- gsc_write(cfg, GSC_IN_CON);
- return 0;
+}
+static int gsc_src_set_transf(struct device *dev,
enum drm_exynos_degree degree,enum drm_exynos_flip flip)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- u32 cfg;
- DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
degree, flip);- cfg = gsc_read(GSC_IN_CON);
- cfg &= ~GSC_IN_ROT_MASK;
- switch (degree) {
- case EXYNOS_DRM_DEGREE_0:
if (flip & EXYNOS_DRM_FLIP_VERTICAL)cfg |= GSC_IN_ROT_XFLIP;if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)cfg |= GSC_IN_ROT_YFLIP;break;- case EXYNOS_DRM_DEGREE_90:
if (flip & EXYNOS_DRM_FLIP_VERTICAL)cfg |= GSC_IN_ROT_90_XFLIP;else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)cfg |= GSC_IN_ROT_90_YFLIP;elsecfg |= GSC_IN_ROT_90;break;- case EXYNOS_DRM_DEGREE_180:
cfg |= GSC_IN_ROT_180;break;- case EXYNOS_DRM_DEGREE_270:
cfg |= GSC_IN_ROT_270;break;- default:
dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);return -EINVAL;- }
- gsc_write(cfg, GSC_IN_CON);
- ctx->rotation = cfg &
(GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;- return ctx->rotation;
+}
+static int gsc_src_set_size(struct device *dev, int swap,
struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct drm_exynos_pos img_pos = *pos;
- struct gsc_scaler *sc = &ctx->sc;
- u32 cfg;
- DRM_DEBUG_KMS("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
__func__, swap, pos->x, pos->y, pos->w, pos->h);- if (swap) {
img_pos.w = pos->h;img_pos.h = pos->w;- }
- /* pixel offset */
- cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
GSC_SRCIMG_OFFSET_Y(img_pos.y));- gsc_write(cfg, GSC_SRCIMG_OFFSET);
- /* cropped size */
- cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
GSC_CROPPED_HEIGHT(img_pos.h));- gsc_write(cfg, GSC_CROPPED_SIZE);
- DRM_DEBUG_KMS("%s:hsize[%d]vsize[%d]\n",
__func__, sz->hsize, sz->vsize);- /* original size */
- cfg = gsc_read(GSC_SRCIMG_SIZE);
- cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
GSC_SRCIMG_WIDTH_MASK);- cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
GSC_SRCIMG_HEIGHT(sz->vsize));- gsc_write(cfg, GSC_SRCIMG_SIZE);
- cfg = gsc_read(GSC_IN_CON);
- cfg &= ~GSC_IN_RGB_TYPE_MASK;
- DRM_DEBUG_KMS("%s:width[%d]range[%d]\n",
__func__, pos->w, sc->range);- if (pos->w >= GSC_WIDTH_ITU_709)
if (sc->range)cfg |= GSC_IN_RGB_HD_WIDE;elsecfg |= GSC_IN_RGB_HD_NARROW;- else
if (sc->range)cfg |= GSC_IN_RGB_SD_WIDE;elsecfg |= GSC_IN_RGB_SD_NARROW;- gsc_write(cfg, GSC_IN_CON);
- return 0;
+}
+static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
enum drm_exynos_ipp_buf_type buf_type)+{
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- bool masked;
- u32 cfg;
- u32 mask = 0x00000001 << buf_id;
- DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__,
buf_id, buf_type);- /* mask register set */
- cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
- switch (buf_type) {
- case IPP_BUF_ENQUEUE:
masked = false;break;- case IPP_BUF_DEQUEUE:
masked = true;break;- default:
dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");return -EINVAL;- }
- /* sequence id */
- cfg &= (~mask);
Unnecessary parenthesis.
- done.
- cfg |= masked << buf_id;
- gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
- gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
- gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
- return 0;
+}
+static int gsc_src_set_addr(struct device *dev,
struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,enum drm_exynos_ipp_buf_type buf_type)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
- struct drm_exynos_ipp_property *property;
- if (!c_node) {
DRM_ERROR("failed to get c_node.\n");return -EINVAL;-EFAULT
- done.
- }
- property = &c_node->property;
- if (!property) {
DRM_ERROR("failed to get property.\n");return -EINVAL;-EFAULT
- done.
- }
- DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
property->prop_id, buf_id, buf_type);- if (buf_id > GSC_MAX_SRC) {
dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);return -ENOMEM;-EINVAL
- done.
- }
- /* address register set */
- switch (buf_type) {
- case IPP_BUF_ENQUEUE:
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],GSC_IN_BASE_ADDR_Y(buf_id));gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],GSC_IN_BASE_ADDR_CB(buf_id));gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],GSC_IN_BASE_ADDR_CR(buf_id));break;- case IPP_BUF_DEQUEUE:
gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));break;- default:
/* bypass */break;- }
- return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
+}
+static struct exynos_drm_ipp_ops gsc_src_ops = {
- .set_fmt = gsc_src_set_fmt,
- .set_transf = gsc_src_set_transf,
- .set_size = gsc_src_set_size,
- .set_addr = gsc_src_set_addr,
+};
+static int gsc_dst_set_fmt(struct device *dev, u32 fmt) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- u32 cfg;
- DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
- cfg = gsc_read(GSC_OUT_CON);
- cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |GSC_OUT_GLOBAL_ALPHA_MASK);- switch (fmt) {
- case DRM_FORMAT_RGB565:
cfg |= GSC_OUT_RGB565;break;- case DRM_FORMAT_XRGB8888:
cfg |= GSC_OUT_XRGB8888;break;- case DRM_FORMAT_BGRX8888:
cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);break;- case DRM_FORMAT_YUYV:
cfg |= (GSC_OUT_YUV422_1P |GSC_OUT_YUV422_1P_ORDER_LSB_Y |GSC_OUT_CHROMA_ORDER_CBCR);break;- case DRM_FORMAT_YVYU:
cfg |= (GSC_OUT_YUV422_1P |GSC_OUT_YUV422_1P_ORDER_LSB_Y |GSC_OUT_CHROMA_ORDER_CRCB);break;- case DRM_FORMAT_UYVY:
cfg |= (GSC_OUT_YUV422_1P |GSC_OUT_YUV422_1P_OEDER_LSB_C |GSC_OUT_CHROMA_ORDER_CBCR);break;- case DRM_FORMAT_VYUY:
cfg |= (GSC_OUT_YUV422_1P |GSC_OUT_YUV422_1P_OEDER_LSB_C |GSC_OUT_CHROMA_ORDER_CRCB);break;- case DRM_FORMAT_NV21:
- case DRM_FORMAT_NV61:
cfg |= (GSC_OUT_CHROMA_ORDER_CRCB |GSC_OUT_YUV420_2P);Please check to join to one line overall. This line can be in 80 character.
- Thank's. done.
break;- case DRM_FORMAT_YUV422:
- case DRM_FORMAT_YUV420:
- case DRM_FORMAT_YVU420:
cfg |= GSC_OUT_YUV420_3P;break;- case DRM_FORMAT_NV12:
- case DRM_FORMAT_NV16:
cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |GSC_OUT_YUV420_2P);break;- case DRM_FORMAT_NV12MT:
cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);break;- default:
dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);return -EINVAL;- }
- gsc_write(cfg, GSC_OUT_CON);
- return 0;
+}
+static int gsc_dst_set_transf(struct device *dev,
enum drm_exynos_degree degree,enum drm_exynos_flip flip)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- u32 cfg;
- DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
degree, flip);- cfg = gsc_read(GSC_IN_CON);
- cfg &= ~GSC_IN_ROT_MASK;
- switch (degree) {
- case EXYNOS_DRM_DEGREE_0:
if (flip & EXYNOS_DRM_FLIP_VERTICAL)cfg |= GSC_IN_ROT_XFLIP;if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)cfg |= GSC_IN_ROT_YFLIP;break;- case EXYNOS_DRM_DEGREE_90:
if (flip & EXYNOS_DRM_FLIP_VERTICAL)cfg |= GSC_IN_ROT_90_XFLIP;else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)cfg |= GSC_IN_ROT_90_YFLIP;elsecfg |= GSC_IN_ROT_90;break;- case EXYNOS_DRM_DEGREE_180:
cfg |= GSC_IN_ROT_180;break;- case EXYNOS_DRM_DEGREE_270:
cfg |= GSC_IN_ROT_270;break;- default:
dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);return -EINVAL;- }
- gsc_write(cfg, GSC_IN_CON);
- ctx->rotation = cfg &
(GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;- return ctx->rotation;
+}
+static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio) +{
- DRM_DEBUG_KMS("%s:src[%d]dst[%d]\n", __func__, src, dst);
- if (src >= dst * 8) {
DRM_ERROR("failed to make ratio and shift.\n");return -EINVAL;- } else if (src >= dst * 4)
*ratio = 4;- else if (src >= dst * 2)
*ratio = 2;- else
*ratio = 1;- return 0;
+}
+static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor) +{
- if (hratio == 4 && vratio == 4)
*shfactor = 4;- else if ((hratio == 4 && vratio == 2) ||
(hratio == 2 && vratio == 4))*shfactor = 3;- else if ((hratio == 4 && vratio == 1) ||
(hratio == 1 && vratio == 4) ||(hratio == 2 && vratio == 2))*shfactor = 2;- else if (hratio == 1 && vratio == 1)
*shfactor = 0;- else
*shfactor = 1;+}
+static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
struct drm_exynos_pos *src, struct drm_exynos_pos *dst)+{
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- u32 cfg;
- u32 src_w, src_h, dst_w, dst_h;
- int ret = 0;
- src_w = src->w;
- src_h = src->h;
- if (ctx->rotation) {
dst_w = dst->h;dst_h = dst->w;- } else {
dst_w = dst->w;dst_h = dst->h;- }
- ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
- if (ret) {
dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");return ret;- }
- ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
- if (ret) {
dev_err(ippdrv->dev, "failed to get ratio vertical.\n");return ret;- }
- DRM_DEBUG_KMS("%s:pre_hratio[%d]pre_vratio[%d]\n",
__func__, sc->pre_hratio, sc->pre_vratio);- sc->main_hratio = (src_w << 16) / dst_w;
- sc->main_vratio = (src_h << 16) / dst_h;
- DRM_DEBUG_KMS("%s:main_hratio[%ld]main_vratio[%ld]\n",
__func__, sc->main_hratio, sc->main_vratio);- gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
&sc->pre_shfactor);- DRM_DEBUG_KMS("%s:pre_shfactor[%d]\n", __func__,
sc->pre_shfactor);- cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
GSC_PRESC_H_RATIO(sc->pre_hratio) |GSC_PRESC_V_RATIO(sc->pre_vratio));- gsc_write(cfg, GSC_PRE_SCALE_RATIO);
- return ret;
+}
+static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio) +{
- int i, j, k, sc_ratio;
- if (main_hratio <= GSC_SC_UP_MAX_RATIO)
sc_ratio = 0;- else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
sc_ratio = 1;- else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
sc_ratio = 2;- else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
sc_ratio = 3;- else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
sc_ratio = 4;- else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
sc_ratio = 5;- else
sc_ratio = 6;- for (i = 0; i < 9; i++)
for (j = 0; j < 8; j++)for (k = 0; k < 3; k++)gsc_write(h_coef_8t[sc_ratio][i][j],GSC_HCOEF(i, j, k));Please define constants to macro or get array size.
- about for loop ? or value ?
+}
+static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio) +{
- int i, j, k, sc_ratio = 0;
Unnecessary initialization.
- done.
- if (main_vratio <= GSC_SC_UP_MAX_RATIO)
sc_ratio = 0;- else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
sc_ratio = 1;- else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
sc_ratio = 2;- else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
sc_ratio = 3;- else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
sc_ratio = 4;- else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
sc_ratio = 5;- else
sc_ratio = 6;- for (i = 0; i < 9; i++)
for (j = 0; j < 4; j++)for (k = 0; k < 3; k++)gsc_write(v_coef_4t[sc_ratio][i][j],GSC_VCOEF(i, j, k));+}
+static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc) +{
- u32 cfg;
- DRM_DEBUG_KMS("%s:main_hratio[%ld]main_vratio[%ld]\n",
__func__, sc->main_hratio, sc->main_vratio);- gsc_set_h_coef(ctx, sc->main_hratio);
- cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
- gsc_write(cfg, GSC_MAIN_H_RATIO);
- gsc_set_v_coef(ctx, sc->main_vratio);
- cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
- gsc_write(cfg, GSC_MAIN_V_RATIO);
+}
+static int gsc_dst_set_size(struct device *dev, int swap,
struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct drm_exynos_pos img_pos = *pos;
- struct gsc_scaler *sc = &ctx->sc;
- u32 cfg;
- DRM_DEBUG_KMS("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
__func__, swap, pos->x, pos->y, pos->w, pos->h);- if (swap) {
img_pos.w = pos->h;img_pos.h = pos->w;- }
- /* pixel offset */
- cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
GSC_DSTIMG_OFFSET_Y(pos->y));- gsc_write(cfg, GSC_DSTIMG_OFFSET);
- /* scaled size */
- cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
- gsc_write(cfg, GSC_SCALED_SIZE);
- DRM_DEBUG_KMS("%s:hsize[%d]vsize[%d]\n",
__func__, sz->hsize, sz->vsize);- /* original size */
- cfg = gsc_read(GSC_DSTIMG_SIZE);
- cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
GSC_DSTIMG_WIDTH_MASK);- cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
GSC_DSTIMG_HEIGHT(sz->vsize));- gsc_write(cfg, GSC_DSTIMG_SIZE);
- cfg = gsc_read(GSC_OUT_CON);
- cfg &= ~GSC_OUT_RGB_TYPE_MASK;
- DRM_DEBUG_KMS("%s:width[%d]range[%d]\n",
__func__, pos->w, sc->range);- if (pos->w >= GSC_WIDTH_ITU_709)
if (sc->range)cfg |= GSC_OUT_RGB_HD_WIDE;elsecfg |= GSC_OUT_RGB_HD_NARROW;- else
if (sc->range)cfg |= GSC_OUT_RGB_SD_WIDE;elsecfg |= GSC_OUT_RGB_SD_NARROW;- gsc_write(cfg, GSC_OUT_CON);
- return 0;
+}
+static int gsc_dst_get_buf_seq(struct gsc_context *ctx) +{
- u32 cfg, i, buf_num = GSC_REG_SZ;
- u32 mask = 0x00000001;
- cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
- for (i = 0; i < GSC_REG_SZ; i++)
if (cfg & (mask << i))buf_num--;- DRM_DEBUG_KMS("%s:buf_num[%d]\n", __func__, buf_num);
- return buf_num;
+}
+static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
enum drm_exynos_ipp_buf_type buf_type)+{
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- bool masked;
- u32 cfg;
- u32 mask = 0x00000001 << buf_id;
- int ret = 0;
- DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__,
buf_id, buf_type);- mutex_lock(&ctx->lock);
- /* mask register set */
- cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
- switch (buf_type) {
- case IPP_BUF_ENQUEUE:
masked = false;break;- case IPP_BUF_DEQUEUE:
masked = true;break;- default:
dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");ret = -EINVAL;goto err_unlock;- }
- /* sequence id */
- cfg &= (~mask);
Unnecessary parenthesis.
- done.
- cfg |= masked << buf_id;
- gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
- gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
- gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
- /* interrupt enable */
- if (buf_type == IPP_BUF_ENQUEUE &&
gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)gsc_handle_irq(ctx, true, false, true);- /* interrupt disable */
- if (buf_type == IPP_BUF_DEQUEUE &&
gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)gsc_handle_irq(ctx, false, false, true);+err_unlock:
- mutex_unlock(&ctx->lock);
- return ret;
+}
+static int gsc_dst_set_addr(struct device *dev,
struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,enum drm_exynos_ipp_buf_type buf_type)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
- struct drm_exynos_ipp_property *property;
- if (!c_node) {
DRM_ERROR("failed to get c_node.\n");return -EINVAL;-EFAULT
- done.
- }
- property = &c_node->property;
- if (!property) {
DRM_ERROR("failed to get property.\n");return -EINVAL;-EFAULT
- done.
- }
- DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
property->prop_id, buf_id, buf_type);- if (buf_id > GSC_MAX_DST) {
dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);return -ENOMEM;-EINVAL
- done.
- }
- /* address register set */
- switch (buf_type) {
- case IPP_BUF_ENQUEUE:
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],GSC_OUT_BASE_ADDR_Y(buf_id));gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],GSC_OUT_BASE_ADDR_CB(buf_id));gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],GSC_OUT_BASE_ADDR_CR(buf_id));break;- case IPP_BUF_DEQUEUE:
gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));break;- default:
/* bypass */break;- }
- return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
+}
+static struct exynos_drm_ipp_ops gsc_dst_ops = {
- .set_fmt = gsc_dst_set_fmt,
- .set_transf = gsc_dst_set_transf,
- .set_size = gsc_dst_set_size,
- .set_addr = gsc_dst_set_addr,
+};
+static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable) +{
- DRM_INFO("%s:enable[%d]\n", __func__, enable);
DRM_DEBUG_KMS?
- sorry my mistaken. done.
- if (enable) {
clk_set_parent(ctx->child_clk, ctx->parent_clk);I think this is enough only to one operation.
- Thank's move to probe.
clk_enable(ctx->gsc_clk);ctx->suspended = false;- } else {
clk_disable(ctx->gsc_clk);ctx->suspended = true;- }
- return 0;
+}
+static int gsc_get_src_buf_index(struct gsc_context *ctx) +{
- u32 cfg, curr_index, i;
- u32 buf_id = GSC_MAX_SRC;
- DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
- cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
- curr_index = GSC_IN_CURR_GET_INDEX(cfg);
- for (i = curr_index; i < GSC_MAX_SRC; i++) {
if (!((cfg >> i) & 0x1)) {buf_id = i;break;}- }
- if (buf_id == GSC_MAX_SRC) {
DRM_ERROR("failed to get in buffer index.\n");return -EIO;Is this IO error?
- Do you want to EINVAL ?
- }
- if (gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
DRM_ERROR("failed to dequeue.\n");return IRQ_HANDLED;Is IRQ_HANDLED right return value?
- my missing point. use 'ret' changed it.
- }
- DRM_DEBUG_KMS("%s:cfg[0x%x]curr_index[%d]buf_id[%d]\n", __func__,
cfg,
curr_index, buf_id);- return buf_id;
+}
+static int gsc_get_dst_buf_index(struct gsc_context *ctx) +{
- u32 cfg, curr_index, i;
- u32 buf_id = GSC_MAX_DST;
- DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
- cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
- curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
- for (i = curr_index; i < GSC_MAX_DST; i++) {
if (!((cfg >> i) & 0x1)) {buf_id = i;break;}- }
- if (buf_id == GSC_MAX_DST) {
DRM_ERROR("failed to get out buffer index.\n");return -EIO;Is this IO error?
- EINVAL OK ?
- }
- if (gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
DRM_ERROR("failed to dequeue.\n");return IRQ_HANDLED;Is IRQ_HANDLED right return value?
- changed also.
- }
- DRM_DEBUG_KMS("%s:cfg[0x%x]curr_index[%d]buf_id[%d]\n", __func__,
cfg,
curr_index, buf_id);- return buf_id;
+}
+static irqreturn_t gsc_irq_handler(int irq, void *dev_id) +{
- struct gsc_context *ctx = dev_id;
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
- struct drm_exynos_ipp_event_work *event_work =
c_node->event_work;- u32 status;
- int buf_id[EXYNOS_DRM_OPS_MAX];
- DRM_DEBUG_KMS("%s:gsc id[%d]\n", __func__, ctx->id);
- status = gsc_read(GSC_IRQ);
- if (status & GSC_IRQ_STATUS_OR_IRQ) {
dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n",ctx->id, status);return IRQ_NONE;- }
- if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
dev_dbg(ippdrv->dev, "occured frame done at %d, status 0x%x.\n",ctx->id, status);buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)return IRQ_HANDLED;buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);if (buf_id[EXYNOS_DRM_OPS_DST] < 0)return IRQ_HANDLED;DRM_DEBUG_KMS("%s:buf_id_src[%d]buf_id_dst[%d]\n", __func__,buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);event_work->ippdrv = ippdrv;event_work->buf_id[EXYNOS_DRM_OPS_SRC] =buf_id[EXYNOS_DRM_OPS_SRC];event_work->buf_id[EXYNOS_DRM_OPS_DST] =buf_id[EXYNOS_DRM_OPS_DST];queue_work(ippdrv->event_workq,(struct work_struct *)event_work);- }
- return IRQ_HANDLED;
+}
+static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) +{
- struct drm_exynos_ipp_prop_list *prop_list;
- DRM_DEBUG_KMS("%s\n", __func__);
- prop_list = kzalloc(sizeof(*prop_list), GFP_KERNEL);
- if (!prop_list) {
DRM_ERROR("failed to alloc property list.\n");return -ENOMEM;- }
- /*ToDo : fix supported function list*/
Please remove comments.
- removed it.
- prop_list->version = 1;
- prop_list->writeback = 1;
- prop_list->refresh_min = GSC_REFRESH_MIN;
- prop_list->refresh_max = GSC_REFRESH_MAX;
- prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
(1 << EXYNOS_DRM_FLIP_HORIZONTAL);- prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
(1 << EXYNOS_DRM_DEGREE_90) |(1 << EXYNOS_DRM_DEGREE_180) |(1 << EXYNOS_DRM_DEGREE_270);- prop_list->csc = 1;
- prop_list->crop = 1;
- prop_list->crop_max.hsize = GSC_CROP_MAX;
- prop_list->crop_max.vsize = GSC_CROP_MAX;
- prop_list->crop_min.hsize = GSC_CROP_MIN;
- prop_list->crop_min.vsize = GSC_CROP_MIN;
- prop_list->scale = 1;
Hardcode. There are too much flags in prop_list and they are just 1 bit on/off flags, so i think you can join them to one variable.
- I want to remain this one. If we use combine flags, userland always check bit and operation. I don't prefer that.
- prop_list->scale_max.hsize = GSC_SCALE_MAX;
- prop_list->scale_max.vsize = GSC_SCALE_MAX;
- prop_list->scale_min.hsize = GSC_SCALE_MIN;
- prop_list->scale_min.vsize = GSC_SCALE_MIN;
- ippdrv->prop_list = prop_list;
- return 0;
+}
+static int gsc_ippdrv_check_property(struct device *dev,
struct drm_exynos_ipp_property *property)+{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
- struct drm_exynos_ipp_config *config;
- struct drm_exynos_pos *pos;
- struct drm_exynos_sz *sz;
- bool swap;
- int i;
- DRM_DEBUG_KMS("%s\n", __func__);
- for_each_ipp_ops(i) {
if ((i == EXYNOS_DRM_OPS_SRC) &&(property->cmd == IPP_CMD_WB))continue;config = &property->config[i];pos = &config->pos;sz = &config->sz;/* check for flip */switch (config->flip) {case EXYNOS_DRM_FLIP_NONE:case EXYNOS_DRM_FLIP_VERTICAL:case EXYNOS_DRM_FLIP_HORIZONTAL:case EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL:/* No problem */break;default:DRM_ERROR("invalid flip.\n");goto err_property;}/* check for degree */switch (config->degree) {case EXYNOS_DRM_DEGREE_90:case EXYNOS_DRM_DEGREE_270:swap = true;break;case EXYNOS_DRM_DEGREE_0:case EXYNOS_DRM_DEGREE_180:swap = false;break;default:DRM_ERROR("invalid degree.\n");goto err_property;}/* check for buffer bound */if ((pos->x + pos->w > sz->hsize) ||(pos->y + pos->h > sz->vsize)) {DRM_ERROR("out of buf bound.\n");goto err_property;}/* check for crop */if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {if (swap) {if ((pos->h < pp->crop_min.hsize) ||(sz->vsize > pp->crop_max.hsize) ||(pos->w < pp->crop_min.vsize) ||(sz->hsize > pp->crop_max.vsize)) {DRM_ERROR("out of crop size.\n");goto err_property;}} else {if ((pos->w < pp->crop_min.hsize) ||(sz->hsize > pp->crop_max.hsize) ||(pos->h < pp->crop_min.vsize) ||(sz->vsize > pp->crop_max.vsize)) {DRM_ERROR("out of crop size.\n");goto err_property;}}}/* check for scale */if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {if (swap) {if ((pos->h < pp->scale_min.hsize) ||(sz->vsize > pp->scale_max.hsize) ||(pos->w < pp->scale_min.vsize) ||(sz->hsize > pp->scale_max.vsize)) {DRM_ERROR("out of scale size.\n");goto err_property;}} else {if ((pos->w < pp->scale_min.hsize) ||(sz->hsize > pp->scale_max.hsize) ||(pos->h < pp->scale_min.vsize) ||(sz->vsize > pp->scale_max.vsize)) {DRM_ERROR("out of scale size.\n");goto err_property;}}}- }
- return 0;
+err_property:
- for_each_ipp_ops(i) {
if ((i == EXYNOS_DRM_OPS_SRC) &&(property->cmd == IPP_CMD_WB))continue;config = &property->config[i];pos = &config->pos;sz = &config->sz;DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",i ? "dst" : "src", config->flip, config->degree,pos->x, pos->y, pos->w, pos->h,sz->hsize, sz->vsize);- }
- return -EINVAL;
+}
+static int gsc_ippdrv_reset(struct device *dev) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct gsc_scaler *sc = &ctx->sc;
- int ret;
- DRM_DEBUG_KMS("%s\n", __func__);
- /* reset h/w block */
- ret = gsc_sw_reset(ctx);
- if (ret < 0) {
dev_err(dev, "failed to reset hardware.\n");return ret;- }
- /* scaler setting */
- memset(&ctx->sc, 0x0, sizeof(ctx->sc));
- sc->range = true;
- return 0;
+}
+static int gsc_check_prepare(struct gsc_context *ctx) +{
- /* ToDo: check prepare using read register */
- DRM_DEBUG_KMS("%s\n", __func__);
- return 0;
+}
I read your comments but i can't understand why this dummy function needs still. Please remove and if implement it later, send additional patch.
- removed it. please see the v4 patch.
+static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- struct drm_exynos_ipp_cmd_node *c_node = ippdrv->cmd;
- struct drm_exynos_ipp_property *property;
- struct drm_exynos_ipp_config *config;
- struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
- struct drm_exynos_ipp_set_wb set_wb;
- u32 cfg;
- int ret, i;
- DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
- if (!c_node) {
DRM_ERROR("failed to get c_node.\n");return -EINVAL;- }
- property = &c_node->property;
- if (!property) {
DRM_ERROR("failed to get property.\n");return -EINVAL;- }
- ret = gsc_check_prepare(ctx);
- if (ret) {
dev_err(dev, "failed to check prepare.\n");return ret;- }
Please remove.
- removed it. please see the v4 patch
- gsc_handle_irq(ctx, true, false, true);
- /* ToDo: window size, prescaler config */
Please remove comment.
- done.
- for_each_ipp_ops(i) {
config = &property->config[i];img_pos[i] = config->pos;- }
- switch (cmd) {
- case IPP_CMD_M2M:
/* enable one shot */cfg = gsc_read(GSC_ENABLE);cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |GSC_ENABLE_CLK_GATE_MODE_MASK);cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;gsc_write(cfg, GSC_ENABLE);/* src dma memory */cfg = gsc_read(GSC_IN_CON);cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);cfg |= GSC_IN_PATH_MEMORY;gsc_write(cfg, GSC_IN_CON);/* dst dma memory */cfg = gsc_read(GSC_OUT_CON);cfg |= GSC_OUT_PATH_MEMORY;gsc_write(cfg, GSC_OUT_CON);break;- case IPP_CMD_WB:
/* ToDo: need to replace the property structure. */set_wb.enable = 1;set_wb.refresh = property->refresh_rate;gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);/* src local path */cfg = readl(GSC_IN_CON);cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);gsc_write(cfg, GSC_IN_CON);/* dst dma memory */cfg = gsc_read(GSC_OUT_CON);cfg |= GSC_OUT_PATH_MEMORY;gsc_write(cfg, GSC_OUT_CON);break;- case IPP_CMD_OUTPUT:
/* src dma memory */cfg = gsc_read(GSC_IN_CON);cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);cfg |= GSC_IN_PATH_MEMORY;gsc_write(cfg, GSC_IN_CON);/* dst local path */cfg = gsc_read(GSC_OUT_CON);cfg |= GSC_OUT_PATH_MEMORY;gsc_write(cfg, GSC_OUT_CON);break;- default:
ret = -EINVAL;dev_err(dev, "invalid operations.\n");return ret;- }
- ret = gsc_set_prescaler(ctx, &ctx->sc,
&img_pos[EXYNOS_DRM_OPS_SRC],&img_pos[EXYNOS_DRM_OPS_DST]);- if (ret) {
dev_err(dev, "failed to set precalser.\n");return ret;- }
- gsc_set_scaler(ctx, &ctx->sc);
- cfg = gsc_read(GSC_ENABLE);
- cfg |= GSC_ENABLE_ON;
- gsc_write(cfg, GSC_ENABLE);
- return 0;
+}
+static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- struct drm_exynos_ipp_set_wb set_wb = {0, 0};
- u32 cfg;
- DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
- switch (cmd) {
- case IPP_CMD_M2M:
/* bypass */break;- case IPP_CMD_WB:
gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);break;- case IPP_CMD_OUTPUT:
- default:
dev_err(dev, "invalid operations.\n");break;- }
- gsc_handle_irq(ctx, false, false, true);
- /* reset sequence */
- gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
- gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
- gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
- cfg = gsc_read(GSC_ENABLE);
- cfg &= ~GSC_ENABLE_ON;
- gsc_write(cfg, GSC_ENABLE);
+}
+static int __devinit gsc_probe(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct gsc_context *ctx;
- struct resource *res;
- struct exynos_drm_ippdrv *ippdrv;
- int ret;
- ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
- if (!ctx)
return -ENOMEM;- /* clock control */
- ctx->gsc_clk = clk_get(dev, "gscl");
- if (IS_ERR(ctx->gsc_clk)) {
dev_err(dev, "failed to get gsc clock.\n");ret = PTR_ERR(ctx->gsc_clk);goto err_ctx;- }
- ctx->parent_clk = clk_get(NULL, "aclk_300_gscl");
- if (IS_ERR(ctx->parent_clk)) {
dev_err(dev, "failed to get parent clock.\n");ret = PTR_ERR(ctx->parent_clk);clk_put(ctx->gsc_clk);goto err_ctx;- }
- ctx->child_clk = clk_get(NULL, "dout_aclk_300_gscl");
- if (IS_ERR(ctx->child_clk)) {
dev_err(dev, "failed to get child clock.\n");ret = PTR_ERR(ctx->child_clk);clk_put(ctx->gsc_clk);clk_put(ctx->parent_clk);goto err_ctx;- }
Why do these clocks need? Please don't decide specific clock source in driver.
- we need to parent clk, child clk link at this point if we enable GSC block.
- /* resource memory */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
dev_err(dev, "failed to find registers.\n");ret = -ENOENT;goto err_clk;- }
- ctx->regs_res = request_mem_region(res->start, resource_size(res),
dev_name(dev));- if (!ctx->regs_res) {
dev_err(dev, "failed to claim register region.\n");ret = -ENOENT;goto err_clk;- }
- ctx->regs = ioremap(res->start, resource_size(res));
- if (!ctx->regs) {
dev_err(dev, "failed to map registers.\n");ret = -ENXIO;goto err_req_region;- }
Use devm_request_and_ioremap()
- Why request devm_request_and_ioremap() in this patch. I think Exynos DRM module not changed devm_ at current. so, I think this patch merge at first. and changed it about all Exynos DRM drivers. I think that is better.
- /* resource irq */
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res) {
dev_err(dev, "failed to request irq resource.\n");ret = -ENOENT;goto err_get_regs;- }
- ctx->irq = res->start;
- ret = request_threaded_irq(ctx->irq, NULL, gsc_irq_handler,
IRQF_ONESHOT, "drm_gsc", ctx);Use devm_request_irq
- ditto.
- if (ret < 0) {
dev_err(dev, "failed to request irq.\n");goto err_get_regs;- }
- /* context initailization */
- ctx->id = pdev->id;
- ippdrv = &ctx->ippdrv;
- ippdrv->dev = dev;
- ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
- ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
- ippdrv->check_property = gsc_ippdrv_check_property;
- ippdrv->reset = gsc_ippdrv_reset;
- ippdrv->start = gsc_ippdrv_start;
- ippdrv->stop = gsc_ippdrv_stop;
- ret = gsc_init_prop_list(ippdrv);
- if (ret < 0) {
dev_err(dev, "failed to init property list.\n");goto err_get_irq;- }
- DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id,
(int)ippdrv);- mutex_init(&ctx->lock);
- platform_set_drvdata(pdev, ctx);
- pm_runtime_set_active(dev);
- pm_runtime_enable(dev);
- ret = exynos_drm_ippdrv_register(ippdrv);
- if (ret < 0) {
dev_err(dev, "failed to register drm gsc device.\n");goto err_ippdrv_register;- }
- dev_info(&pdev->dev, "drm gsc registered successfully.\n");
- return 0;
+err_ippdrv_register:
- kfree(ippdrv->prop_list);
- pm_runtime_disable(dev);
- free_irq(ctx->irq, ctx);
+err_get_irq:
- free_irq(ctx->irq, ctx);
+err_get_regs:
- iounmap(ctx->regs);
+err_req_region:
- release_resource(ctx->regs_res);
- kfree(ctx->regs_res);
+err_clk:
- clk_put(ctx->child_clk);
- clk_put(ctx->parent_clk);
- clk_put(ctx->gsc_clk);
+err_ctx:
- kfree(ctx);
- return ret;
+}
+static int __devexit gsc_remove(struct platform_device *pdev) +{
- struct device *dev = &pdev->dev;
- struct gsc_context *ctx = get_gsc_context(dev);
- struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
- kfree(ippdrv->prop_list);
- exynos_drm_ippdrv_unregister(ippdrv);
- mutex_destroy(&ctx->lock);
- pm_runtime_set_suspended(dev);
- pm_runtime_disable(dev);
- free_irq(ctx->irq, ctx);
- iounmap(ctx->regs);
- release_resource(ctx->regs_res);
- kfree(ctx->regs_res);
- clk_put(ctx->child_clk);
- clk_put(ctx->parent_clk);
- clk_put(ctx->gsc_clk);
- kfree(ctx);
- return 0;
+}
+#ifdef CONFIG_PM_SLEEP +static int gsc_suspend(struct device *dev) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- /* ToDo */
Remove.
- Why? you request to me about above to top. so, I moved it. TODO needed
- DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
- if (pm_runtime_suspended(dev))
return 0;- return gsc_clk_ctrl(ctx, false);
+}
+static int gsc_resume(struct device *dev) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- /* ToDo */
Ditto.
- ditto.
- DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
- if (!pm_runtime_suspended(dev))
return gsc_clk_ctrl(ctx, true);- return 0;
+} +#endif
+#ifdef CONFIG_PM_RUNTIME +static int gsc_runtime_suspend(struct device *dev) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- /* ToDo */
Ditto.
- ditto.
- DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
- return gsc_clk_ctrl(ctx, false);
+}
+static int gsc_runtime_resume(struct device *dev) +{
- struct gsc_context *ctx = get_gsc_context(dev);
- /* ToDo */
Ditto.
- ditto.
- DRM_DEBUG_KMS("%s:id[%d]\n", __FILE__, ctx->id);
- return gsc_clk_ctrl(ctx, true);
If runtime PM isn't enabled, how do you control clock?
- Good point. hmm ~ what is standard ? please recommand your knowledge to me.
+} +#endif
+static const struct dev_pm_ops gsc_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
- SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
+};
+/* ToDo: need to check use case platform_device_id */
Use "TODO" instead of "ToDo".
- removed it.
+struct platform_driver gsc_driver = {
- .probe = gsc_probe,
- .remove = __devexit_p(gsc_remove),
- .driver = {
.name = "exynos-drm-gsc",.owner = THIS_MODULE,.pm = &gsc_pm_ops,- },
+};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.h b/drivers/gpu/drm/exynos/exynos_drm_gsc.h new file mode 100644 index 0000000..b3ef7a0 --- /dev/null +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.h @@ -0,0 +1,34 @@ +/*
- Copyright (c) 2012 Samsung Electronics Co., Ltd.
- Authors:
- Eunchul Kim chulspro.kim@samsung.com
- Jinyoung Jeon jy0.jeon@samsung.com
- Sangmin Lee lsmin.lee@samsung.com
- Permission is hereby granted, free of charge, to any person
obtaining a
- copy of this software and associated documentation files (the
"Software"),
- to deal in the Software without restriction, including without
limitation
- the rights to use, copy, modify, merge, publish, distribute,
sublicense,
- and/or sell copies of the Software, and to permit persons to whom the
- Software is furnished to do so, subject to the following conditions:
- The above copyright notice and this permission notice (including
the next
- paragraph) shall be included in all copies or substantial portions
of the
- Software.
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
- VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR
- OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- OTHER DEALINGS IN THE SOFTWARE.
- */
+#ifndef _EXYNOS_DRM_GSC_H_ +#define _EXYNOS_DRM_GSC_H_
+/* ToDo */
Please remove this dummy header file.
- I want to finish file creation in this patch. We need to link with MIxer so, I prepared it.
+#endif /* _EXYNOS_DRM_GSC_H_ */ diff --git a/drivers/gpu/drm/exynos/regs-gsc.h b/drivers/gpu/drm/exynos/regs-gsc.h new file mode 100644 index 0000000..ed297b5 --- /dev/null +++ b/drivers/gpu/drm/exynos/regs-gsc.h @@ -0,0 +1,295 @@ +/* linux/drivers/gpu/drm/exynos/regs-gsc.h
- Copyright (c) 2012 Samsung Electronics Co., Ltd.
http://www.samsung.com
- Register definition file for Samsung G-Scaler driver
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
- */
+#ifndef EXYNOS_REGS_GSC_H_ +#define EXYNOS_REGS_GSC_H_
+/* SYSCON. GSCBLK_CFG */ +#include <plat/map-base.h> +#include <plat/cpu.h> +#define SYSREG_DISP1BLK_CFG (S3C_VA_SYS + 0x0214) +#define FIFORST_DISP1 (1 << 23) +#define GSC_OUT_MIXER0 (1 << 7) +#define GSC_OUT_MIXER0_GSC3 (3 << 5) +#define SYSREG_GSCBLK_CFG0 (S3C_VA_SYS + 0x0220) +#define GSC_OUT_DST_FIMD_SEL(x) (1 << (8 + 2 * (x))) +#define GSC_OUT_DST_MXR_SEL(x) (2 << (8 + 2 * (x))) +#define GSC_PXLASYNC_RST(x) (1 << (x)) +#define PXLASYNC_LO_MASK_CAMIF_TOP (1 << 20) +#define SYSREG_GSCBLK_CFG1 (S3C_VA_SYS + 0x0224) +#define GSC_BLK_DISP1WB_DEST(x) (x << 10) +#define GSC_BLK_SW_RESET_WB_DEST(x) (1 << (18 + x)) +#define GSC_BLK_PXLASYNC_LO_MASK_WB(x) (0 << (14 + x)) +#define GSC_BLK_GSCL_WB_IN_SRC_SEL(x) (1 << (2 * x)) +#define SYSREG_GSCBLK_CFG2 (S3C_VA_SYS + 0x2000) +#define PXLASYNC_LO_MASK_CAMIF_GSCL(x) (1 << (x))
+/* G-Scaler enable */ +#define GSC_ENABLE 0x00 +#define GSC_ENABLE_PP_UPDATE_TIME_MASK (1 << 9) +#define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9) +#define GSC_ENABLE_PP_UPDATE_TIME_EOPAS (1 << 9) +#define GSC_ENABLE_CLK_GATE_MODE_MASK (1 << 8) +#define GSC_ENABLE_CLK_GATE_MODE_FREE (1 << 8) +#define GSC_ENABLE_IPC_MODE_MASK (1 << 7) +#define GSC_ENABLE_NORM_MODE (0 << 7) +#define GSC_ENABLE_IPC_MODE (1 << 7) +#define GSC_ENABLE_PP_UPDATE_MODE_MASK (1 << 6) +#define GSC_ENABLE_PP_UPDATE_FIRE_MODE (1 << 6) +#define GSC_ENABLE_IN_PP_UPDATE (1 << 5) +#define GSC_ENABLE_ON_CLEAR_MASK (1 << 4) +#define GSC_ENABLE_ON_CLEAR_ONESHOT (1 << 4) +#define GSC_ENABLE_QOS_ENABLE (1 << 3) +#define GSC_ENABLE_OP_STATUS (1 << 2) +#define GSC_ENABLE_SFR_UPDATE (1 << 1) +#define GSC_ENABLE_ON (1 << 0)
+/* G-Scaler S/W reset */ +#define GSC_SW_RESET 0x04 +#define GSC_SW_RESET_SRESET (1 << 0)
+/* G-Scaler IRQ */ +#define GSC_IRQ 0x08 +#define GSC_IRQ_STATUS_OR_IRQ (1 << 17) +#define GSC_IRQ_STATUS_OR_FRM_DONE (1 << 16) +#define GSC_IRQ_OR_MASK (1 << 2) +#define GSC_IRQ_FRMDONE_MASK (1 << 1) +#define GSC_IRQ_ENABLE (1 << 0)
+/* G-Scaler input control */ +#define GSC_IN_CON 0x10 +#define GSC_IN_CHROM_STRIDE_SEL_MASK (1 << 20) +#define GSC_IN_CHROM_STRIDE_SEPAR (1 << 20) +#define GSC_IN_RB_SWAP_MASK (1 << 19) +#define GSC_IN_RB_SWAP (1 << 19) +#define GSC_IN_ROT_MASK (7 << 16) +#define GSC_IN_ROT_270 (7 << 16) +#define GSC_IN_ROT_90_YFLIP (6 << 16) +#define GSC_IN_ROT_90_XFLIP (5 << 16) +#define GSC_IN_ROT_90 (4 << 16) +#define GSC_IN_ROT_180 (3 << 16) +#define GSC_IN_ROT_YFLIP (2 << 16) +#define GSC_IN_ROT_XFLIP (1 << 16) +#define GSC_IN_RGB_TYPE_MASK (3 << 14) +#define GSC_IN_RGB_HD_WIDE (3 << 14) +#define GSC_IN_RGB_HD_NARROW (2 << 14) +#define GSC_IN_RGB_SD_WIDE (1 << 14) +#define GSC_IN_RGB_SD_NARROW (0 << 14) +#define GSC_IN_YUV422_1P_ORDER_MASK (1 << 13) +#define GSC_IN_YUV422_1P_ORDER_LSB_Y (0 << 13) +#define GSC_IN_YUV422_1P_OEDER_LSB_C (1 << 13) +#define GSC_IN_CHROMA_ORDER_MASK (1 << 12) +#define GSC_IN_CHROMA_ORDER_CBCR (0 << 12) +#define GSC_IN_CHROMA_ORDER_CRCB (1 << 12) +#define GSC_IN_FORMAT_MASK (7 << 8) +#define GSC_IN_XRGB8888 (0 << 8) +#define GSC_IN_RGB565 (1 << 8) +#define GSC_IN_YUV420_2P (2 << 8) +#define GSC_IN_YUV420_3P (3 << 8) +#define GSC_IN_YUV422_1P (4 << 8) +#define GSC_IN_YUV422_2P (5 << 8) +#define GSC_IN_YUV422_3P (6 << 8) +#define GSC_IN_TILE_TYPE_MASK (1 << 4) +#define GSC_IN_TILE_C_16x8 (0 << 4) +#define GSC_IN_TILE_C_16x16 (1 << 4) +#define GSC_IN_TILE_MODE (1 << 3) +#define GSC_IN_LOCAL_SEL_MASK (3 << 1) +#define GSC_IN_LOCAL_CAM3 (3 << 1) +#define GSC_IN_LOCAL_FIMD_WB (2 << 1) +#define GSC_IN_LOCAL_CAM1 (1 << 1) +#define GSC_IN_LOCAL_CAM0 (0 << 1) +#define GSC_IN_PATH_MASK (1 << 0) +#define GSC_IN_PATH_LOCAL (1 << 0) +#define GSC_IN_PATH_MEMORY (0 << 0)
+/* G-Scaler source image size */ +#define GSC_SRCIMG_SIZE 0x14 +#define GSC_SRCIMG_HEIGHT_MASK (0x1fff << 16) +#define GSC_SRCIMG_HEIGHT(x) ((x) << 16) +#define GSC_SRCIMG_WIDTH_MASK (0x3fff << 0) +#define GSC_SRCIMG_WIDTH(x) ((x) << 0)
+/* G-Scaler source image offset */ +#define GSC_SRCIMG_OFFSET 0x18 +#define GSC_SRCIMG_OFFSET_Y_MASK (0x1fff << 16) +#define GSC_SRCIMG_OFFSET_Y(x) ((x) << 16) +#define GSC_SRCIMG_OFFSET_X_MASK (0x1fff << 0) +#define GSC_SRCIMG_OFFSET_X(x) ((x) << 0)
+/* G-Scaler cropped source image size */ +#define GSC_CROPPED_SIZE 0x1C +#define GSC_CROPPED_HEIGHT_MASK (0x1fff << 16) +#define GSC_CROPPED_HEIGHT(x) ((x) << 16) +#define GSC_CROPPED_WIDTH_MASK (0x1fff << 0) +#define GSC_CROPPED_WIDTH(x) ((x) << 0)
+/* G-Scaler output control */ +#define GSC_OUT_CON 0x20 +#define GSC_OUT_GLOBAL_ALPHA_MASK (0xff << 24) +#define GSC_OUT_GLOBAL_ALPHA(x) ((x) << 24) +#define GSC_OUT_CHROM_STRIDE_SEL_MASK (1 << 13) +#define GSC_OUT_CHROM_STRIDE_SEPAR (1 << 13) +#define GSC_OUT_RB_SWAP_MASK (1 << 12) +#define GSC_OUT_RB_SWAP (1 << 12) +#define GSC_OUT_RGB_TYPE_MASK (3 << 10) +#define GSC_OUT_RGB_HD_NARROW (3 << 10) +#define GSC_OUT_RGB_HD_WIDE (2 << 10) +#define GSC_OUT_RGB_SD_NARROW (1 << 10) +#define GSC_OUT_RGB_SD_WIDE (0 << 10) +#define GSC_OUT_YUV422_1P_ORDER_MASK (1 << 9) +#define GSC_OUT_YUV422_1P_ORDER_LSB_Y (0 << 9) +#define GSC_OUT_YUV422_1P_OEDER_LSB_C (1 << 9) +#define GSC_OUT_CHROMA_ORDER_MASK (1 << 8) +#define GSC_OUT_CHROMA_ORDER_CBCR (0 << 8) +#define GSC_OUT_CHROMA_ORDER_CRCB (1 << 8) +#define GSC_OUT_FORMAT_MASK (7 << 4) +#define GSC_OUT_XRGB8888 (0 << 4) +#define GSC_OUT_RGB565 (1 << 4) +#define GSC_OUT_YUV420_2P (2 << 4) +#define GSC_OUT_YUV420_3P (3 << 4) +#define GSC_OUT_YUV422_1P (4 << 4) +#define GSC_OUT_YUV422_2P (5 << 4) +#define GSC_OUT_YUV444 (7 << 4) +#define GSC_OUT_TILE_TYPE_MASK (1 << 2) +#define GSC_OUT_TILE_C_16x8 (0 << 2) +#define GSC_OUT_TILE_C_16x16 (1 << 2) +#define GSC_OUT_TILE_MODE (1 << 1) +#define GSC_OUT_PATH_MASK (1 << 0) +#define GSC_OUT_PATH_LOCAL (1 << 0) +#define GSC_OUT_PATH_MEMORY (0 << 0)
+/* G-Scaler scaled destination image size */ +#define GSC_SCALED_SIZE 0x24 +#define GSC_SCALED_HEIGHT_MASK (0x1fff << 16) +#define GSC_SCALED_HEIGHT(x) ((x) << 16) +#define GSC_SCALED_WIDTH_MASK (0x1fff << 0) +#define GSC_SCALED_WIDTH(x) ((x) << 0)
+/* G-Scaler pre scale ratio */ +#define GSC_PRE_SCALE_RATIO 0x28 +#define GSC_PRESC_SHFACTOR_MASK (7 << 28) +#define GSC_PRESC_SHFACTOR(x) ((x) << 28) +#define GSC_PRESC_V_RATIO_MASK (7 << 16) +#define GSC_PRESC_V_RATIO(x) ((x) << 16) +#define GSC_PRESC_H_RATIO_MASK (7 << 0) +#define GSC_PRESC_H_RATIO(x) ((x) << 0)
+/* G-Scaler main scale horizontal ratio */ +#define GSC_MAIN_H_RATIO 0x2C +#define GSC_MAIN_H_RATIO_MASK (0xfffff << 0) +#define GSC_MAIN_H_RATIO_VALUE(x) ((x) << 0)
+/* G-Scaler main scale vertical ratio */ +#define GSC_MAIN_V_RATIO 0x30 +#define GSC_MAIN_V_RATIO_MASK (0xfffff << 0) +#define GSC_MAIN_V_RATIO_VALUE(x) ((x) << 0)
+/* G-Scaler input chrominance stride */ +#define GSC_IN_CHROM_STRIDE 0x3C +#define GSC_IN_CHROM_STRIDE_MASK (0x3fff << 0) +#define GSC_IN_CHROM_STRIDE_VALUE(x) ((x) << 0)
+/* G-Scaler destination image size */ +#define GSC_DSTIMG_SIZE 0x40 +#define GSC_DSTIMG_HEIGHT_MASK (0x1fff << 16) +#define GSC_DSTIMG_HEIGHT(x) ((x) << 16) +#define GSC_DSTIMG_WIDTH_MASK (0x1fff << 0) +#define GSC_DSTIMG_WIDTH(x) ((x) << 0)
+/* G-Scaler destination image offset */ +#define GSC_DSTIMG_OFFSET 0x44 +#define GSC_DSTIMG_OFFSET_Y_MASK (0x1fff << 16) +#define GSC_DSTIMG_OFFSET_Y(x) ((x) << 16) +#define GSC_DSTIMG_OFFSET_X_MASK (0x1fff << 0) +#define GSC_DSTIMG_OFFSET_X(x) ((x) << 0)
+/* G-Scaler output chrominance stride */ +#define GSC_OUT_CHROM_STRIDE 0x48 +#define GSC_OUT_CHROM_STRIDE_MASK (0x3fff << 0) +#define GSC_OUT_CHROM_STRIDE_VALUE(x) ((x) << 0)
+/* G-Scaler input y address mask */ +#define GSC_IN_BASE_ADDR_Y_MASK 0x4C +/* G-Scaler input y base address */ +#define GSC_IN_BASE_ADDR_Y(n) (0x50 + (n) * 0x4) +/* G-Scaler input y base current address */ +#define GSC_IN_BASE_ADDR_Y_CUR(n) (0x60 + (n) * 0x4)
+/* G-Scaler input cb address mask */ +#define GSC_IN_BASE_ADDR_CB_MASK 0x7C +/* G-Scaler input cb base address */ +#define GSC_IN_BASE_ADDR_CB(n) (0x80 + (n) * 0x4) +/* G-Scaler input cb base current address */ +#define GSC_IN_BASE_ADDR_CB_CUR(n) (0x90 + (n) * 0x4)
+/* G-Scaler input cr address mask */ +#define GSC_IN_BASE_ADDR_CR_MASK 0xAC +/* G-Scaler input cr base address */ +#define GSC_IN_BASE_ADDR_CR(n) (0xB0 + (n) * 0x4) +/* G-Scaler input cr base current address */ +#define GSC_IN_BASE_ADDR_CR_CUR(n) (0xC0 + (n) * 0x4)
+/* G-Scaler input address mask */ +#define GSC_IN_CURR_ADDR_INDEX (0xf << 24) +#define GSC_IN_CURR_GET_INDEX(x) ((x) >> 24) +#define GSC_IN_BASE_ADDR_PINGPONG(x) ((x) << 16) +#define GSC_IN_BASE_ADDR_MASK (0xff << 0)
+/* G-Scaler output y address mask */ +#define GSC_OUT_BASE_ADDR_Y_MASK 0x10C +/* G-Scaler output y base address */ +#define GSC_OUT_BASE_ADDR_Y(n) (0x110 + (n) * 0x4)
+/* G-Scaler output cb address mask */ +#define GSC_OUT_BASE_ADDR_CB_MASK 0x15C +/* G-Scaler output cb base address */ +#define GSC_OUT_BASE_ADDR_CB(n) (0x160 + (n) * 0x4)
+/* G-Scaler output cr address mask */ +#define GSC_OUT_BASE_ADDR_CR_MASK 0x1AC +/* G-Scaler output cr base address */ +#define GSC_OUT_BASE_ADDR_CR(n) (0x1B0 + (n) * 0x4)
+/* G-Scaler output address mask */ +#define GSC_OUT_CURR_ADDR_INDEX (0xf << 24) +#define GSC_OUT_CURR_GET_INDEX(x) ((x) >> 24) +#define GSC_OUT_BASE_ADDR_PINGPONG(x) ((x) << 16) +#define GSC_OUT_BASE_ADDR_MASK (0xffff << 0)
+/* G-Scaler horizontal scaling filter */ +#define GSC_HCOEF(n, s, x) (0x300 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
+/* G-Scaler vertical scaling filter */ +#define GSC_VCOEF(n, s, x) (0x200 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
+/* G-Scaler BUS control */ +#define GSC_BUSCON 0xA78 +#define GSC_BUSCON_INT_TIME_MASK (1 << 8) +#define GSC_BUSCON_INT_DATA_TRANS (0 << 8) +#define GSC_BUSCON_INT_AXI_RESPONSE (1 << 8) +#define GSC_BUSCON_AWCACHE(x) ((x) << 4) +#define GSC_BUSCON_ARCACHE(x) ((x) << 0)
+/* G-Scaler V position */ +#define GSC_VPOSITION 0xA7C +#define GSC_VPOS_F(x) ((x) << 0)
+/* G-Scaler clock initial count */ +#define GSC_CLK_INIT_COUNT 0xC00 +#define GSC_CLK_GATE_MODE_INIT_CNT(x) ((x) << 0)
+/* G-Scaler clock snoop count */ +#define GSC_CLK_SNOOP_COUNT 0xC04 +#define GSC_CLK_GATE_MODE_SNOOP_CNT(x) ((x) << 0)
+#endif /* EXYNOS_REGS_GSC_H_ */