[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #30 from Christian König deathsimple@vodafone.de --- (In reply to Chernovsky Oleg from comment #29)

No luck. Tried various hacks and commenting return values.

Will try mmiotracing these registers from fglrx on weekend

Be careful that to write no irrational values into the PLL registers, e.g. don't use partly radeon partly fglrx settings.

I once over clocked UVD to 4GHz instead of 400MHz by accident and the card is still working, but at least in theory you can damage the hardware with that.