On Fri, Apr 6, 2012 at 23:31, Jiri Slaby jslaby@suse.cz wrote:
That was introduced in 05eff845a28499762075d3a72e238a31f4d2407c to close a race where the pipestat triggered an interrupt after we processed the secondary registers and before reseting the primary.
But the basic premise that we should only enter the interrupt handler with IIR!=0 holds (presuming non-shared interrupt lines such as MSI).
Ok, this behavior is definitely new. I get several "nobody cared" about this interrupt a week. This never used to happen. And something weird emerges in /proc/interrupts when this happens: 42: 1003292 1212890 PCI-MSI-edge �s����:0000:00:02.0 instead of 42: 1006715 1218472 PCI-MSI-edge i915@pci:0000:00:02.0
This looks ugly. Can you try to reproduce on 3.4-rc2? That should contain everything that -next currently contains drm/i915-wise. If it still happens there, please bisect it.
Also please check whether any of the subordinate interrupt regs (pipestat) is stuck and might cause these interrupts as Jesse suggested.
Thanks, Daniel