tc_wait_pll_lock() is always called as a follow-up for updating PLLUPDATE and PLLEN bit of a given PLL control register. To simplify things, merge the two operation into a single helper function tc_pllupdate() and convert the rest of the code to use it. No functional change intended.
Signed-off-by: Andrey Smirnov andrew.smirnov@gmail.com Reviewed-by: Laurent Pinchart laurent.pinchart@ideasonboard.com Reviewed-by: Andrzej Hajda a.hajda@samsung.com Cc: Andrzej Hajda a.hajda@samsung.com Cc: Laurent Pinchart Laurent.pinchart@ideasonboard.com Cc: Tomi Valkeinen tomi.valkeinen@ti.com Cc: Andrey Gusakov andrey.gusakov@cogentembedded.com Cc: Philipp Zabel p.zabel@pengutronix.de Cc: Cory Tusar cory.tusar@zii.aero Cc: Chris Healy cphealy@gmail.com Cc: Lucas Stach l.stach@pengutronix.de Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org --- drivers/gpu/drm/bridge/tc358767.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 7a3a1b2d5c56..fe672f6bba73 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -427,10 +427,18 @@ static u32 tc_srcctrl(struct tc_data *tc) return reg; }
-static void tc_wait_pll_lock(struct tc_data *tc) +static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) { + int ret; + + ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); + if (ret) + return ret; + /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ usleep_range(3000, 6000); + + return 0; }
static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) @@ -530,13 +538,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) return ret;
/* Force PLL parameter update and disable bypass */ - ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLUPDATE | PLLEN); - if (ret) - return ret; - - tc_wait_pll_lock(tc); - - return 0; + return tc_pllupdate(tc, PXL_PLLCTRL); }
static int tc_pxl_pll_dis(struct tc_data *tc) @@ -610,15 +612,13 @@ static int tc_aux_link_setup(struct tc_data *tc) * Initially PLLs are in bypass. Force PLL parameter update, * disable PLL bypass, enable PLL */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP0_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc);
- ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP1_PLLCTRL); if (ret) goto err; - tc_wait_pll_lock(tc);
ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000); if (ret == -ETIMEDOUT) { @@ -898,15 +898,13 @@ static int tc_main_link_enable(struct tc_data *tc) return ret;
/* PLL setup */ - ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP0_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc);
- ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN); + ret = tc_pllupdate(tc, DP1_PLLCTRL); if (ret) return ret; - tc_wait_pll_lock(tc);
/* Reset/Enable Main Links */ dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;