On Tue, Feb 09, 2021 at 04:28:28PM -0500, Lyude Paul wrote:
Since Intel has introduced the gen9_bc platform, a combination of Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and avoid WARNing on them.
Changes since v4:
- Split this into it's own patch - vsyrjala
Cc: Matt Roper matthew.d.roper@intel.com Cc: Jani Nikula jani.nikula@linux.intel.com Cc: Ville Syrjala ville.syrjala@linux.intel.com [originally from Tejas's work] Signed-off-by: Tejas Upadhyay tejaskumarx.surendrakumar.upadhyay@intel.com Signed-off-by: Lyude Paul lyude@redhat.com
Reviewed-by: Rodrigo Vivi rodrigo.vivi@intel.com
drivers/gpu/drm/i915/intel_pch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 4813207fc053..7476f0e063c6 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_TGP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
!IS_ROCKETLAKE(dev_priv));
!IS_ROCKETLAKE(dev_priv) &&!IS_GEN9_BC(dev_priv));-- 2.29.2
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