[PATCH v2 01/26] drm/amd/dal: Add dal headers

Signed-off-by: Harry Wentland harry.wentland@amd.com Reviewed-by: Alex Deucher alexander.deucher@amd.com --- drivers/gpu/drm/amd/dal/dal_services.h | 266 ++++++ drivers/gpu/drm/amd/dal/dal_services_types.h | 62 ++ drivers/gpu/drm/amd/dal/dc/dc.h | 462 ++++++++++ drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 277 ++++++ drivers/gpu/drm/amd/dal/dc/dc_types.h | 936 +++++++++++++++++++++ drivers/gpu/drm/amd/dal/dc/dm_helpers.h | 98 +++ drivers/gpu/drm/amd/dal/dc/dm_services.h | 485 +++++++++++ drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 167 ++++ drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 510 +++++++++++ drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h | 64 ++ drivers/gpu/drm/amd/dal/dc/inc/clock_source.h | 176 ++++ drivers/gpu/drm/amd/dal/dc/inc/compressor.h | 140 +++ drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 54 ++ drivers/gpu/drm/amd/dal/dc/inc/core_status.h | 46 + drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 357 ++++++++ drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h | 151 ++++ drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h | 56 ++ drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h | 118 +++ drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 126 +++ drivers/gpu/drm/amd/dal/dc/inc/ipp.h | 106 +++ drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h | 138 +++ drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 68 ++ drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 83 ++ drivers/gpu/drm/amd/dal/dc/inc/opp.h | 308 +++++++ drivers/gpu/drm/amd/dal/dc/inc/resource.h | 80 ++ drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h | 88 ++ drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h | 155 ++++ drivers/gpu/drm/amd/dal/dc/inc/transform.h | 217 +++++ drivers/gpu/drm/amd/dal/dc/irq_types.h | 199 +++++ .../amd/dal/include/adapter_service_interface.h | 632 ++++++++++++++ .../drm/amd/dal/include/adapter_service_types.h | 71 ++ .../amd/dal/include/asic_capability_interface.h | 58 ++ .../drm/amd/dal/include/asic_capability_types.h | 134 +++ drivers/gpu/drm/amd/dal/include/audio_interface.h | 184 ++++ drivers/gpu/drm/amd/dal/include/audio_types.h | 277 ++++++ .../drm/amd/dal/include/bios_parser_interface.h | 98 +++ .../gpu/drm/amd/dal/include/bios_parser_types.h | 327 +++++++ drivers/gpu/drm/amd/dal/include/dal_asic_id.h | 117 +++ .../gpu/drm/amd/dal/include/dal_register_logger.h | 43 + drivers/gpu/drm/amd/dal/include/dal_types.h | 305 +++++++ .../amd/dal/include/dc_clock_generator_interface.h | 77 ++ drivers/gpu/drm/amd/dal/include/dcs_types.h | 742 ++++++++++++++++ drivers/gpu/drm/amd/dal/include/ddc_interface.h | 74 ++ .../gpu/drm/amd/dal/include/ddc_service_types.h | 221 +++++ .../drm/amd/dal/include/display_clock_interface.h | 186 ++++ .../drm/amd/dal/include/display_path_interface.h | 436 ++++++++++ drivers/gpu/drm/amd/dal/include/dmcu_interface.h | 87 ++ drivers/gpu/drm/amd/dal/include/dmcu_types.h | 199 +++++ drivers/gpu/drm/amd/dal/include/dpcd_defs.h | 873 +++++++++++++++++++ .../gpu/drm/amd/dal/include/encoder_interface.h | 278 ++++++ drivers/gpu/drm/amd/dal/include/fixed31_32.h | 389 +++++++++ drivers/gpu/drm/amd/dal/include/fixed32_32.h | 82 ++ drivers/gpu/drm/amd/dal/include/gpio_interface.h | 93 ++ .../drm/amd/dal/include/gpio_service_interface.h | 81 ++ drivers/gpu/drm/amd/dal/include/gpio_types.h | 341 ++++++++ drivers/gpu/drm/amd/dal/include/grph_csc_types.h | 98 +++ .../drm/amd/dal/include/grph_object_ctrl_defs.h | 593 +++++++++++++ drivers/gpu/drm/amd/dal/include/grph_object_defs.h | 328 ++++++++ drivers/gpu/drm/amd/dal/include/grph_object_id.h | 277 ++++++ .../drm/amd/dal/include/hw_sequencer_interface.h | 388 +++++++++ .../gpu/drm/amd/dal/include/hw_sequencer_types.h | 304 +++++++ drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 127 +++ drivers/gpu/drm/amd/dal/include/irq_interface.h | 53 ++ .../drm/amd/dal/include/irq_service_interface.h | 55 ++ .../drm/amd/dal/include/link_service_interface.h | 202 +++++ .../gpu/drm/amd/dal/include/link_service_types.h | 427 ++++++++++ drivers/gpu/drm/amd/dal/include/logger_interface.h | 153 ++++ drivers/gpu/drm/amd/dal/include/logger_types.h | 356 ++++++++ drivers/gpu/drm/amd/dal/include/scaler_types.h | 196 +++++ drivers/gpu/drm/amd/dal/include/set_mode_types.h | 142 ++++ drivers/gpu/drm/amd/dal/include/signal_types.h | 59 ++ drivers/gpu/drm/amd/dal/include/vector.h | 150 ++++ drivers/gpu/drm/amd/dal/include/video_csc_types.h | 135 +++ .../gpu/drm/amd/dal/include/video_gamma_types.h | 57 ++ 74 files changed, 16498 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dal_services.h create mode 100644 drivers/gpu/drm/amd/dal/dal_services_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_bios_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dc_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_helpers.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_services.h create mode 100644 drivers/gpu/drm/amd/dal/dc/dm_services_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/clock_source.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/compressor.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_dc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_status.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/core_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/ipp.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/mem_input.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/opp.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/resource.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h create mode 100644 drivers/gpu/drm/amd/dal/dc/inc/transform.h create mode 100644 drivers/gpu/drm/amd/dal/dc/irq_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/adapter_service_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/asic_capability_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/audio_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/audio_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/dal_asic_id.h create mode 100644 drivers/gpu/drm/amd/dal/include/dal_register_logger.h create mode 100644 drivers/gpu/drm/amd/dal/include/dal_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/display_clock_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/display_path_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_defs.h create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/fixed31_32.h create mode 100644 drivers/gpu/drm/amd/dal/include/fixed32_32.h create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_service_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/grph_csc_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_defs.h create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_id.h create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/i2caux_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/irq_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/irq_service_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/logger_interface.h create mode 100644 drivers/gpu/drm/amd/dal/include/logger_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/scaler_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/signal_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/vector.h create mode 100644 drivers/gpu/drm/amd/dal/include/video_csc_types.h create mode 100644 drivers/gpu/drm/amd/dal/include/video_gamma_types.h

diff --git a/drivers/gpu/drm/amd/dal/dal_services.h b/drivers/gpu/drm/amd/dal/dal_services.h new file mode 100644 index 000000000000..398e4e559455 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dal_services.h @@ -0,0 +1,266 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_SERVICES_H__ +#define __DAL_SERVICES_H__ + +/* DC headers*/ +#include "dc/dc_services.h" + +#include "dal_power_interface_types.h" + +#include "irq_types.h" +#include "include/dal_types.h" + +/* TODO: investigate if it can be removed. */ +/* Undefine DEPRECATED because it conflicts with printk.h */ +#undef DEPRECATED + +/* + * + * interrupt services to register and unregister handlers + * + */ + +/* the timer "interrupt" current implementation supports only +'one-shot' type, and LOW level (asynchronous) context */ +void dal_register_timer_interrupt( + struct dc_context *ctx, + struct dc_timer_interrupt_params *int_params, + interrupt_handler ih, + void *handler_args); + +/* + * + * kernel memory manipulation + * + */ + +/* Reallocate memory. The contents will remain unchanged.*/ +void *dc_service_realloc(struct dc_context *ctx, const void *ptr, uint32_t size); + +void dc_service_memmove(void *dst, const void *src, uint32_t size); + +void dc_service_memset(void *p, int32_t c, uint32_t count); + +int32_t dal_memcmp(const void *p1, const void *p2, uint32_t count); + +int32_t dal_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count); + +/* + * + * GPU registers access + * + */ +static inline uint32_t dal_read_reg( + const struct dc_context *ctx, + uint32_t address) +{ + uint32_t value = cgs_read_register(ctx->cgs_device, address); + +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value); + } +#endif + return value; +} + +static inline uint32_t get_reg_field_value_ex( + uint32_t reg_value, + uint32_t mask, + uint8_t shift) +{ + return (mask & reg_value) >> shift; +} + +#define get_reg_field_value(reg_value, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +static inline uint32_t set_reg_field_value_ex( + uint32_t reg_value, + uint32_t value, + uint32_t mask, + uint8_t shift) +{ + return (reg_value & ~mask) | (mask & (value << shift)); +} + +#define set_reg_field_value(reg_value, value, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +static inline void dal_write_reg( + const struct dc_context *ctx, + uint32_t address, + uint32_t value) +{ +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value); + } +#endif + cgs_write_register(ctx->cgs_device, address, value); +} + +static inline uint32_t dal_read_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index) +{ + return cgs_read_ind_register(ctx->cgs_device,addr_space,index); +} + +static inline void dal_write_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index, + uint32_t value) +{ + cgs_write_ind_register(ctx->cgs_device,addr_space,index,value); +} + +enum platform_method { + PM_GET_AVAILABLE_METHODS = 1 << 0, + PM_GET_LID_STATE = 1 << 1, + PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2 +}; + +struct platform_info_params { + enum platform_method method; + void *data; +}; + +struct platform_info_brightness_caps { + uint8_t ac_level_percentage; + uint8_t dc_level_percentage; +}; + +struct platform_info_ext_brightness_caps { + struct platform_info_brightness_caps basic_caps; + struct data_point { + uint8_t luminance; + uint8_t signal_level; + } data_points[99]; + + uint8_t data_points_num; + uint8_t min_input_signal; + uint8_t max_input_signal; +}; + +bool dal_get_platform_info( + struct dc_context *ctx, + struct platform_info_params *params); + + +static inline uint32_t dal_bios_cmd_table_para_revision( + struct dc_context *ctx, + uint32_t index) +{ + uint8_t frev; + uint8_t crev; + + if (cgs_atom_get_cmd_table_revs( + ctx->cgs_device, + index, + &frev, + &crev) != 0) + return 0; + + return crev; +} + +/* Calls to notification */ + +/* Notify display manager for hotplug event */ +void dal_notify_hotplug( + struct dc_context *ctx, + uint32_t display_index, + bool is_connected); + + +void dal_notify_setmode_complete( + struct dc_context *ctx, + uint32_t h_total, + uint32_t v_total, + uint32_t h_active, + uint32_t v_active, + uint32_t pix_clk_in_khz); + +/* End of notification calls */ + +/* + * + * Delay functions. + * + * + */ + +/* Following the guidance: + * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt + * + * This is a busy wait for nano seconds and should be used only for + * extremely short ranges + */ +void dal_delay_in_nanoseconds(uint32_t nanoseconds); + + +/* + * + * atombios services + * + */ + +bool dal_exec_bios_cmd_table( + struct dc_context *ctx, + uint32_t index, + void *params); + +/* + * + * print-out services + * + */ +#define dal_log_to_buffer(buffer, size, fmt, args)\ + vsnprintf(buffer, size, fmt, args) + +long dal_get_pid(void); +long dal_get_tgid(void); + +/* + * + * general debug capabilities + * + */ + +#endif /* __DAL_SERVICES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dal_services_types.h b/drivers/gpu/drm/amd/dal/dal_services_types.h new file mode 100644 index 000000000000..89c73c651d09 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dal_services_types.h @@ -0,0 +1,62 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_SERVICES_TYPES_H__ +#define __DAL_SERVICES_TYPES_H__ + +#define INVALID_DISPLAY_INDEX 0xffffffff + +#if defined __KERNEL__ + +#include <asm/byteorder.h> +#include <linux/types.h> +#include <drm/drmP.h> + +#include "cgs_linux.h" + +#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU) +#define BIGENDIAN_CPU +#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU) +#define LITTLEENDIAN_CPU +#endif + +#undef READ +#undef WRITE +#undef FRAME_SIZE + +#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__) + +#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__) + +#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__) + +#define dal_vlog(fmt, args) vprintk(fmt, args) + +#define dal_min(x, y) min(x, y) +#define dal_max(x, y) max(x, y) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h new file mode 100644 index 000000000000..61f13bd0af49 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dc.h @@ -0,0 +1,462 @@ +/* + * Copyright 2012-14 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_INTERFACE_H_ +#define DC_INTERFACE_H_ + +#include "dc_types.h" +#include "dal_types.h" +#include "audio_types.h" +#include "logger_types.h" + +#define MAX_SINKS_PER_LINK 4 + +/******************************************************************************* + * Display Core Interfaces + ******************************************************************************/ +struct dc_init_data { + struct dc_context *ctx; + struct adapter_service *adapter_srv; + uint8_t num_virtual_links; +}; + +struct dc_caps { + uint32_t max_targets; + uint32_t max_links; + uint32_t max_audios; +}; + +void dc_get_caps(const struct dc *dc, struct dc_caps *caps); + +struct dc *dc_create(const struct dal_init_data *init_params); +void dc_destroy(struct dc **dc); + +/******************************************************************************* + * Surface Interfaces + ******************************************************************************/ + +struct dc_surface { + bool visible; + bool flip_immediate; + struct dc_plane_address address; + + struct scaling_taps scaling_quality; + struct rect src_rect; + struct rect dst_rect; + struct rect clip_rect; + + union plane_size plane_size; + struct dc_tiling_info tiling_info; + struct plane_colorimetry colorimetry; + + enum surface_pixel_format format; + enum dc_rotation_angle rotation; + enum plane_stereo_format stereo_format; + + struct gamma_ramp gamma_correction; /* deprecated */ + struct dc_gamma_ramp gamma; +}; + +/* + * This structure is filled in by dc_surface_get_status and contains + * the last requested address and the currently active address so the called + * can determine if there are any outstanding flips + */ +struct dc_surface_status { + struct dc_plane_address requested_address; + struct dc_plane_address current_address; + const struct dc_target *dc_target; +}; + +/* + * Create a new surface with default parameters; + */ +struct dc_surface *dc_create_surface(const struct dc *dc); +const struct dc_surface_status* dc_surface_get_status( + struct dc_surface *dc_surface); + +void dc_surface_retain(const struct dc_surface *dc_surface); +void dc_surface_release(const struct dc_surface *dc_surface); + +/* + * This structure holds a surface address. There could be multiple addresses + * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such + * as frame durations and DCC format can also be set. + */ +struct dc_flip_addrs { + struct dc_plane_address address; + bool flip_immediate; + /* TODO: DCC format info */ + /* TODO: add flip duration for FreeSync */ +}; + +/* + * Optimized flip address update function. + * + * After this call: + * Surface addresses and flip attributes are programmed. + * Surface flip occur at next configured time (h_sync or v_sync flip) + */ +void dc_flip_surface_addrs(struct dc* dc, + const struct dc_surface *const surfaces[], + struct dc_flip_addrs flip_addrs[], + uint32_t count); + +/* + * Set up surface attributes and associate to a target + * The surfaces parameter is an absolute set of all surface active for the target. + * If no surfaces are provided, the target will be blanked; no memory read. + * Any flip related attribute changes must be done through this interface. + * + * After this call: + * Surfaces attributes are programmed and configured to be composed into target. + * This does not trigger a flip. No surface address is programmed. + */ +bool dc_commit_surfaces_to_target( + struct dc *dc, + struct dc_surface *dc_surfaces[], + uint8_t surface_count, + struct dc_target *dc_target); + +/******************************************************************************* + * Target Interfaces + ******************************************************************************/ +#define MAX_STREAM_NUM 1 + +struct dc_target { + uint8_t stream_count; + const struct dc_stream *streams[MAX_STREAM_NUM]; +}; + +/* + * Target status is returned from dc_target_get_status in order to get the + * the IRQ source, current frame counter and currently attached surfaces. + */ +struct dc_target_status { + enum dc_irq_source page_flip_src; + enum dc_irq_source v_update_src; + uint32_t cur_frame_count; + const struct dc_surface *surfaces[MAX_SURFACE_NUM]; + uint8_t surface_count; +}; + +struct dc_target *dc_create_target_for_streams( + struct dc_stream *dc_streams[], + uint8_t stream_count); + +/* + * Get the current target status. + */ +const struct dc_target_status *dc_target_get_status( + const struct dc_target* dc_target); + +void dc_target_retain(struct dc_target *dc_target); +void dc_target_release(struct dc_target *dc_target); +void dc_target_log( + const struct dc_target *dc_target, + struct dal_logger *dal_logger, + enum log_major log_major, + enum log_minor log_minor); + +uint8_t dc_get_current_target_count(const struct dc *dc); +struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i); + +bool dc_target_is_connected_to_sink( + const struct dc_target *dc_target, + const struct dc_sink *dc_sink); + +uint8_t dc_target_get_link_index(const struct dc_target *dc_target); +uint8_t dc_target_get_controller_id(const struct dc_target *dc_target); + +uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target); +enum dc_irq_source dc_target_get_irq_src( + const struct dc_target *dc_target, const enum irq_type irq_type); + +void dc_target_enable_memory_requests(struct dc_target *target); +void dc_target_disable_memory_requests(struct dc_target *target); + +/* + * Structure to store surface/target associations for validation + */ +struct dc_validation_set { + const struct dc_target *target; + const struct dc_surface *surfaces[4]; + uint8_t surface_count; +}; + +/* + * This function takes a set of resources and checks that they are cofunctional. + * + * After this call: + * No hardware is programmed for call. Only validation is done. + */ +bool dc_validate_resources( + const struct dc *dc, + const struct dc_validation_set set[], + uint8_t set_count); + +/* + * Set up streams and links associated to targets to drive sinks + * The targets parameter is an absolute set of all active targets. + * + * After this call: + * Phy, Encoder, Timing Generator are programmed and enabled. + * New targets are enabled with blank stream; no memory read. + */ +bool dc_commit_targets( + struct dc *dc, + struct dc_target *targets[], + uint8_t target_count); + +/******************************************************************************* + * Stream Interfaces + ******************************************************************************/ +struct dc_stream { + const struct dc_sink *sink; + struct dc_crtc_timing timing; + + struct rect src; /* viewport in target space*/ + struct rect dst; /* stream addressable area */ + + struct audio_info audio_info; + + /* TODO: dithering */ + /* TODO: transfer function (CSC/regamma/gamut remap) */ + /* TODO: custom INFO packets */ + /* TODO: DRR/Freesync parameters */ + /* TODO: ABM info (DMCU) */ + /* TODO: PSR info */ + /* TODO: CEA VIC */ +}; + +/** + * Create a new default stream for the requested sink + */ +struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); + +void dc_stream_retain(struct dc_stream *dc_stream); +void dc_stream_release(struct dc_stream *dc_stream); + +void dc_update_stream(const struct dc_stream *dc_stream, + struct rect *src, struct rect *dst); + +/******************************************************************************* + * Link Interfaces + ******************************************************************************/ + +/* + * A link contains one or more sinks and their connected status. + * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. + */ +struct dc_link { + const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; + unsigned int sink_count; + const struct dc_sink *local_sink; + unsigned int link_index; + enum dc_connection_type type; + enum signal_type connector_signal; + enum dc_irq_source irq_source_hpd; + enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ +}; + +/* + * Return an enumerated dc_link. dc_link order is constant and determined at + * boot time. They cannot be created or destroyed. + * Use dc_get_caps() to get number of links. + */ +const struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); + +/* Return id of physical connector represented by a dc_link at link_index.*/ +const struct graphics_object_id dc_get_link_id_at_index( + struct dc *dc, uint32_t link_index); + +/* Set backlight level of an embedded panel (eDP, LVDS). */ +bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level); + +/* Request DC to detect if there is a Panel connected. + * boot - If this call is during initial boot. + * Return false for any type of detection failure or MST detection + * true otherwise. True meaning further action is required (status update + * and OS notification). + */ +bool dc_link_detect(const struct dc_link *dc_link, bool boot); + +/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. */ +bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link); + +bool dc_link_add_remote_sink(const struct dc_link *link, struct dc_sink *sink); + +void dc_link_remove_remote_sink( + const struct dc_link *link, + const struct dc_sink *sink); + +/* Used by diagnostics for virtual link at the moment */ +void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink); + +/******************************************************************************* + * Sink Interfaces - A sink corresponds to a display output device + ******************************************************************************/ + +/* + * The sink structure contains EDID and other display device properties + */ +struct dc_sink { + enum signal_type sink_signal; + struct dc_edid dc_edid; /* raw edid */ + struct dc_edid_caps edid_caps; /* parse display caps */ +}; + +void dc_sink_retain(const struct dc_sink *sink); +void dc_sink_release(const struct dc_sink *sink); + +const struct audio **dc_get_audios(struct dc *dc); + +struct dc_sink_init_data { + enum signal_type sink_signal; + const struct dc_link *link; + uint32_t dongle_max_pix_clk; + bool converter_disable_audio; +}; + +struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); + + +/******************************************************************************* + * Cursor interfaces - To manages the cursor within a target + ******************************************************************************/ +/* TODO: Deprecated once we switch to dc_set_cursor_position */ +bool dc_target_set_cursor_attributes( + struct dc_target *dc_target, + const struct dc_cursor_attributes *attributes); + +bool dc_target_set_cursor_position( + struct dc_target *dc_target, + const struct dc_cursor_position *position); + +/* Newer interfaces */ +struct dc_cursor { + struct dc_plane_address address; + struct dc_cursor_attributes attributes; +}; + +/* + * Create a new cursor with default values for a given target. + */ +struct dc_cursor *dc_create_cursor_for_target( + const struct dc *dc, + struct dc_target *dc_target); + +/** + * Commit cursor attribute changes such as pixel format and dimensions and + * surface address. + * + * After this call: + * Cursor address and format is programmed to the new values. + * Cursor position is unmodified. + */ +bool dc_commit_cursor( + const struct dc *dc, + struct dc_cursor *cursor); + +/* + * Optimized cursor position update + * + * After this call: + * Cursor position will be programmed as well as enable/disable bit. + */ +bool dc_set_cursor_position( + const struct dc *dc, + struct dc_cursor *cursor, + struct dc_cursor_position *pos); + + + +/******************************************************************************* + * Interrupt interfaces + ******************************************************************************/ +enum dc_irq_source dc_interrupt_to_irq_source( + struct dc *dc, + uint32_t src_id, + uint32_t ext_id); +void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); +void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); +const enum dc_irq_source dc_get_hpd_irq_source_at_index( + struct dc *dc, uint32_t link_index); +const struct dc_target *dc_get_target_on_irq_source( + const struct dc *dc, + enum dc_irq_source src); + + +/******************************************************************************* + * Power Interfaces + ******************************************************************************/ + +void dc_set_power_state( + struct dc *dc, + enum dc_acpi_cm_power_state power_state, + enum dc_video_power_state video_power_state); +void dc_resume(const struct dc *dc); + +/******************************************************************************* + * DDC Interfaces + ******************************************************************************/ + +const struct ddc_service *dc_get_ddc_at_index( + struct dc *dc, uint32_t link_index); + +/* + * DPCD access interfaces + */ + +bool dc_read_dpcd( + struct dc *dc, + uint32_t link_index, + uint32_t address, + uint8_t *data, + uint32_t size); + +bool dc_write_dpcd( + struct dc *dc, + uint32_t link_index, + uint32_t address, + const uint8_t *data, + uint32_t size); + + +uint8_t dc_get_dig_index(const struct dc_stream *stream); + +enum signal_type dc_get_display_signal( + const struct dc_stream *stream); + +enum gpio_ddc_line dc_get_ddc_line( + const struct dc_stream *stream); + + +#endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h new file mode 100644 index 000000000000..53f047788b31 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h @@ -0,0 +1,277 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_BIOS_TYPES_H +#define DC_BIOS_TYPES_H + +/****************************************************************************** + * Interface file for VBIOS implementations. + * + * The default implementation is inside DC. + * Display Manager (which instantiates DC) has the option to supply it's own + * (external to DC) implementation of VBIOS, which will be called by DC, using + * this interface. + * (The intended use is Diagnostics, but other uses may appear.) + *****************************************************************************/ + +#include "include/bios_parser_types.h" + + +struct dc_vbios_funcs { + uint8_t (*get_connectors_number)(struct dc_bios *bios); + + void (*power_down)(struct dc_bios *bios); + void (*power_up)(struct dc_bios *bios); + + uint8_t (*get_encoders_number)(struct dc_bios *bios); + uint32_t (*get_oem_ddc_lines_number)(struct dc_bios *bios); + + struct graphics_object_id (*get_encoder_id)( + struct dc_bios *bios, + uint32_t i); + struct graphics_object_id (*get_connector_id)( + struct dc_bios *bios, + uint8_t connector_index); + uint32_t (*get_src_number)( + struct dc_bios *bios, + struct graphics_object_id id); + uint32_t (*get_dst_number)( + struct dc_bios *bios, + struct graphics_object_id id); + + uint32_t (*get_gpio_record)( + struct dc_bios *dcb, + struct graphics_object_id id, + struct bp_gpio_cntl_info *gpio_record, + uint32_t record_size); + + enum bp_result (*get_src_obj)( + struct dc_bios *bios, + struct graphics_object_id object_id, uint32_t index, + struct graphics_object_id *src_object_id); + enum bp_result (*get_dst_obj)( + struct dc_bios *bios, + struct graphics_object_id object_id, uint32_t index, + struct graphics_object_id *dest_object_id); + enum bp_result (*get_oem_ddc_info)( + struct dc_bios *bios, + uint32_t index, + struct graphics_object_i2c_info *info); + + enum bp_result (*get_i2c_info)( + struct dc_bios *dcb, + struct graphics_object_id id, + struct graphics_object_i2c_info *info); + + enum bp_result (*get_voltage_ddc_info)( + struct dc_bios *bios, + uint32_t index, + struct graphics_object_i2c_info *info); + enum bp_result (*get_thermal_ddc_info)( + struct dc_bios *bios, + uint32_t i2c_channel_id, + struct graphics_object_i2c_info *info); + enum bp_result (*get_hpd_info)( + struct dc_bios *bios, + struct graphics_object_id id, + struct graphics_object_hpd_info *info); + enum bp_result (*get_device_tag)( + struct dc_bios *bios, + struct graphics_object_id connector_object_id, + uint32_t device_tag_index, + struct connector_device_tag_info *info); + enum bp_result (*get_firmware_info)( + struct dc_bios *bios, + struct firmware_info *info); + enum bp_result (*get_spread_spectrum_info)( + struct dc_bios *bios, + enum as_signal_type signal, + uint32_t index, + struct spread_spectrum_info *ss_info); + uint32_t (*get_ss_entry_number)( + struct dc_bios *bios, + enum as_signal_type signal); + enum bp_result (*get_embedded_panel_info)( + struct dc_bios *bios, + struct embedded_panel_info *info); + enum bp_result (*enum_embedded_panel_patch_mode)( + struct dc_bios *bios, + uint32_t index, + struct embedded_panel_patch_mode *mode); + enum bp_result (*get_gpio_pin_info)( + struct dc_bios *bios, + uint32_t gpio_id, + struct gpio_pin_info *info); + enum bp_result (*get_faked_edid_len)( + struct dc_bios *bios, + uint32_t *len); + enum bp_result (*get_faked_edid_buf)( + struct dc_bios *bios, + uint8_t *buff, + uint32_t len); + enum bp_result (*get_encoder_cap_info)( + struct dc_bios *bios, + struct graphics_object_id object_id, + struct bp_encoder_cap_info *info); + enum bp_result (*get_din_connector_info)( + struct dc_bios *bios, + struct graphics_object_id id, + struct din_connector_info *info); + + bool (*is_lid_open)( + struct dc_bios *bios); + bool (*is_lid_status_changed)( + struct dc_bios *bios); + bool (*is_display_config_changed)( + struct dc_bios *bios); + bool (*is_accelerated_mode)( + struct dc_bios *bios); + void (*set_scratch_lcd_scale)( + struct dc_bios *bios, + enum lcd_scale scale); + enum lcd_scale (*get_scratch_lcd_scale)( + struct dc_bios *bios); + void (*get_bios_event_info)( + struct dc_bios *bios, + struct bios_event_info *info); + void (*update_requested_backlight_level)( + struct dc_bios *bios, + uint32_t backlight_8bit); + uint32_t (*get_requested_backlight_level)( + struct dc_bios *bios); + void (*take_backlight_control)( + struct dc_bios *bios, + bool cntl); + bool (*is_active_display)( + struct dc_bios *bios, + enum signal_type signal, + const struct connector_device_tag_info *device_tag); + enum controller_id (*get_embedded_display_controller_id)( + struct dc_bios *bios); + uint32_t (*get_embedded_display_refresh_rate)( + struct dc_bios *bios); + void (*set_scratch_connected)( + struct dc_bios *bios, + struct graphics_object_id connector_id, + bool connected, + const struct connector_device_tag_info *device_tag); + void (*prepare_scratch_active_and_requested)( + struct dc_bios *bios, + enum controller_id controller_id, + enum signal_type signal, + const struct connector_device_tag_info *device_tag); + void (*set_scratch_active_and_requested)( + struct dc_bios *bios); + void (*set_scratch_critical_state)( + struct dc_bios *bios, + bool state); + void (*set_scratch_acc_mode_change)( + struct dc_bios *bios); + + bool (*is_device_id_supported)( + struct dc_bios *bios, + struct device_id id); + + /* COMMANDS */ + + enum bp_result (*encoder_control)( + struct dc_bios *bios, + struct bp_encoder_control *cntl); + enum bp_result (*transmitter_control)( + struct dc_bios *bios, + struct bp_transmitter_control *cntl); + enum bp_result (*crt_control)( + struct dc_bios *bios, + enum engine_id engine_id, + bool enable, + uint32_t pixel_clock); + enum bp_result (*enable_crtc)( + struct dc_bios *bios, + enum controller_id id, + bool enable); + enum bp_result (*adjust_pixel_clock)( + struct dc_bios *bios, + struct bp_adjust_pixel_clock_parameters *bp_params); + enum bp_result (*set_pixel_clock)( + struct dc_bios *bios, + struct bp_pixel_clock_parameters *bp_params); + enum bp_result (*set_dce_clock)( + struct dc_bios *bios, + struct bp_set_dce_clock_parameters *bp_params); + enum bp_result (*enable_spread_spectrum_on_ppll)( + struct dc_bios *bios, + struct bp_spread_spectrum_parameters *bp_params, + bool enable); + enum bp_result (*program_crtc_timing)( + struct dc_bios *bios, + struct bp_hw_crtc_timing_parameters *bp_params); + enum bp_result (*blank_crtc)( + struct dc_bios *bios, + struct bp_blank_crtc_parameters *bp_params, + bool blank); + enum bp_result (*set_overscan)( + struct dc_bios *bios, + struct bp_hw_crtc_overscan_parameters *bp_params); + enum bp_result (*crtc_source_select)( + struct dc_bios *bios, + struct bp_crtc_source_select *bp_params); + enum bp_result (*program_display_engine_pll)( + struct dc_bios *bios, + struct bp_pixel_clock_parameters *bp_params); + enum bp_result (*get_divider_for_target_display_clock)( + struct dc_bios *bios, + struct bp_display_clock_parameters *bp_params); + enum signal_type (*dac_load_detect)( + struct dc_bios *bios, + struct graphics_object_id encoder, + struct graphics_object_id connector, + enum signal_type display_signal); + enum bp_result (*enable_memory_requests)( + struct dc_bios *bios, + enum controller_id controller_id, + bool enable); + enum bp_result (*external_encoder_control)( + struct dc_bios *bios, + struct bp_external_encoder_control *cntl); + enum bp_result (*enable_disp_power_gating)( + struct dc_bios *bios, + enum controller_id controller_id, + enum bp_pipe_control_action action); + + void (*post_init)(struct dc_bios *bios); + + struct integrated_info *(*create_integrated_info)( + struct dc_bios *bios); + + void (*destroy_integrated_info)( + struct dc_bios *dcb, + struct integrated_info **info); +}; + +struct dc_bios { + const struct dc_vbios_funcs *funcs; +}; + +#endif /* DC_BIOS_TYPES_H */ diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h new file mode 100644 index 000000000000..c238531dc6c0 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h @@ -0,0 +1,936 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef DC_TYPES_H_ +#define DC_TYPES_H_ + +#include "dm_services_types.h" +#include "fixed32_32.h" +#include "fixed31_32.h" +#include "irq_types.h" + +/* forward declarations */ +struct dc; +struct dc_surface; +struct dc_target; +struct dc_stream; +struct dc_link; +struct dc_sink; +struct dal; + +/******************************** + * Environment definitions + ********************************/ +enum dce_environment { + DCE_ENV_PRODUCTION_DRV = 0, + /* Emulation on FPGA, in "Maximus" System. + * This environment enforces that *only* DC registers accessed. + * (access to non-DC registers will hang FPGA) */ + DCE_ENV_FPGA_MAXIMUS, + /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces + * requirements of Diagnostics team. */ + DCE_ENV_DIAG +}; + +/* Note: use these macro definitions instead of direct comparison! */ +#define IS_FPGA_MAXIMUS_DC(dce_environment) \ + (dce_environment == DCE_ENV_FPGA_MAXIMUS) + +#define IS_DIAG_DC(dce_environment) \ + (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) + +/********************************/ + +#define MAX_EDID_BUFFER_SIZE 512 +#define MAX_SURFACE_NUM 2 +#define NUM_PIXEL_FORMATS 10 + +enum surface_color_space { + SURFACE_COLOR_SPACE_SRGB = 0x0000, + SURFACE_COLOR_SPACE_BT601 = 0x0001, + SURFACE_COLOR_SPACE_BT709 = 0x0002, + SURFACE_COLOR_SPACE_XVYCC_BT601 = 0x0004, + SURFACE_COLOR_SPACE_XVYCC_BT709 = 0x0008, + SURFACE_COLOR_SPACE_XRRGB = 0x0010 +}; + +/*Displayable pixel format in fb*/ +enum surface_pixel_format { + SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, + /*TOBE REMOVED paletta 256 colors*/ + SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = + SURFACE_PIXEL_FORMAT_GRPH_BEGIN, + /*16 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, + /*16 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_RGB565, + /*32 bpp*/ + SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, + /*32 bpp swaped*/ + SURFACE_PIXEL_FORMAT_GRPH_BGRA8888, + + SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, + /*swaped*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, + /*TOBE REMOVED swaped, XR_BIAS has no differance + * for pixel layout than previous and we can + * delete this after discusion*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, + /*64 bpp */ + SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, + /*swaped & float*/ + SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, + /*grow graphics here if necessary */ + + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = + SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, + SURFACE_PIXEL_FORMAT_VIDEO_422_YCb, + SURFACE_PIXEL_FORMAT_VIDEO_422_YCr, + SURFACE_PIXEL_FORMAT_VIDEO_422_CbY, + SURFACE_PIXEL_FORMAT_VIDEO_422_CrY, + /*grow 422/420 video here if necessary */ + SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb1555 = + SURFACE_PIXEL_FORMAT_VIDEO_444_BEGIN, + SURFACE_PIXEL_FORMAT_VIDEO_444_CrYCb565, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb4444, + SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA5551, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb8888, + SURFACE_PIXEL_FORMAT_VIDEO_444_ACrYCb2101010, + SURFACE_PIXEL_FORMAT_VIDEO_444_CbYCrA1010102 + /*grow 444 video here if necessary */ +}; + + +/* Pixel format */ +enum pixel_format { + /*graph*/ + PIXEL_FORMAT_UNINITIALIZED, + PIXEL_FORMAT_INDEX8, + PIXEL_FORMAT_RGB565, + PIXEL_FORMAT_ARGB8888, + PIXEL_FORMAT_ARGB2101010, + PIXEL_FORMAT_ARGB2101010_XRBIAS, + PIXEL_FORMAT_FP16, + /*video*/ + PIXEL_FORMAT_420BPP12, + PIXEL_FORMAT_422BPP16, + PIXEL_FORMAT_444BPP16, + PIXEL_FORMAT_444BPP32, + /*end of pixel format definition*/ + PIXEL_FORMAT_INVALID, + + PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, + PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, + PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12, + PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_444BPP32, + PIXEL_FORMAT_UNKNOWN +}; + +enum plane_stereo_format { + PLANE_STEREO_FORMAT_NONE = 0, + PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, + PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, + PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, + PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, + PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, + PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 +}; + +/* 3D format for view, typically define how L/R eye surface is arranged within + * frames + */ +enum view_3d_format { + VIEW_3D_FORMAT_NONE = 0, + VIEW_3D_FORMAT_FRAME_SEQUENTIAL, + VIEW_3D_FORMAT_SIDE_BY_SIDE, + VIEW_3D_FORMAT_TOP_AND_BOTTOM, + VIEW_3D_FORMAT_COUNT, + VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL +}; + +enum dc_pixel_encoding { + PIXEL_ENCODING_UNDEFINED, + PIXEL_ENCODING_RGB, + PIXEL_ENCODING_YCBCR422, + PIXEL_ENCODING_YCBCR444, + PIXEL_ENCODING_YCBCR420, + PIXEL_ENCODING_COUNT +}; + +/* TODO: Find way to calculate number of bits + * Please increase if pixel_format enum increases + * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 + */ + +union large_integer { + struct { + uint32_t low_part; + int32_t high_part; + }; + + struct { + uint32_t low_part; + int32_t high_part; + } u; + + int64_t quad_part; +}; + +#define PHYSICAL_ADDRESS_LOC union large_integer + +enum dc_edid_connector_type { + EDID_CONNECTOR_UNKNOWN = 0, + EDID_CONNECTOR_ANALOG = 1, + EDID_CONNECTOR_DIGITAL = 10, + EDID_CONNECTOR_DVI = 11, + EDID_CONNECTOR_HDMIA = 12, + EDID_CONNECTOR_MDDI = 14, + EDID_CONNECTOR_DISPLAYPORT = 15 +}; + +enum dc_edid_status { + EDID_OK, + EDID_BAD_INPUT, + EDID_NO_RESPONSE, + EDID_BAD_CHECKSUM, +}; + +struct plane_colorimetry { + enum surface_color_space color_space; + bool limited_range; +}; + +/* audio capability from EDID*/ +struct dc_cea_audio_mode { + uint8_t format_code; /* ucData[0] [6:3]*/ + uint8_t channel_count; /* ucData[0] [2:0]*/ + uint8_t sample_rate; /* ucData[1]*/ + union { + uint8_t sample_size; /* for LPCM*/ + /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ + uint8_t max_bit_rate; + uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ + }; +}; + +struct dc_edid { + uint32_t length; + uint8_t raw_edid[MAX_EDID_BUFFER_SIZE]; +}; + +/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION + * is used. In this case we assume speaker location are: front left, front + * right and front center. */ +#define DEFAULT_SPEAKER_LOCATION 5 + +#define DC_MAX_AUDIO_DESC_COUNT 16 + +#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 + +struct dc_edid_caps { + /* sink identification */ + uint16_t manufacturer_id; + uint16_t product_id; + uint32_t serial_number; + uint8_t manufacture_week; + uint8_t manufacture_year; + uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; + + /* audio caps */ + uint8_t speaker_flags; + uint32_t audio_mode_count; + struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; + uint32_t audio_latency; + uint32_t video_latency; + + /*HDMI 2.0 caps*/ + uint8_t lte_340mcsc_scramble; +}; + +struct scaling_taps { + uint32_t v_taps; + uint32_t h_taps; + uint32_t v_taps_c; + uint32_t h_taps_c; +}; + +struct scaling_ratios { + struct fixed31_32 horz; + struct fixed31_32 vert; + struct fixed31_32 horz_c; + struct fixed31_32 vert_c; +}; + +struct rect { + uint32_t x; + uint32_t y; + uint32_t width; + uint32_t height; +}; + +struct view { + uint32_t width; + uint32_t height; +}; + +struct dc_resolution { + uint32_t width; + uint32_t height; +}; + + +struct dc_mode_flags { + /* note: part of refresh rate flag*/ + uint32_t INTERLACE :1; + /* native display timing*/ + uint32_t NATIVE :1; + /* preferred is the recommended mode, one per display */ + uint32_t PREFERRED :1; + /* true if this mode should use reduced blanking timings + *_not_ related to the Reduced Blanking adjustment*/ + uint32_t REDUCED_BLANKING :1; + /* note: part of refreshrate flag*/ + uint32_t VIDEO_OPTIMIZED_RATE :1; + /* should be reported to upper layers as mode_flags*/ + uint32_t PACKED_PIXEL_FORMAT :1; + /*< preferred view*/ + uint32_t PREFERRED_VIEW :1; + /* this timing should be used only in tiled mode*/ + uint32_t TILED_MODE :1; + uint32_t DSE_MODE :1; + /* Refresh rate divider when Miracast sink is using a + different rate than the output display device + Must be zero for wired displays and non-zero for + Miracast displays*/ + uint32_t MIRACAST_REFRESH_DIVIDER; +}; + +struct dc_crtc_timing_flags { + uint32_t INTERLACE :1; + uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, + it is positive polarity --reversed with dal1 or video bios define*/ + uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, + it is positive polarity --reversed with dal1 or video bios define*/ + + uint32_t HORZ_COUNT_BY_TWO:1; + + uint32_t EXCLUSIVE_3D :1; /* if this bit set, + timing can be driven in 3D format only + and there is no corresponding 2D timing*/ + uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity + (right eye = '1', left eye = '0') */ + uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled + when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ + uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, + because corresponding 2D timing also present in the list*/ + uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing + and we want to match priority of corresponding 3D timing*/ + uint32_t Y_ONLY :1; + + uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ + uint32_t DTD_COUNTER :5; /* values 1 to 16 */ + + /* HDMI 2.0 - Support scrambling for TMDS character + * rates less than or equal to 340Mcsc */ + uint32_t LTE_340MCSC_SCRAMBLE:1; + +}; + +enum dc_timing_standard { + TIMING_STANDARD_UNDEFINED, + TIMING_STANDARD_DMT, + TIMING_STANDARD_GTF, + TIMING_STANDARD_CVT, + TIMING_STANDARD_CVT_RB, + TIMING_STANDARD_CEA770, + TIMING_STANDARD_CEA861, + TIMING_STANDARD_HDMI, + TIMING_STANDARD_TV_NTSC, + TIMING_STANDARD_TV_NTSC_J, + TIMING_STANDARD_TV_PAL, + TIMING_STANDARD_TV_PAL_M, + TIMING_STANDARD_TV_PAL_CN, + TIMING_STANDARD_TV_SECAM, + TIMING_STANDARD_EXPLICIT, + /*!< For explicit timings from EDID, VBIOS, etc.*/ + TIMING_STANDARD_USER_OVERRIDE, + /*!< For mode timing override by user*/ + TIMING_STANDARD_MAX +}; + +enum dc_aspect_ratio { + ASPECT_RATIO_NO_DATA, + ASPECT_RATIO_4_3, + ASPECT_RATIO_16_9, + ASPECT_RATIO_64_27, + ASPECT_RATIO_256_135, + ASPECT_RATIO_FUTURE +}; + +enum dc_color_depth { + COLOR_DEPTH_UNDEFINED, + COLOR_DEPTH_666, + COLOR_DEPTH_888, + COLOR_DEPTH_101010, + COLOR_DEPTH_121212, + COLOR_DEPTH_141414, + COLOR_DEPTH_161616, + COLOR_DEPTH_COUNT +}; + +enum dc_timing_3d_format { + TIMING_3D_FORMAT_NONE, + TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ + TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ + TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ + /* for active DP-HDMI dongle*/ + TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ + TIMING_3D_FORMAT_HW_FRAME_PACKING, + TIMING_3D_FORMAT_SW_FRAME_PACKING, + TIMING_3D_FORMAT_ROW_INTERLEAVE, + TIMING_3D_FORMAT_COLUMN_INTERLEAVE, + TIMING_3D_FORMAT_PIXEL_INTERLEAVE, + TIMING_3D_FORMAT_SIDE_BY_SIDE, + TIMING_3D_FORMAT_TOP_AND_BOTTOM, + TIMING_3D_FORMAT_SBS_SW_PACKED, + /* Side-by-side, packed by application/driver into 2D frame*/ + TIMING_3D_FORMAT_TB_SW_PACKED, + /* Top-and-bottom, packed by application/driver into 2D frame*/ + + TIMING_3D_FORMAT_MAX, +}; + +enum dc_timing_source { + TIMING_SOURCE_UNDEFINED, + + /* explicitly specifed by user, most important*/ + TIMING_SOURCE_USER_FORCED, + TIMING_SOURCE_USER_OVERRIDE, + TIMING_SOURCE_CUSTOM, + TIMING_SOURCE_EXPLICIT, + + /* explicitly specified by the display device, more important*/ + TIMING_SOURCE_EDID_CEA_SVD_3D, + TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, + TIMING_SOURCE_EDID_CEA_SVD_420, + TIMING_SOURCE_EDID_DETAILED, + TIMING_SOURCE_EDID_ESTABLISHED, + TIMING_SOURCE_EDID_STANDARD, + TIMING_SOURCE_EDID_CEA_SVD, + TIMING_SOURCE_EDID_CVT_3BYTE, + TIMING_SOURCE_EDID_4BYTE, + TIMING_SOURCE_VBIOS, + TIMING_SOURCE_CV, + TIMING_SOURCE_TV, + TIMING_SOURCE_HDMI_VIC, + + /* implicitly specified by display device, still safe but less important*/ + TIMING_SOURCE_DEFAULT, + + /* only used for custom base modes */ + TIMING_SOURCE_CUSTOM_BASE, + + /* these timing might not work, least important*/ + TIMING_SOURCE_RANGELIMIT, + TIMING_SOURCE_OS_FORCED, + TIMING_SOURCE_IMPLICIT, + + /* only used by default mode list*/ + TIMING_SOURCE_BASICMODE, + + TIMING_SOURCE_COUNT +}; + +enum dc_timing_support_method { + TIMING_SUPPORT_METHOD_UNDEFINED, + TIMING_SUPPORT_METHOD_EXPLICIT, + TIMING_SUPPORT_METHOD_IMPLICIT, + TIMING_SUPPORT_METHOD_NATIVE +}; + +struct dc_mode_info { + uint32_t pixel_width; + uint32_t pixel_height; + uint32_t field_rate; + /* Vertical refresh rate for progressive modes. + * Field rate for interlaced modes.*/ + + enum dc_timing_standard timing_standard; + enum dc_timing_source timing_source; + struct dc_mode_flags flags; +}; + +/* TODO: assess necessity*/ +/*scanning type*/ +enum scanning_type { + SCANNING_TYPE_NODATA = 0, + SCANNING_TYPE_OVERSCAN, + SCANNING_TYPE_UNDERSCAN, + SCANNING_TYPE_FUTURE, + SCANNING_TYPE_UNDEFINED +}; + +struct dc_crtc_timing { + uint32_t h_total; + uint32_t h_border_left; + uint32_t h_addressable; + uint32_t h_border_right; + uint32_t h_front_porch; + uint32_t h_sync_width; + + uint32_t v_total; + uint32_t v_border_top; + uint32_t v_addressable; + uint32_t v_border_bottom; + uint32_t v_front_porch; + uint32_t v_sync_width; + + uint32_t pix_clk_khz; + + uint32_t vic; + uint32_t hdmi_vic; + enum dc_timing_standard timing_standard; + enum dc_timing_3d_format timing_3d_format; + enum dc_color_depth display_color_depth; + enum dc_pixel_encoding pixel_encoding; + enum dc_aspect_ratio aspect_ratio; + enum scanning_type scan_type; + + struct dc_crtc_timing_flags flags; +}; + +struct dc_mode_timing { + struct dc_mode_info mode_info; + struct dc_crtc_timing crtc_timing; +}; + +/* Rotation angle */ +enum dc_rotation_angle { + ROTATION_ANGLE_0 = 0, + ROTATION_ANGLE_90, + ROTATION_ANGLE_180, + ROTATION_ANGLE_270, + ROTATION_ANGLE_COUNT +}; + +struct dc_cursor_position { + uint32_t x; + uint32_t y; + + uint32_t x_origin; + uint32_t y_origin; + + /* + * This parameter indicates whether HW cursor should be enabled + */ + bool enable; + + /* + * This parameter indicates whether cursor hot spot should be + * programmed + */ + bool hot_spot_enable; +}; + +/* This enum is for programming CURSOR_MODE register field. */ +/* What this register should be programmed to depends on */ +/* OS requested cursor shape flags */ +/* and what we stored in the cursor surface. */ +enum dc_cursor_color_format { + CURSOR_MODE_MONO, + CURSOR_MODE_COLOR_1BIT_AND, + CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, + CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA +}; + +union dc_cursor_attribute_flags { + struct { + uint32_t ENABLE_MAGNIFICATION:1; + uint32_t INVERSE_TRANSPARENT_CLAMPING:1; + uint32_t HORIZONTAL_MIRROR:1; + uint32_t VERTICAL_MIRROR:1; + uint32_t RESERVED:28; + } bits; + uint32_t value; +}; + +/* This is all the parameters required by DAL in order to */ +/* update the cursor attributes, */ +/* including the new cursor image surface address, size, */ +/* hotspot location, color format, etc. */ +struct dc_cursor_attributes { + PHYSICAL_ADDRESS_LOC address; + + /* Width and height should correspond to cursor surface width x heigh */ + uint32_t width; + uint32_t height; + uint32_t x_hot; + uint32_t y_hot; + + enum dc_cursor_color_format color_format; + + /* In case we support HW Cursor rotation in the future */ + enum dc_rotation_angle rotation_angle; + + union dc_cursor_attribute_flags attribute_flags; + +}; + + +enum dc_plane_addr_type { + PLN_ADDR_TYPE_GRAPHICS = 0, + PLN_ADDR_TYPE_GRPH_STEREO, + PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, +}; + +struct dc_plane_address { + enum dc_plane_addr_type type; + union { + struct{ + PHYSICAL_ADDRESS_LOC addr; + } grph; + + /*stereo*/ + struct { + PHYSICAL_ADDRESS_LOC left_addr; + PHYSICAL_ADDRESS_LOC right_addr; + } grph_stereo; + + /*video progressive*/ + struct { + PHYSICAL_ADDRESS_LOC chroma_addr; + PHYSICAL_ADDRESS_LOC luma_addr; + } video_progressive; + }; +}; + +enum dc_power_state { + DC_POWER_STATE_ON = 1, + DC_POWER_STATE_STANDBY, + DC_POWER_STATE_SUSPEND, + DC_POWER_STATE_OFF +}; + +/* DC PowerStates */ +enum dc_video_power_state { + DC_VIDEO_POWER_UNSPECIFIED = 0, + DC_VIDEO_POWER_ON = 1, + DC_VIDEO_POWER_STANDBY, + DC_VIDEO_POWER_SUSPEND, + DC_VIDEO_POWER_OFF, + DC_VIDEO_POWER_HIBERNATE, + DC_VIDEO_POWER_SHUTDOWN, + DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ + DC_VIDEO_POWER_AFTER_RESET, + DC_VIDEO_POWER_MAXIMUM +}; + +enum dc_acpi_cm_power_state { + DC_ACPI_CM_POWER_STATE_D0 = 1, + DC_ACPI_CM_POWER_STATE_D1 = 2, + DC_ACPI_CM_POWER_STATE_D2 = 4, + DC_ACPI_CM_POWER_STATE_D3 = 8 +}; + +struct view_port_alignment { + uint8_t x_width_size_alignment; + uint8_t y_height_size_alignment; + uint8_t x_start_alignment; + uint8_t y_start_alignment; +}; + +enum dc_connection_type { + dc_connection_none, + dc_connection_single, + dc_connection_mst_branch, + dc_connection_active_dongle +}; + +/* + * Gamma ramp representation in DC + * + * A gamma ramp is just a curve defined within the range of [min, max] with + * arbitrary precision. + * + * DM is responsible for providing DC with an interface to obtain any y value + * within that range with a selected precision. + * + * bit32 ------------------------------------------------- bit 0 + * [ padding ][ exponent bits ][ fraction bits ] + * + * DC specifies the input x value and precision to the callback function + * get_gamma_value as well as providing the context and DM returns the y + * value. + * + * If fraction_bits + exponent_bits exceed width of 32 bits, get_gamma_value + * returns 0. If x is outside the bounds of [min, max], get_gamma_value + * returns 0. + * + */ +/* TODO: Deprecated */ +enum { + RGB_256X3X16 = 256, + DX_GAMMA_RAMP_MAX = 1025 +}; + +enum gamma_ramp_type { + GAMMA_RAMP_UNINITIALIZED = 0, + GAMMA_RAMP_DEFAULT, + GAMMA_RAMP_RBG256X3X16, + GAMMA_RAMP_DXGI_1, +}; + +struct dxgi_rgb { + struct fixed32_32 red; + struct fixed32_32 green; + struct fixed32_32 blue; +}; + +struct gamma_ramp_dxgi_1 { + struct dxgi_rgb scale; + struct dxgi_rgb offset; + struct dxgi_rgb gamma_curve[DX_GAMMA_RAMP_MAX]; +}; + +struct gamma_ramp_rgb256x3x16 { + uint16_t red[RGB_256X3X16]; + uint16_t green[RGB_256X3X16]; + uint16_t blue[RGB_256X3X16]; +}; + +struct gamma_ramp { + enum gamma_ramp_type type; + union { + struct gamma_ramp_rgb256x3x16 gamma_ramp_rgb256x3x16; + struct gamma_ramp_dxgi_1 gamma_ramp_dxgi1; + }; + uint32_t size; +}; + + +struct dc_gamma_ramp { + uint32_t (*get_gamma_value) ( + void *context, + uint8_t exponent_bits, + uint8_t fraction_bits, + uint32_t x); + void *context; + uint32_t min; + uint32_t max; +}; + +struct dc_csc_adjustments { + struct fixed31_32 contrast; + struct fixed31_32 saturation; + struct fixed31_32 brightness; + struct fixed31_32 hue; +}; + + +enum { + MAX_LANES = 2, + MAX_COFUNC_PATH = 6, + LAYER_INDEX_PRIMARY = -1, +}; + +/* Scaling format */ +enum scaling_transformation { + SCALING_TRANSFORMATION_UNINITIALIZED, + SCALING_TRANSFORMATION_IDENTITY = 0x0001, + SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, + SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, + SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, + SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, + SCALING_TRANSFORMATION_INVALID = 0x80000000, + + /* Flag the first and last */ + SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, + SCALING_TRANSFORMATION_END = + SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE +}; + +struct view_stereo_3d_support { + enum view_3d_format format; + struct { + uint32_t CLONE_MODE:1; + uint32_t SCALING:1; + uint32_t SINGLE_FRAME_SW_PACKED:1; + } features; +}; + +enum tiling_mode { + TILING_MODE_INVALID, + TILING_MODE_LINEAR, + TILING_MODE_TILED, + TILING_MODE_COUNT +}; + +struct view_position { + uint32_t x; + uint32_t y; +}; + +struct render_mode { + struct view view; + enum pixel_format pixel_format; +}; + +struct pixel_format_support { + bool INDEX8 :1; + bool RGB565 :1; + bool ARGB8888 :1; + bool ARGB2101010 :1; + bool ARGB2101010_XRBIAS :1; + bool FP16 :1; +}; + +struct stereo_3d_view { + enum view_3d_format view_3d_format; + union { + uint32_t raw; + struct /*stereo_3d_view_flags*/ + { + bool SINGLE_FRAME_SW_PACKED :1; + bool EXCLUSIVE_3D :1; + } bits; + } flags; +}; + +/* TODO: These values come from hardware spec. We need to readdress this + * if they ever change. + */ +enum array_mode_values { + DC_ARRAY_UNDEFINED = 0, + DC_ARRAY_1D_TILED_THIN1 = 0x2, + DC_ARRAY_2D_TILED_THIN1 = 0x4, +}; + + +enum tile_mode_values { + DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +}; + +enum tile_split_values { + DC_DISPLAY_MICRO_TILING = 0x0, + DC_THIN_MICRO_TILING = 0x1, + DC_DEPTH_MICRO_TILING = 0x2, + DC_ROTATED_MICRO_TILING = 0x3, +}; + +struct dc_tiling_info { + + /* Specifies the number of memory banks for tiling + * purposes. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 2,4,8,16 + */ + unsigned int num_banks; + /* Specifies the number of tiles in the x direction + * to be incorporated into the same bank. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 1,2,4,8 + */ + unsigned int bank_width; + /* Specifies the number of tiles in the y direction to + * be incorporated into the same bank. + * Only applies to 2D and 3D tiling modes. + * POSSIBLE VALUES: 1,2,4,8 + */ + unsigned int bank_height; + /* Specifies the macro tile aspect ratio. Only applies + * to 2D and 3D tiling modes. + */ + unsigned int tile_aspect; + /* Specifies the number of bytes that will be stored + * contiguously for each tile. + * If the tile data requires more storage than this + * amount, it is split into multiple slices. + * This field must not be larger than + * GB_ADDR_CONFIG.DRAM_ROW_SIZE. + * Only applies to 2D and 3D tiling modes. + * For color render targets, TILE_SPLIT >= 256B. + */ + enum tile_split_values tile_split; + /* Specifies the addressing within a tile. + * 0x0 - DISPLAY_MICRO_TILING + * 0x1 - THIN_MICRO_TILING + * 0x2 - DEPTH_MICRO_TILING + * 0x3 - ROTATED_MICRO_TILING + */ + enum tile_mode_values tile_mode; + /* Specifies the number of pipes and how they are + * interleaved in the surface. + * Refer to memory addressing document for complete + * details and constraints. + */ + unsigned int pipe_config; + /* Specifies the tiling mode of the surface. + * THIN tiles use an 8x8x1 tile size. + * THICK tiles use an 8x8x4 tile size. + * 2D tiling modes rotate banks for successive Z slices + * 3D tiling modes rotate pipes and banks for Z slices + * Refer to memory addressing document for complete + * details and constraints. + */ + enum array_mode_values array_mode; +}; + +union plane_size { + /* Grph or Video will be selected + * based on format above: + * Use Video structure if + * format >= DalPixelFormat_VideoBegin + * else use Grph structure + */ + struct { + struct rect surface_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch + * is 32 pixel aligned. + */ + uint32_t surface_pitch; + } grph; + + struct { + struct rect luma_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch is + * 32 pixel aligned. + */ + uint32_t luma_pitch; + + struct rect chroma_size; + /* Graphic surface pitch in pixels. + * In LINEAR_GENERAL mode, pitch is + * 32 pixel aligned. + */ + uint32_t chroma_pitch; + } video; +}; + +#endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h new file mode 100644 index 000000000000..b6ce51080b86 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h @@ -0,0 +1,98 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * This file defines helper functions provided by the Display Manager to + * Display Core. + */ +#ifndef __DM_HELPERS__ +#define __DM_HELPERS__ + +#include "dc_types.h" +#include "dc.h" + +struct dp_mst_stream_allocation_table; + +enum dc_edid_status dm_helpers_parse_edid_caps( + struct dc_context *ctx, + const struct dc_edid *edid, + struct dc_edid_caps *edid_caps); + +/* + * Writes payload allocation table in immediate downstream device. + */ +bool dm_helpers_dp_mst_write_payload_allocation_table( + struct dc_context *ctx, + const struct dc_stream *stream, + struct dp_mst_stream_allocation_table *proposed_table, + bool enable); + +/* + * Polls for ACT (allocation change trigger) handled and + */ +bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( + struct dc_context *ctx, + const struct dc_stream *stream); +/* + * Sends ALLOCATE_PAYLOAD message. + */ +bool dm_helpers_dp_mst_send_payload_allocation( + struct dc_context *ctx, + const struct dc_stream *stream, + bool enable); + +void dm_helpers_dp_mst_handle_mst_hpd_rx_irq( + void *param); + +bool dm_helpers_dp_mst_start_top_mgr( + struct dc_context *ctx, + const struct dc_link *link, + bool boot); + +void dm_helpers_dp_mst_stop_top_mgr( + struct dc_context *ctx, + const struct dc_link *link); + +/** + * OS specific aux read callback. + */ +bool dm_helper_dp_read_dpcd( + struct dc_context *ctx, + const struct dc_link *link, + uint32_t address, + uint8_t *data, + uint32_t size); + +/** + * OS specific aux write callback. + */ +bool dm_helper_dp_write_dpcd( + struct dc_context *ctx, + const struct dc_link *link, + uint32_t address, + const uint8_t *data, + uint32_t size); + +#endif /* __DM_HELPERS__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h new file mode 100644 index 000000000000..206c0b7df7c6 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h @@ -0,0 +1,485 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * This file defines external dependencies of Display Core. + */ + +#ifndef __DM_SERVICES_H__ + +#define __DM_SERVICES_H__ + +/* TODO: remove when DC is complete. */ +#include "dm_services_types.h" +#include "logger_interface.h" +#include "include/dal_types.h" +#include "irq_types.h" +#include "link_service_types.h" + +#undef DEPRECATED + +/* if the pointer is not NULL, the allocated memory is zeroed */ +void *dm_alloc(struct dc_context *ctx, uint32_t size); + +/* reallocate memory. The contents will remain unchanged.*/ +void *dm_realloc(struct dc_context *ctx, const void *ptr, uint32_t size); + +void dm_free(struct dc_context *ctx, void *p); + +void dm_memset(void *p, int32_t c, uint32_t count); + +void dm_memmove(void *dst, const void *src, uint32_t size); + +int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count); + +int32_t dm_strncmp(const int8_t *p1, const int8_t *p2, uint32_t count); + +irq_handler_idx dm_register_interrupt( + struct dc_context *ctx, + struct dc_interrupt_params *int_params, + interrupt_handler ih, + void *handler_args); + +void dm_unregister_interrupt( + struct dc_context *ctx, + enum dc_irq_source irq_source, + irq_handler_idx handler_idx); + +/* + * + * GPU registers access + * + */ + +#define dm_read_reg(ctx, address) \ + dm_read_reg_func(ctx, address, __func__) + +static inline uint32_t dm_read_reg_func( + const struct dc_context *ctx, + uint32_t address, + const char *func_name) +{ + uint32_t value = cgs_read_register(ctx->cgs_device, address); + +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s DC_READ_REG: 0x%x 0x%x\n", func_name, address, value); + } +#endif + return value; +} + +#define dm_write_reg(ctx, address, value) \ + dm_write_reg_func(ctx, address, value, __func__) + +static inline void dm_write_reg_func( + const struct dc_context *ctx, + uint32_t address, + uint32_t value, + const char *func_name) +{ +#if defined(__DAL_REGISTER_LOGGER__) + if (true == dal_reg_logger_should_dump_register()) { + dal_reg_logger_rw_count_increment(); + DRM_INFO("%s DC_WRITE_REG: 0x%x 0x%x\n", func_name, address, value); + } +#endif + cgs_write_register(ctx->cgs_device, address, value); +} + +static inline uint32_t dm_read_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index) +{ + return cgs_read_ind_register(ctx->cgs_device, addr_space, index); +} + +static inline void dm_write_index_reg( + const struct dc_context *ctx, + enum cgs_ind_reg addr_space, + uint32_t index, + uint32_t value) +{ + cgs_write_ind_register(ctx->cgs_device, addr_space, index, value); +} + +static inline uint32_t get_reg_field_value_ex( + uint32_t reg_value, + uint32_t mask, + uint8_t shift) +{ + return (mask & reg_value) >> shift; +} + +#define get_reg_field_value(reg_value, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +static inline uint32_t set_reg_field_value_ex( + uint32_t reg_value, + uint32_t value, + uint32_t mask, + uint8_t shift) +{ + return (reg_value & ~mask) | (mask & (value << shift)); +} + +#define set_reg_field_value(reg_value, value, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT) + +/* + * atombios services + */ + +bool dm_exec_bios_cmd_table( + struct dc_context *ctx, + uint32_t index, + void *params); + +#ifdef BUILD_DAL_TEST +uint32_t dm_bios_cmd_table_para_revision( +struct dc_context *ctx, + uint32_t index); + +bool dm_bios_cmd_table_revision( + struct dc_context *ctx, + uint32_t index, + uint8_t *frev, + uint8_t *crev); +#endif + +#ifndef BUILD_DAL_TEST +static inline uint32_t dm_bios_cmd_table_para_revision( + struct dc_context *ctx, + uint32_t index) +{ + uint8_t frev; + uint8_t crev; + + if (cgs_atom_get_cmd_table_revs( + ctx->cgs_device, + index, + &frev, + &crev) != 0) + return 0; + + return crev; +} +#else +uint32_t dm_bios_cmd_table_para_revision( + struct dc_context *ctx, + uint32_t index); +#endif + +/************************************** + * Power Play (PP) interfaces + **************************************/ + +enum dal_to_power_clocks_state { + PP_CLOCKS_STATE_INVALID, + PP_CLOCKS_STATE_ULTRA_LOW, + PP_CLOCKS_STATE_LOW, + PP_CLOCKS_STATE_NOMINAL, + PP_CLOCKS_STATE_PERFORMANCE +}; + +/* clocks in khz */ +struct dal_to_power_info { + enum dal_to_power_clocks_state required_clock; + uint32_t min_sclk; + uint32_t min_mclk; + uint32_t min_deep_sleep_sclk; +}; + +/* clocks in khz */ +struct power_to_dal_info { + uint32_t min_sclk; + uint32_t max_sclk; + uint32_t min_mclk; + uint32_t max_mclk; +}; + +/* clocks in khz */ +struct dal_system_clock_range { + uint32_t min_sclk; + uint32_t max_sclk; + + uint32_t min_mclk; + uint32_t max_mclk; + + uint32_t min_dclk; + uint32_t max_dclk; + + /* Wireless Display */ + uint32_t min_eclk; + uint32_t max_eclk; +}; + +/* clocks in khz */ +struct dal_to_power_dclk { + uint32_t optimal; /* input: best optimizes for stutter efficiency */ + uint32_t minimal; /* input: the lowest clk that DAL can support */ + uint32_t established; /* output: the actually set one */ +}; + +/* DAL calls this function to notify PP about clocks it needs for the Mode Set. + * This is done *before* it changes DCE clock. + * + * If required clock is higher than current, then PP will increase the voltage. + * + * If required clock is lower than current, then PP will defer reduction of + * voltage until the call to dc_service_pp_post_dce_clock_change(). + * + * \input - Contains clocks needed for Mode Set. + * + * \output - Contains clocks adjusted by PP which DAL should use for Mode Set. + * Valid only if function returns zero. + * + * \returns true - call is successful + * false - call failed + */ +bool dm_pp_pre_dce_clock_change( + struct dc_context *ctx, + struct dal_to_power_info *input, + struct power_to_dal_info *output); + +struct dc_pp_single_disp_config { + enum signal_type signal; + uint8_t transmitter; + uint8_t ddi_channel_mapping; + uint8_t pipe_idx; + uint32_t src_height; + uint32_t src_width; + uint32_t v_refresh; + uint32_t sym_clock; /* HDMI only */ + struct link_settings link_settings; /* DP only */ +}; + +struct dc_pp_display_configuration { + bool nb_pstate_switch_disable;/* controls NB PState switch */ + bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ + bool cpu_pstate_disable; + uint32_t cpu_pstate_separation_time; + + uint32_t min_memory_clock_khz; + uint32_t min_engine_clock_khz; + uint32_t min_engine_clock_deep_sleep_khz; + + uint32_t avail_mclk_switch_time_us; + uint32_t avail_mclk_switch_time_in_disp_active_us; + + uint32_t disp_clk_khz; + + bool all_displays_in_sync; + + uint8_t display_count; + struct dc_pp_single_disp_config disp_configs[3]; + + /*Controller Index of primary display - used in MCLK SMC switching hang + * SW Workaround*/ + uint8_t crtc_index; + /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ + uint32_t line_time_in_us; +}; + +enum dc_pp_clocks_state { + DC_PP_CLOCKS_STATE_INVALID = 0, + DC_PP_CLOCKS_STATE_ULTRA_LOW, + DC_PP_CLOCKS_STATE_LOW, + DC_PP_CLOCKS_STATE_NOMINAL, + DC_PP_CLOCKS_STATE_PERFORMANCE, + + /* Starting from DCE11, Max 8 levels of DPM state supported. */ + DC_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DC_PP_CLOCKS_STATE_INVALID, + DC_PP_CLOCKS_DPM_STATE_LEVEL_0 = DC_PP_CLOCKS_STATE_ULTRA_LOW, + DC_PP_CLOCKS_DPM_STATE_LEVEL_1 = DC_PP_CLOCKS_STATE_LOW, + DC_PP_CLOCKS_DPM_STATE_LEVEL_2 = DC_PP_CLOCKS_STATE_NOMINAL, + /* to be backward compatible */ + DC_PP_CLOCKS_DPM_STATE_LEVEL_3 = DC_PP_CLOCKS_STATE_PERFORMANCE, + DC_PP_CLOCKS_DPM_STATE_LEVEL_4 = DC_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1, + DC_PP_CLOCKS_DPM_STATE_LEVEL_5 = DC_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1, + DC_PP_CLOCKS_DPM_STATE_LEVEL_6 = DC_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1, + DC_PP_CLOCKS_DPM_STATE_LEVEL_7 = DC_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1, +}; + +struct dc_pp_static_clock_info { + uint32_t max_sclk_khz; + uint32_t max_mclk_khz; + + /* max possible display block clocks state */ + enum dc_pp_clocks_state max_clocks_state; +}; + +/* The returned clocks range are 'static' system clocks which will be used for + * mode validation purposes. + * + * \returns true - call is successful + * false - call failed + */ +bool dc_service_get_system_clocks_range( + const struct dc_context *ctx, + struct dal_system_clock_range *sys_clks); + +enum dc_pp_clock_type { + DC_PP_CLOCK_TYPE_DISPLAY_CLK = 1, + DC_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */ + DC_PP_CLOCK_TYPE_MEMORY_CLK +}; + +#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ + (clk_type) == DC_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \ + (clk_type) == DC_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \ + (clk_type) == DC_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid" + +#define DC_PP_MAX_CLOCK_LEVELS 8 + +struct dc_pp_clock_levels { + uint32_t num_levels; + uint32_t clocks_in_khz[DC_PP_MAX_CLOCK_LEVELS]; +}; + +/* Gets valid clocks levels from pplib + * + * input: clk_type - display clk / sclk / mem clk + * + * output: array of valid clock levels for given type in ascending order, + * with invalid levels filtered out + * + */ +bool dm_pp_get_clock_levels_by_type( + const struct dc_context *ctx, + enum dc_pp_clock_type clk_type, + struct dc_pp_clock_levels *clk_level_info); + + +bool dm_pp_apply_safe_state( + const struct dc_context *ctx); + +/* DAL calls this function to notify PP about completion of Mode Set. + * For PP it means that current DCE clocks are those which were returned + * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. + * + * If the clocks are higher than before, then PP does nothing. + * + * If the clocks are lower than before, then PP reduces the voltage. + * + * \returns true - call is successful + * false - call failed + */ +bool dm_pp_apply_display_requirements( + const struct dc_context *ctx, + const struct dc_pp_display_configuration *pp_display_cfg); + + +/****** end of PP interfaces ******/ + +void dm_sleep_in_milliseconds(struct dc_context *ctx, uint32_t milliseconds); + +void dm_delay_in_microseconds(struct dc_context *ctx, uint32_t microseconds); + +enum platform_method { + PM_GET_AVAILABLE_METHODS = 1 << 0, + PM_GET_LID_STATE = 1 << 1, + PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2 +}; + +struct platform_info_params { + enum platform_method method; + void *data; +}; + +struct platform_info_brightness_caps { + uint8_t ac_level_percentage; + uint8_t dc_level_percentage; +}; + +struct platform_info_ext_brightness_caps { + struct platform_info_brightness_caps basic_caps; + struct data_point { + uint8_t luminance; + uint8_t signal_level; + } data_points[99]; + + uint8_t data_points_num; + uint8_t min_input_signal; + uint8_t max_input_signal; +}; + +bool dm_get_platform_info( + struct dc_context *ctx, + struct platform_info_params *params); + +/* + * + * print-out services + * + */ +#define dm_log_to_buffer(buffer, size, fmt, args)\ + vsnprintf(buffer, size, fmt, args) + +long dm_get_pid(void); +long dm_get_tgid(void); + +/* + * + * general debug capabilities + * + */ +#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER) + +#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) +#define ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + kgdb_breakpoint(); \ + } \ +} while (0) +#else +#define ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + ; \ + } \ +} while (0) +#endif + +#if defined(CONFIG_DEBUG_KERNEL_DAL) +#define ASSERT(expr) ASSERT_CRITICAL(expr) + +#else +#define ASSERT(expr) WARN_ON(!(expr)) +#endif + +#define BREAK_TO_DEBUGGER() ASSERT(0) + +#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */ + +#endif /* __DM_SERVICES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h new file mode 100644 index 000000000000..bc458aa41a5d --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h @@ -0,0 +1,167 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DM_SERVICES_TYPES_H__ +#define __DM_SERVICES_TYPES_H__ + +#define INVALID_DISPLAY_INDEX 0xffffffff + +#if defined __KERNEL__ + +#include <asm/byteorder.h> +#include <linux/types.h> +#include <drm/drmP.h> + +#include "cgs_linux.h" + +#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU) +#define BIGENDIAN_CPU +#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU) +#define LITTLEENDIAN_CPU +#endif + +#undef READ +#undef WRITE +#undef FRAME_SIZE + +#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__) + +#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__) + +#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__) + +#define dm_vlog(fmt, args) vprintk(fmt, args) + +#define dm_min(x, y) min(x, y) +#define dm_max(x, y) max(x, y) + +#elif defined BUILD_DAL_TEST + +#include <inttypes.h> +#include <stdlib.h> +#include <string.h> + +#include <stdio.h> + +#include <stdarg.h> + +#include "cgs_linux.h" + +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define LLONG_MAX ((long long)(~0ULL>>1)) +#define LLONG_MIN (-LLONG_MAX - 1) +#define UINT_MAX (~0U) + +typedef _Bool bool; +enum { false, true }; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#define LITTLEENDIAN_CPU 1 + +#include <test_context.h> + +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#define container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - offsetof(type, member))) + +#define dal_test_not_implemented() \ + printf("[DAL_TEST_NOT_IMPL]:%s\n", __func__) + +#define dm_output_to_console(fmt, ...) do { \ + printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \ + while (false) + +#define dm_error(fmt, ...) printf("[DAL_ERROR]" fmt, ##__VA_ARGS__) + +#define dm_output_to_console(fmt, ...) do { \ + printf("[DAL_LOG]" fmt, ##__VA_ARGS__); } \ + while (false) + + +#define dm_debug(fmt, ...) printf("[DAL_DBG]" fmt, ##__VA_ARGS__) + +#define dm_vlog(fmt, args) vprintf(fmt, args) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +#define dm_min(x, y) ({\ + typeof(x) _min1 = (x);\ + typeof(y) _min2 = (y);\ + (void) (&_min1 == &_min2);\ + _min1 < _min2 ? _min1 : _min2; }) + +#define dm_max(x, y) ({\ + typeof(x) _max1 = (x);\ + typeof(y) _max2 = (y);\ + (void) (&_max1 == &_max2);\ + _max1 > _max2 ? _max1 : _max2; }) + +/* division functions */ + +static inline int64_t div64_s64(int64_t x, int64_t y) +{ + return x / y; +} + +static inline uint64_t div64_u64(uint64_t x, uint64_t y) +{ + return x / y; +} + +static inline uint64_t div_u64(uint64_t x, uint32_t y) +{ + return x / y; +} + +static inline uint64_t div64_u64_rem(uint64_t x, uint64_t y, uint64_t *rem) +{ + if (rem) + *rem = x % y; + return x / y; +} + +static inline uint64_t div_u64_rem(uint64_t x, uint32_t y, uint32_t *rem) +{ + if (rem) + *rem = x % y; + return x / y; +} + +#define cpu_to_le16(do_nothing) do_nothing + +#define le16_to_cpu(do_nothing) do_nothing + +#define cpu_to_le32(do_nothing) do_nothing + +#define le32_to_cpu(do_nothing) do_nothing + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h new file mode 100644 index 000000000000..0d228ed0455c --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h @@ -0,0 +1,510 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * Bandwidth and Watermark calculations interface. + * (Refer to "DCE11_mode_support.xlsm" from Perforce.) + */ +#ifndef __BANDWIDTH_CALCS_H__ +#define __BANDWIDTH_CALCS_H__ + +#include "bw_fixed.h" +/******************************************************************************* + * There are three types of input into Calculations: + * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP + * 2. board-level values - these are generally coming from VBIOS parser + * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. + ******************************************************************************/ +enum bw_defines { + /*Common*/ + bw_def_no = 0, + bw_def_none = 0, + bw_def_yes = 1, + bw_def_ok = 1, + bw_def_high = 2, + bw_def_mid = 1, + bw_def_low = 0, + + /*Internal*/ + bw_defs_start = 255, + bw_def_underlay422, + bw_def_underlay420_luma, + bw_def_underlay420_chroma, + bw_def_underlay444, + bw_def_graphics, + bw_def_display_write_back420_luma, + bw_def_display_write_back420_chroma, + bw_def_portrait, + bw_def_hsr_mtn_4, + bw_def_hsr_mtn_h_taps, + bw_def_ceiling__h_taps_div_4___meq_hsr, + bw_def_invalid_linear_or_stereo_mode, + bw_def_invalid_rotation_or_bpp_or_stereo, + bw_def_vsr_mtn_v_taps, + bw_def_vsr_mtn_4, + bw_def_auto, + bw_def_manual, + bw_def_exceeded_allowed_maximum_sclk, + bw_def_exceeded_allowed_page_close_open, + bw_def_exceeded_allowed_outstanding_pte_req_queue_size, + bw_def_exceeded_allowed_maximum_bw, + bw_def_high_no_nbp_state_change, + bw_def_landscape, + + /*Panning and bezel*/ + bw_def_any_lines, + + /*Underlay mode*/ + bw_def_underlay_only, + bw_def_blended, + bw_def_blend, + + /*Stereo mode*/ + bw_def_mono, + bw_def_side_by_side, + bw_def_top_bottom, + + /*Underlay surface type*/ + bw_def_420, + bw_def_422, + bw_def_444, + + /*Tiling mode*/ + bw_def_linear, + bw_def_tiled, + + bw_def_notok = -1, + bw_def_na = -1 +}; + +struct bw_calcs_dceip { + struct bw_fixed dmif_request_buffer_size; + struct bw_fixed de_tiling_buffer; + bool dcfclk_request_generation; + uint32_t lines_interleaved_into_lb; + uint32_t chunk_width; + uint32_t number_of_graphics_pipes; + uint32_t number_of_underlay_pipes; + bool display_write_back_supported; + bool argb_compression_support; + struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; + struct bw_fixed alpha_vscaler_efficiency; + uint32_t max_dmif_buffer_allocated; + uint32_t graphics_dmif_size; + uint32_t underlay_luma_dmif_size; + uint32_t underlay_chroma_dmif_size; + bool pre_downscaler_enabled; + bool underlay_downscale_prefetch_enabled; + struct bw_fixed lb_write_pixels_per_dispclk; + struct bw_fixed lb_size_per_component444; + bool graphics_lb_nodownscaling_multi_line_prefetching; + struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; + struct bw_fixed underlay420_luma_lb_size_per_component; + struct bw_fixed underlay420_chroma_lb_size_per_component; + struct bw_fixed underlay422_lb_size_per_component; + struct bw_fixed cursor_chunk_width; + struct bw_fixed cursor_dcp_buffer_lines; + struct bw_fixed cursor_memory_interface_buffer_pixels; + struct bw_fixed underlay_maximum_width_efficient_for_tiling; + struct bw_fixed underlay_maximum_height_efficient_for_tiling; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; + struct bw_fixed minimum_outstanding_pte_request_limit; + struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; + bool limit_excessive_outstanding_dmif_requests; + struct bw_fixed linear_mode_line_request_alternation_slice; + uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; + uint32_t display_write_back420_luma_mcifwr_buffer_size; + uint32_t display_write_back420_chroma_mcifwr_buffer_size; + struct bw_fixed request_efficiency; + struct bw_fixed dispclk_per_request; + struct bw_fixed dispclk_ramping_factor; + struct bw_fixed display_pipe_throughput_factor; + uint32_t scatter_gather_pte_request_rows_in_tiling_mode; + struct bw_fixed mcifwr_all_surfaces_burst_time; /* 0 todo: this is a bug*/ +}; + +struct bw_calcs_vbios { + uint32_t dram_channel_width_in_bits; + uint32_t number_of_dram_channels; + uint32_t number_of_dram_banks; + struct bw_fixed high_yclk; /*MHz*/ + struct bw_fixed mid_yclk; /*MHz*/ + struct bw_fixed low_yclk; /*MHz*/ + struct bw_fixed low_sclk; /*MHz*/ + struct bw_fixed mid_sclk; /*MHz*/ + struct bw_fixed high_sclk; /*MHz*/ + struct bw_fixed low_voltage_max_dispclk; /*MHz*/ + struct bw_fixed mid_voltage_max_dispclk; /*MHz*/ + struct bw_fixed high_voltage_max_dispclk; /*MHz*/ + struct bw_fixed data_return_bus_width; + struct bw_fixed trc; + struct bw_fixed dmifmc_urgent_latency; + struct bw_fixed stutter_self_refresh_exit_latency; + struct bw_fixed nbp_state_change_latency; + struct bw_fixed mcifwrmc_urgent_latency; + bool scatter_gather_enable; + struct bw_fixed down_spread_percentage; + uint32_t cursor_width; + uint32_t average_compression_rate; + uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; + struct bw_fixed blackout_duration; + struct bw_fixed maximum_blackout_recovery_time; +}; + +struct bw_calcs_mode_data_internal { + /* data for all displays */ + uint32_t number_of_displays; + uint32_t graphics_rotation_angle; + uint32_t underlay_rotation_angle; + enum bw_defines display_synchronization_enabled; + enum bw_defines underlay_surface_type; + enum bw_defines panning_and_bezel_adjustment; + enum bw_defines graphics_tiling_mode; + bool graphics_interlace_mode; + uint32_t graphics_bytes_per_pixel; + uint32_t graphics_htaps; + uint32_t graphics_vtaps; + uint32_t graphics_lb_bpc; + uint32_t underlay_lb_bpc; + enum bw_defines underlay_tiling_mode; + uint32_t underlay_htaps; + uint32_t underlay_vtaps; + uint32_t underlay_src_width; + uint32_t underlay_src_height; + uint32_t underlay_pitch_in_pixels; + enum bw_defines underlay_stereo_mode; + bool d0_fbc_enable; + bool d0_lpt_enable; + uint32_t d0_htotal; + struct bw_fixed d0_pixel_rate; + uint32_t d0_graphics_src_width; + uint32_t d0_graphics_src_height; + struct bw_fixed d0_graphics_scale_ratio; + enum bw_defines d0_graphics_stereo_mode; + enum bw_defines d0_underlay_mode; + struct bw_fixed d0_underlay_scale_ratio; + uint32_t d1_htotal; + struct bw_fixed d1_pixel_rate; + uint32_t d1_graphics_src_width; + uint32_t d1_graphics_src_height; + struct bw_fixed d1_graphics_scale_ratio; + enum bw_defines d1_graphics_stereo_mode; + bool d1_display_write_back_dwb_enable; + enum bw_defines d1_underlay_mode; + struct bw_fixed d1_underlay_scale_ratio; + uint32_t d2_htotal; + struct bw_fixed d2_pixel_rate; + uint32_t d2_graphics_src_width; + uint32_t d2_graphics_src_height; + struct bw_fixed d2_graphics_scale_ratio; + enum bw_defines d2_graphics_stereo_mode; +}; + + +struct bw_calcs_input_single_display { + uint32_t graphics_rotation_angle; + uint32_t underlay_rotation_angle; + enum bw_defines underlay_surface_type; + enum bw_defines panning_and_bezel_adjustment; + uint32_t graphics_bytes_per_pixel; + bool graphics_interlace_mode; + enum bw_defines graphics_tiling_mode; + uint32_t graphics_h_taps; + uint32_t graphics_v_taps; + uint32_t graphics_lb_bpc; + uint32_t underlay_lb_bpc; + enum bw_defines underlay_tiling_mode; + uint32_t underlay_h_taps; + uint32_t underlay_v_taps; + uint32_t underlay_src_width; + uint32_t underlay_src_height; + uint32_t underlay_pitch_in_pixels; + enum bw_defines underlay_stereo_mode; + bool fbc_enable; + bool lpt_enable; + uint32_t h_total; + struct bw_fixed pixel_rate; + uint32_t graphics_src_width; + uint32_t graphics_src_height; + struct bw_fixed graphics_scale_ratio; + enum bw_defines graphics_stereo_mode; + enum bw_defines underlay_mode; +}; + +#define BW_CALCS_MAX_NUM_DISPLAYS 3 + +struct bw_calcs_mode_data { + /* data for all displays */ + uint8_t number_of_displays; + bool display_synchronization_enabled; + + struct bw_calcs_input_single_display + displays_data[BW_CALCS_MAX_NUM_DISPLAYS]; +}; + +/******************************************************************************* + * Output data structure(s). + ******************************************************************************/ +#define maximum_number_of_surfaces 12 +/*Units : MHz, us */ +struct bw_calcs_results { + bool cpup_state_change_enable; + bool cpuc_state_change_enable; + bool nbp_state_change_enable; + bool stutter_mode_enable; + uint32_t y_clk_level; + uint32_t sclk_level; + uint32_t number_of_underlay_surfaces; + struct bw_fixed src_width_after_surface_type; + struct bw_fixed src_height_after_surface_type; + struct bw_fixed hsr_after_surface_type; + struct bw_fixed vsr_after_surface_type; + struct bw_fixed src_width_after_rotation; + struct bw_fixed src_height_after_rotation; + struct bw_fixed hsr_after_rotation; + struct bw_fixed vsr_after_rotation; + struct bw_fixed source_height_pixels; + struct bw_fixed hsr_after_stereo; + struct bw_fixed vsr_after_stereo; + struct bw_fixed source_width_in_lb; + struct bw_fixed lb_line_pitch; + struct bw_fixed underlay_maximum_source_efficient_for_tiling; + struct bw_fixed num_lines_at_frame_start; + struct bw_fixed min_dmif_size_in_time; + struct bw_fixed min_mcifwr_size_in_time; + struct bw_fixed total_requests_for_dmif_size; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; + struct bw_fixed useful_pte_per_pte_request; + struct bw_fixed scatter_gather_pte_request_rows; + struct bw_fixed scatter_gather_row_height; + struct bw_fixed scatter_gather_pte_requests_in_vblank; + struct bw_fixed inefficient_linear_pitch_in_bytes; + struct bw_fixed inefficient_underlay_pitch_in_pixels; + struct bw_fixed minimum_underlay_pitch_padding_recommended_for_efficiency; + struct bw_fixed cursor_total_data; + struct bw_fixed cursor_total_request_groups; + struct bw_fixed scatter_gather_total_pte_requests; + struct bw_fixed scatter_gather_total_pte_request_groups; + struct bw_fixed tile_width_in_pixels; + struct bw_fixed dmif_total_number_of_data_request_page_close_open; + struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; + struct bw_fixed bytes_per_page_close_open; + struct bw_fixed mcifwr_total_page_close_open_time; + struct bw_fixed total_requests_for_adjusted_dmif_size; + struct bw_fixed total_dmifmc_urgent_trips; + struct bw_fixed total_dmifmc_urgent_latency; + struct bw_fixed total_display_reads_required_data; + struct bw_fixed total_display_reads_required_dram_access_data; + struct bw_fixed total_display_writes_required_data; + struct bw_fixed total_display_writes_required_dram_access_data; + struct bw_fixed display_reads_required_data; + struct bw_fixed display_reads_required_dram_access_data; + struct bw_fixed dmif_total_page_close_open_time; + struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; + struct bw_fixed min_read_buffer_size_in_time; + struct bw_fixed display_reads_time_for_data_transfer; + struct bw_fixed display_writes_time_for_data_transfer; + struct bw_fixed dmif_required_dram_bandwidth; + struct bw_fixed mcifwr_required_dram_bandwidth; + struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; + struct bw_fixed required_mcifmcwr_urgent_latency; + struct bw_fixed required_dram_bandwidth_gbyte_per_second; + struct bw_fixed dram_bandwidth; + struct bw_fixed dmif_required_sclk; + struct bw_fixed mcifwr_required_sclk; + struct bw_fixed required_sclk; + struct bw_fixed downspread_factor; + struct bw_fixed v_scaler_efficiency; + struct bw_fixed scaler_limits_factor; + struct bw_fixed display_pipe_pixel_throughput; + struct bw_fixed total_dispclk_required_with_ramping; + struct bw_fixed total_dispclk_required_without_ramping; + struct bw_fixed total_read_request_bandwidth; + struct bw_fixed total_write_request_bandwidth; + struct bw_fixed dispclk_required_for_total_read_request_bandwidth; + struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; + struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; + struct bw_fixed dispclk; + struct bw_fixed blackout_recovery_time; + struct bw_fixed min_pixels_per_data_fifo_entry; + struct bw_fixed sclk_deep_sleep; + struct bw_fixed chunk_request_time; + struct bw_fixed cursor_request_time; + struct bw_fixed line_source_pixels_transfer_time; + struct bw_fixed dmifdram_access_efficiency; + struct bw_fixed mcifwrdram_access_efficiency; + struct bw_fixed total_average_bandwidth_no_compression; + struct bw_fixed total_average_bandwidth; + struct bw_fixed total_stutter_cycle_duration; + struct bw_fixed stutter_burst_time; + struct bw_fixed time_in_self_refresh; + struct bw_fixed stutter_efficiency; + struct bw_fixed worst_number_of_trips_to_memory; + struct bw_fixed immediate_flip_time; + struct bw_fixed latency_for_non_dmif_clients; + struct bw_fixed latency_for_non_mcifwr_clients; + struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; + struct bw_fixed nbp_state_dram_speed_change_margin; + struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; + bool displays_match_flag[maximum_number_of_surfaces]; + bool use_alpha[maximum_number_of_surfaces]; + bool orthogonal_rotation[maximum_number_of_surfaces]; + bool enable[maximum_number_of_surfaces]; + bool access_one_channel_only[maximum_number_of_surfaces]; + bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; + bool interlace_mode[maximum_number_of_surfaces]; + bool display_pstate_change_enable[maximum_number_of_surfaces]; + struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; + struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; + uint32_t bytes_per_pixel[maximum_number_of_surfaces]; + struct bw_fixed h_total[maximum_number_of_surfaces]; + struct bw_fixed pixel_rate[maximum_number_of_surfaces]; + struct bw_fixed src_width[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; + struct bw_fixed src_height[maximum_number_of_surfaces]; + struct bw_fixed scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed h_taps[maximum_number_of_surfaces]; + struct bw_fixed v_taps[maximum_number_of_surfaces]; + struct bw_fixed rotation_angle[maximum_number_of_surfaces]; + uint32_t lb_bpc[maximum_number_of_surfaces]; + struct bw_fixed compression_rate[maximum_number_of_surfaces]; + struct bw_fixed hsr[maximum_number_of_surfaces]; + struct bw_fixed vsr[maximum_number_of_surfaces]; + struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; + struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; + struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; + struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; + struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; + struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; + struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; + struct bw_fixed v_filter_init[maximum_number_of_surfaces]; + struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; + struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; + struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; + struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; + struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; + struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; + bool line_buffer_prefetch[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed active_time[maximum_number_of_surfaces]; + struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; + struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed dmif_burst_time[3][3]; + struct bw_fixed mcifwr_burst_time[3][3]; + struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][3]; + struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][3]; + struct bw_fixed min_dram_speed_change_margin[3][3]; + struct bw_fixed dram_speed_change_margin[3][3]; + struct bw_fixed dispclk_required_for_dram_speed_change[3][3]; + struct bw_fixed blackout_duration_margin[3][3]; + struct bw_fixed dispclk_required_for_blackout_duration[3][3]; + struct bw_fixed dispclk_required_for_blackout_recovery[3][3]; + struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; +}; + +struct bw_watermarks { + uint32_t a_mark; + uint32_t b_mark; +}; + +struct bw_calcs_output { + bool cpuc_state_change_enable; + bool cpup_state_change_enable; + bool stutter_mode_enable; + bool nbp_state_change_enable; + bool all_displays_in_sync; + struct bw_watermarks urgent_wm_ns[4]; + struct bw_watermarks stutter_exit_wm_ns[4]; + struct bw_watermarks nbp_state_change_wm_ns[4]; + uint32_t required_sclk; + uint32_t required_sclk_deep_sleep; + uint32_t required_yclk; + uint32_t dispclk_khz; + int32_t required_blackout_duration_us; +}; + + +/** + * Initialize structures with data which will NOT change at runtime. + */ +void bw_calcs_init( + struct bw_calcs_dceip *bw_dceip, + struct bw_calcs_vbios *bw_vbios); + +/** + * Return: + * true - Display(s) configuration supported. + * In this case 'calcs_output' contains data for HW programming + * false - Display(s) configuration not supported (not enough bandwidth). + */ +bool bw_calcs( + struct dc_context *ctx, + const struct bw_calcs_dceip *dceip, + const struct bw_calcs_vbios *vbios, + const struct bw_calcs_mode_data *mode_data, + struct bw_calcs_output *calcs_output); + + +#endif /* __BANDWIDTH_CALCS_H__ */ + diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h new file mode 100644 index 000000000000..ff271cc0aea1 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef BW_FIXED_H_ +#define BW_FIXED_H_ + +struct bw_fixed { + int64_t value; +}; + +struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3); + +struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3); + +struct bw_fixed bw_int_to_fixed(int64_t value); + +int32_t bw_fixed_to_int(struct bw_fixed value); + +struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum); + +struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw); + +struct bw_fixed bw_add(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2); + +struct bw_fixed bw_min2(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_max2(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_floor2(const struct bw_fixed arg, const struct bw_fixed significance); +struct bw_fixed bw_ceil2(const struct bw_fixed arg, const struct bw_fixed significance); + +bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2); + + +#endif //BW_FIXED_H_ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h new file mode 100644 index 000000000000..0120ee23e6be --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h @@ -0,0 +1,176 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_CLOCK_SOURCE_H__ +#define __DC_CLOCK_SOURCE_H__ + +#include "dc_types.h" +#include "include/grph_object_id.h" +#include "include/bios_parser_types.h" + +struct clock_source; + +struct spread_spectrum_data { + uint32_t percentage; /*> In unit of 0.01% or 0.001%*/ + uint32_t percentage_divider; /*> 100 or 1000 */ + uint32_t freq_range_khz; + uint32_t modulation_freq_hz; + + struct spread_spectrum_flags flags; +}; + +struct delta_sigma_data { + uint32_t feedback_amount; + uint32_t nfrac_amount; + uint32_t ds_frac_size; + uint32_t ds_frac_amount; +}; + +/** + * Pixel Clock Parameters structure + * These parameters are required as input + * when calculating Pixel Clock Dividers for requested Pixel Clock + */ +struct pixel_clk_flags { + uint32_t ENABLE_SS:1; + uint32_t DISPLAY_BLANKED:1; + uint32_t PROGRAM_PIXEL_CLOCK:1; + uint32_t PROGRAM_ID_CLOCK:1; +}; + +/** + * Display Port HW De spread of Reference Clock related Parameters structure + * Store it once at boot for later usage + */ +struct csdp_ref_clk_ds_params { + bool hw_dso_n_dp_ref_clk; +/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/ + uint32_t avg_dp_ref_clk_khz; +/* Average DP Reference clock (in KHz)*/ + uint32_t ss_percentage_on_dp_ref_clk; +/* DP Reference clock SS percentage + * (not to be mixed with DP IDCLK SS from PLL Settings)*/ + uint32_t ss_percentage_divider; +/* DP Reference clock SS percentage divider */ +}; + +struct pixel_clk_params { + uint32_t requested_pix_clk; /* in KHz */ +/*> Requested Pixel Clock + * (based on Video Timing standard used for requested mode)*/ + uint32_t requested_sym_clk; /* in KHz */ +/*> Requested Sym Clock (relevant only for display port)*/ + uint32_t dp_ref_clk; /* in KHz */ +/*> DP reference clock - calculated only for DP signal for specific cases*/ + struct graphics_object_id encoder_object_id; +/*> Encoder object Id - needed by VBIOS Exec table*/ + enum signal_type signal_type; +/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/ + enum controller_id controller_id; +/*> ControllerId - which controller using this PLL*/ + enum dc_color_depth color_depth; + struct csdp_ref_clk_ds_params de_spread_params; +/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ + + struct pixel_clk_flags flags; +}; + +/** + * Pixel Clock Dividers structure with desired Pixel Clock + * (adjusted after VBIOS exec table), + * with actually calculated Clock and reference Crystal frequency + */ +struct pll_settings { + uint32_t actual_pix_clk; + uint32_t adjusted_pix_clk; + uint32_t calculated_pix_clk; + uint32_t vco_freq; + uint32_t reference_freq; + uint32_t reference_divider; + uint32_t feedback_divider; + uint32_t fract_feedback_divider; + uint32_t pix_clk_post_divider; + uint32_t ss_percentage; + bool use_external_clk; +}; + +struct calc_pll_clock_source_init_data { + struct dc_bios *bp; + uint32_t min_pix_clk_pll_post_divider; + uint32_t max_pix_clk_pll_post_divider; + uint32_t min_pll_ref_divider; + uint32_t max_pll_ref_divider; + uint32_t min_override_input_pxl_clk_pll_freq_khz; +/* if not 0, override the firmware info */ + + uint32_t max_override_input_pxl_clk_pll_freq_khz; +/* if not 0, override the firmware info */ + + uint32_t num_fract_fb_divider_decimal_point; +/* number of decimal point for fractional feedback divider value */ + + uint32_t num_fract_fb_divider_decimal_point_precision; +/* number of decimal point to round off for fractional feedback divider value*/ + struct dc_context *ctx; + +}; + +struct calc_pll_clock_source { + uint32_t ref_freq_khz; + uint32_t min_pix_clock_pll_post_divider; + uint32_t max_pix_clock_pll_post_divider; + uint32_t min_pll_ref_divider; + uint32_t max_pll_ref_divider; + + uint32_t max_vco_khz; + uint32_t min_vco_khz; + uint32_t min_pll_input_freq_khz; + uint32_t max_pll_input_freq_khz; + + uint32_t fract_fb_divider_decimal_points_num; + uint32_t fract_fb_divider_factor; + uint32_t fract_fb_divider_precision; + uint32_t fract_fb_divider_precision_factor; + struct dc_context *ctx; +}; + +struct clock_source_funcs { + bool (*cs_power_down)( + struct clock_source *); + bool (*program_pix_clk)(struct clock_source *, + struct pixel_clk_params *, struct pll_settings *); + uint32_t (*get_pix_clk_dividers)( + struct clock_source *, + struct pixel_clk_params *, + struct pll_settings *); +}; + +struct clock_source { + struct clock_source_funcs *funcs; + struct dc_context *ctx; + enum clock_source_id id; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h new file mode 100644 index 000000000000..4992ffde7c9a --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h @@ -0,0 +1,140 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_COMPRESSOR_H__ +#define __DAL_COMPRESSOR_H__ + +#include "include/grph_object_id.h" + +enum fbc_compress_ratio { + FBC_COMPRESS_RATIO_INVALID = 0, + FBC_COMPRESS_RATIO_1TO1 = 1, + FBC_COMPRESS_RATIO_2TO1 = 2, + FBC_COMPRESS_RATIO_4TO1 = 4, + FBC_COMPRESS_RATIO_8TO1 = 8, +}; + +union fbc_physical_address { + struct { + uint32_t low_part; + int32_t high_part; + } addr; +}; + +struct compr_addr_and_pitch_params { + uint32_t inst; + uint32_t source_view_width; + uint32_t source_view_height; +}; + +struct fbc_lpt_config { + uint32_t mem_channels_num; + uint32_t banks_num; + uint32_t chan_interleave_size; + uint32_t row_size; +}; + +struct fbc_input_info { + bool dynamic_fbc_buffer_alloc; + uint32_t source_view_width; + uint32_t source_view_height; + uint32_t active_targets_num; + struct fbc_lpt_config lpt_config; +}; + +struct fbc_requested_compressed_size { + uint32_t preferred_size; + uint32_t preferred_size_alignment; + uint32_t min_size; + uint32_t min_size_alignment; + union { + struct { + /*Above preferred_size must be allocated in FB pool */ + uint32_t PREFERRED_MUST_BE_FRAME_BUFFER_POOL:1; + /*Above min_size must be allocated in FB pool */ + uint32_t MIN_MUST_BE_FRAME_BUFFER_POOL:1; + } flags; + uint32_t bits; + }; +}; + +struct fbc_compressed_surface_info { + union fbc_physical_address compressed_surface_address; + uint32_t allocated_size; + union { + struct { + uint32_t FB_POOL:1; /*Allocated in FB Pool */ + uint32_t DYNAMIC_ALLOC:1; /*Dynamic allocation */ + } allocation_flags; + uint32_t bits; + }; +}; + +enum fbc_hw_max_resolution_supported { + FBC_MAX_X = 3840, + FBC_MAX_Y = 2400 +}; + +struct fbc_max_resolution_supported { + uint32_t source_view_width; + uint32_t source_view_height; +}; + +struct compressor { + struct dc_context *ctx; + uint32_t attached_inst; + bool is_enabled; + + union { + uint32_t raw; + struct { + uint32_t FBC_SUPPORT:1; + uint32_t FB_POOL:1; + uint32_t DYNAMIC_ALLOC:1; + uint32_t LPT_SUPPORT:1; + uint32_t LPT_MC_CONFIG:1; + uint32_t DUMMY_BACKEND:1; + uint32_t CLK_GATING_DISABLED:1; + + } bits; + } options; + + union fbc_physical_address compr_surface_address; + + uint32_t embedded_panel_h_size; + uint32_t embedded_panel_v_size; + uint32_t memory_bus_width; + uint32_t banks_num; + uint32_t raw_size; + uint32_t channel_interleave_size; + uint32_t dram_channels_num; + + uint32_t allocated_size; + uint32_t preferred_requested_size; + uint32_t lpt_channels_num; + enum fbc_compress_ratio min_compress_ratio; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h new file mode 100644 index 000000000000..3e66ad7ea72d --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h @@ -0,0 +1,54 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __CORE_DC_H__ +#define __CORE_DC_H__ + +#include "core_types.h" +#include "hw_sequencer.h" + +struct dc { + struct dc_context *ctx; + + uint8_t link_count; + struct core_link *links[MAX_PIPES * 2]; + + /* TODO: determine max number of targets*/ + struct validate_context current_context; + struct resource_pool res_pool; + + /*Power State*/ + enum dc_video_power_state previous_power_state; + enum dc_video_power_state current_power_state; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip bw_dceip; + struct bw_calcs_vbios bw_vbios; + + /* HW functions */ + struct hw_sequencer_funcs hwss; +}; + +#endif /* __CORE_DC_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_status.h b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h new file mode 100644 index 000000000000..9682cf866886 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/core_status.h @@ -0,0 +1,46 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _CORE_STATUS_H_ +#define _CORE_STATUS_H_ + +enum dc_status { + DC_OK = 1, + + DC_NO_CONTROLLER_RESOURCE, + DC_NO_STREAM_ENG_RESOURCE, + DC_NO_STREAM_AUDIO_RESOURCE, + DC_NO_CLOCK_SOURCE_RESOURCE, + DC_FAIL_CONTROLLER_VALIDATE, + DC_FAIL_ENC_VALIDATE, + DC_FAIL_ATTACH_SURFACES, + DC_NO_DP_LINK_BANDWIDTH, + DC_EXCEED_DONGLE_MAX_CLK, + DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */ + + DC_ERROR_UNEXPECTED = -1 +}; + +#endif /* _CORE_STATUS_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h new file mode 100644 index 000000000000..7d63ebb8e789 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h @@ -0,0 +1,357 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _CORE_TYPES_H_ +#define _CORE_TYPES_H_ + +#include "dc.h" +#include "bandwidth_calcs.h" +#include "ddc_service_types.h" + +struct core_stream; +/********* core_target *************/ + +#define CONST_DC_TARGET_TO_CORE(dc_target) \ + container_of(dc_target, const struct core_target, public) +#define DC_TARGET_TO_CORE(dc_target) \ + container_of(dc_target, struct core_target, public) + +#define MAX_PIPES 6 +#define MAX_STREAMS 6 +#define MAX_CLOCK_SOURCES 7 + +struct core_target { + struct dc_target public; + struct dc_target_status status; + + struct dc_context *ctx; +}; + +/********* core_surface **********/ +#define DC_SURFACE_TO_CORE(dc_surface) \ + container_of(dc_surface, struct core_surface, public) + +struct core_surface { + struct dc_surface public; + struct dc_surface_status status; + struct dc_context *ctx; +}; + +void enable_surface_flip_reporting(struct dc_surface *dc_surface, + uint32_t controller_id); + +/********* core_stream ************/ +#include "grph_object_id.h" +#include "link_encoder.h" +#include "stream_encoder.h" +#include "clock_source.h" +#include "audio_interface.h" +#include "scaler_types.h" +#include "hw_sequencer_types.h" +#include "opp.h" + +#define DC_STREAM_TO_CORE(dc_stream) container_of( \ + dc_stream, struct core_stream, public) + +#define PIXEL_CLOCK 27030 + +struct core_stream { + struct dc_stream public; + + /* field internal to DC */ + const struct core_sink *sink; + + struct clock_source *clock_source; + + struct mem_input *mi; + struct input_pixel_processor *ipp; + struct transform *xfm; + struct output_pixel_processor *opp; + struct timing_generator *tg; + struct stream_encoder *stream_enc; + struct display_clock *dis_clk; + + struct overscan_info overscan; + struct scaling_ratios ratios; + struct rect viewport; + struct scaling_taps taps; + enum pixel_format format; + + uint8_t controller_idx; + + struct audio *audio; + + enum signal_type signal; + + /* TODO: move these members into appropriate places (work in progress)*/ + /* timing validation (HDMI only) */ + uint32_t max_tmds_clk_from_edid_in_mhz; + /* maximum supported deep color depth for HDMI */ + enum dc_color_depth max_hdmi_deep_color; + /* maximum supported pixel clock for HDMI */ + uint32_t max_hdmi_pixel_clock; + /* end of TODO */ + + /*TODO: AUTO merge if possible*/ + struct pixel_clk_params pix_clk_params; + struct pll_settings pll_settings; + + /*fmt*/ + /*TODO: AUTO new codepath in apply_context to hw to + * generate these bw unrelated/no fail params*/ + struct bit_depth_reduction_params bit_depth_params;/* used by DCP and FMT */ + struct clamping_and_pixel_encoding_params clamping; + struct hw_info_frame info_frame; + struct encoder_info_frame encoder_info_frame; + + struct audio_output audio_output; + struct dc_context *ctx; +}; + + +/************ core_sink *****************/ + +#define DC_SINK_TO_CORE(dc_sink) \ + container_of(dc_sink, struct core_sink, public) + +struct core_sink { + /** The public, read-only (for DM) area of sink. **/ + struct dc_sink public; + /** End-of-public area. **/ + + /** The 'protected' area - read/write access, for use only inside DC **/ + /* not used for now */ + struct core_link *link; + struct dc_context *ctx; + uint32_t dongle_max_pix_clk; + bool converter_disable_audio; +}; + +/************ link *****************/ +#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public) + +struct link_init_data { + const struct dc *dc; + struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ + uint32_t connector_index; /* this will be mapped to the HPD pins */ + uint32_t link_index; /* this is mapped to DAL display_index + TODO: remove it when DC is complete. */ + struct adapter_service *adapter_srv; +}; + +struct link_caps { + /* support for Spread Spectrum(SS) */ + bool ss_supported; + /* DP link settings (laneCount, linkRate, Spread) */ + uint32_t lane_count; + uint32_t rate; + uint32_t spread; + enum dpcd_revision dpcd_revision; +}; + +struct dpcd_caps { + union dpcd_rev dpcd_rev; + union max_lane_count max_ln_count; + + /* dongle type (DP converter, CV smart dongle) */ + enum display_dongle_type dongle_type; + /* Dongle's downstream count. */ + union sink_count sink_count; + /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, + indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ + bool is_dp_hdmi_s3d_converter; + + bool allow_invalid_MSA_timing_param; + bool panel_mode_edp; + uint32_t sink_dev_id; + uint32_t branch_dev_id; + int8_t branch_dev_name[6]; +}; + +union dp_wa { + struct { + /* keep DP receiver powered up on DisplayOutput */ + uint32_t KEEP_RECEIVER_POWERED:1; + + /* TODO: may add other member in.*/ + } bits; + uint32_t raw; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation + stream_allocations[MAX_CONTROLLER_NUM]; +}; + +struct core_link { + struct dc_link public; + const struct dc *dc; + + struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/ + + struct adapter_service *adapter_srv; + struct link_encoder *link_enc; + struct ddc_service *ddc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + /* caps is the same as reported_link_cap. link_traing use + * reported_link_cap. Will clean up. TODO */ + struct link_settings reported_link_cap; + struct link_settings verified_link_cap; + struct link_settings max_link_setting; + struct link_settings cur_link_settings; + struct lane_settings ln_setting; + struct dpcd_caps dpcd_caps; + unsigned int dpcd_sink_count; + + enum edp_revision edp_revision; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; +}; + +#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public) + +struct core_link *link_create(const struct link_init_data *init_params); +void link_destroy(struct core_link **link); + +enum dc_status dc_link_validate_mode_timing( + const struct core_sink *sink, + struct core_link *link, + const struct dc_crtc_timing *timing); + +void core_link_resume(struct core_link *link); + +void core_link_enable_stream( + struct core_link *link, + struct core_stream *stream); + +void core_link_disable_stream( + struct core_link *link, + struct core_stream *stream); + +/********** DAL Core*********************/ +#include "display_clock_interface.h" + +struct resource_pool; +struct validate_context; + +struct resource_funcs { + void (*destruct)(struct resource_pool *pool); + struct link_encoder *(*link_enc_create)( + const struct encoder_init_data *init); + void (*link_enc_destroy)(struct link_encoder **enc); + enum dc_status (*validate_with_context)( + const struct dc *dc, + const struct dc_validation_set set[], + uint8_t set_count, + struct validate_context *context); + + enum dc_status (*validate_bandwidth)( + const struct dc *dc, + struct validate_context *context); +}; + +struct resource_pool { + struct scaler_filter * scaler_filter; + + struct mem_input *mis[MAX_PIPES]; + struct input_pixel_processor *ipps[MAX_PIPES]; + struct transform *transforms[MAX_PIPES]; + struct output_pixel_processor *opps[MAX_PIPES]; + struct timing_generator *timing_generators[MAX_STREAMS]; + struct stream_encoder *stream_enc[MAX_PIPES * 2]; + + uint8_t controller_count; + uint8_t stream_enc_count; + + union supported_stream_engines stream_engines; + + struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; + uint8_t clk_src_count; + + struct audio *audios[MAX_STREAMS]; + uint8_t audio_count; + + struct display_clock *display_clock; + struct adapter_service *adapter_srv; + struct irq_service *irqs; + + struct resource_funcs *funcs; +}; + +struct controller_ctx { + struct core_surface *surface; + struct core_stream *stream; + struct flags { + bool unchanged; + bool timing_changed; + } flags; +}; + +struct resource_context { + struct resource_pool pool; + struct controller_ctx controller_ctx[MAX_PIPES]; + union supported_stream_engines used_stream_engines; + bool is_stream_enc_acquired[MAX_PIPES * 2]; + bool is_audio_acquired[MAX_STREAMS]; + uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; + }; + +struct target_flags { + bool unchanged; +}; +struct validate_context { + struct core_target *targets[MAX_PIPES]; + struct target_flags target_flags[MAX_PIPES]; + uint8_t target_count; + + struct resource_context res_ctx; + + struct bw_calcs_mode_data bw_mode_data; + /* The output from BW and WM calculations. */ + struct bw_calcs_output bw_results; +}; + + +#endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h new file mode 100644 index 000000000000..18104d6fa6d3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h @@ -0,0 +1,151 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DDC_SERVICE_H__ +#define __DAL_DDC_SERVICE_H__ + +#include "include/ddc_service_types.h" +#include "include/i2caux_interface.h" + +#define EDID_SEGMENT_SIZE 256 + +struct ddc_service; +struct adapter_service; +struct graphics_object_id; +enum ddc_result; +struct av_sync_data; +struct dp_receiver_id_info; + +struct i2c_payloads; +struct aux_payloads; + +struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count); +struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p); +uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p); +void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p); + +struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count); +struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p); +uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p); +void dal_ddc_aux_payloads_destroy(struct aux_payloads **p); + +void dal_ddc_i2c_payloads_add( + struct i2c_payloads *payloads, + uint32_t address, + uint32_t len, + uint8_t *data, + bool write); + +void dal_ddc_aux_payloads_add( + struct aux_payloads *payloads, + uint32_t address, + uint32_t len, + uint8_t *data, + bool write); + +struct ddc_service_init_data { + struct adapter_service *as; + struct graphics_object_id id; + struct dc_context *ctx; +}; + +struct ddc_service *dal_ddc_service_create( + struct ddc_service_init_data *ddc_init_data); + +void dal_ddc_service_destroy(struct ddc_service **ddc); + +enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc); + +void dal_ddc_service_set_transaction_type( + struct ddc_service *ddc, + enum ddc_transaction_type type); + +bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc); + +uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc); + +uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc); + +void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf); + +void dal_ddc_service_i2c_query_dp_dual_mode_adaptor( + struct ddc_service *ddc, + struct display_sink_capability *sink_cap); + +bool dal_ddc_service_query_ddc_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *write_buf, + uint32_t write_size, + uint8_t *read_buf, + uint32_t read_size); + +bool dal_ddc_service_get_dp_receiver_id_info( + struct ddc_service *ddc, + struct dp_receiver_id_info *info); + +enum ddc_result dal_ddc_service_read_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *data, + uint32_t len); + +enum ddc_result dal_ddc_service_write_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + const uint8_t *data, + uint32_t len); + +void dal_ddc_service_write_scdc_data( + struct ddc_service *ddc_service, + uint32_t pix_clk, + bool lte_340_scramble); + +void dal_ddc_service_read_scdc_data( + struct ddc_service *ddc_service); + +void ddc_service_set_dongle_type(struct ddc_service *ddc, + enum display_dongle_type dongle_type); + +void dal_ddc_service_set_ddc_pin( + struct ddc_service *ddc_service, + struct ddc *ddc); + +struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service); +void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service); + +enum ddc_result dal_ddc_service_read_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *data, + uint32_t len); +enum ddc_result dal_ddc_service_write_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + const uint8_t *data, + uint32_t len); + +#endif /* __DAL_DDC_SERVICE_H__ */ + diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h new file mode 100644 index 000000000000..682c0b432bdb --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h @@ -0,0 +1,56 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_DP_H__ +#define __DC_LINK_DP_H__ + +struct core_link; +struct core_stream; +struct link_settings; + +bool dp_hbr_verify_link_cap( + struct core_link *link, + struct link_settings *known_limit_link_setting); + +bool dp_validate_mode_timing( + struct core_link *link, + const struct dc_crtc_timing *timing); + +void decide_link_settings( + struct core_stream *stream, + struct link_settings *link_setting); + +bool perform_link_training( + struct core_link *link, + const struct link_settings *link_setting, + bool skip_video_pattern); + +bool is_mst_supported(struct core_link *link); + +void detect_dp_sink_caps(struct core_link *link); + +bool is_dp_active_dongle(const struct core_link *link); + +#endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h new file mode 100644 index 000000000000..17cb10f117e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h @@ -0,0 +1,118 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef GAMMA_TYPES_H_ + +#define GAMMA_TYPES_H_ + +#include "dc_types.h" +#include "dm_services_types.h" + +/* TODO: Used in IPP and OPP */ +struct dev_c_lut { + uint8_t red; + uint8_t green; + uint8_t blue; +}; + +struct dev_c_lut16 { + uint16_t red; + uint16_t green; + uint16_t blue; +}; + +struct regamma_ramp { + uint16_t gamma[RGB_256X3X16 * 3]; +}; + +/* used by Graphics and Overlay gamma */ +struct gamma_coeff { + int32_t gamma[3]; + int32_t a0[3]; /* index 0 for red, 1 for green, 2 for blue */ + int32_t a1[3]; + int32_t a2[3]; + int32_t a3[3]; +}; + +struct regamma_lut { + union { + struct { + uint32_t GRAPHICS_DEGAMMA_SRGB :1; + uint32_t OVERLAY_DEGAMMA_SRGB :1; + uint32_t GAMMA_RAMP_ARRAY :1; + uint32_t APPLY_DEGAMMA :1; + uint32_t RESERVED :28; + } bits; + uint32_t value; + } features; + + union { + struct regamma_ramp regamma_ramp; + struct gamma_coeff gamma_coeff; + }; +}; + +union gamma_flag { + struct { + uint32_t config_is_changed :1; + uint32_t both_pipe_req :1; + uint32_t regamma_update :1; + uint32_t gamma_update :1; + uint32_t reserved :28; + } bits; + uint32_t u_all; +}; + +enum graphics_regamma_adjust { + GRAPHICS_REGAMMA_ADJUST_BYPASS = 0, GRAPHICS_REGAMMA_ADJUST_HW, /* without adjustments */ + GRAPHICS_REGAMMA_ADJUST_SW /* use adjustments */ +}; + +enum graphics_gamma_lut { + GRAPHICS_GAMMA_LUT_LEGACY = 0, /* use only legacy LUT */ + GRAPHICS_GAMMA_LUT_REGAMMA, /* use only regamma LUT */ + GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA /* use legacy & regamma LUT's */ +}; + +enum graphics_degamma_adjust { + GRAPHICS_DEGAMMA_ADJUST_BYPASS = 0, GRAPHICS_DEGAMMA_ADJUST_HW, /*without adjustments */ + GRAPHICS_DEGAMMA_ADJUST_SW /* use adjustments */ +}; + +struct gamma_parameters { + union gamma_flag flag; + enum pixel_format surface_pixel_format; /*OS surface pixel format*/ + struct regamma_lut regamma; + + enum graphics_regamma_adjust regamma_adjust_type; + enum graphics_degamma_adjust degamma_adjust_type; + + enum graphics_gamma_lut selected_gamma_lut; + + bool disable_adjustments; + + /* here we grow with parameters if necessary */ +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h new file mode 100644 index 000000000000..8460dd729e91 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HW_SEQUENCER_H__ +#define __DC_HW_SEQUENCER_H__ +#include "core_types.h" + +struct gamma_parameters; + +enum pipe_gating_control { + PIPE_GATING_CONTROL_DISABLE = 0, + PIPE_GATING_CONTROL_ENABLE, + PIPE_GATING_CONTROL_INIT +}; + + +struct hw_sequencer_funcs { + + enum dc_status (*apply_ctx_to_hw)( + const struct dc *dc, struct validate_context *context); + + void (*reset_hw_ctx)( + struct dc *dc, + struct validate_context *context, + uint8_t target_count); + + bool (*set_plane_config)( + const struct dc *dc, + struct core_surface *surface, + struct core_target *target); + + bool (*update_plane_address)( + const struct dc *dc, + const struct core_surface *surface, + struct core_target *target); + + bool (*set_gamma_ramp)( + struct input_pixel_processor *ipp, + struct output_pixel_processor *opp, + const struct gamma_ramp *ramp, + const struct gamma_parameters *params); + + void (*power_down)(struct dc *dc); + + void (*enable_accelerated_mode)(struct dc *dc); + + void (*enable_timing_synchronization)( + struct dc_context *dc_ctx, + uint32_t timing_generator_num, + struct timing_generator *tgs[]); + + /* backlight control */ + void (*encoder_set_lcd_backlight_level)( + struct link_encoder *enc, uint32_t level); + + + void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t); + + /* power management */ + void (*clock_gating_power_up)(struct dc_context *ctx, bool enable); + + void (*enable_display_pipe_clock_gating)( + struct dc_context *ctx, + bool clock_gating); + + bool (*enable_display_power_gating)( + struct dc_context *ctx, + uint8_t controller_id, + struct dc_bios *dcb, + enum pipe_gating_control power_gating); + + void (*program_bw)(struct dc *dc, struct validate_context *context); + + void (*enable_stream)(struct core_stream *stream); + + void (*disable_stream)(struct core_stream *stream); + + void (*enable_fe_clock)( + struct dc_context *ctx, uint8_t controller_id, bool enable); + + bool (*pipe_control_lock)( + struct dc_context *ctx, + uint8_t controller_idx, + uint32_t control_mask, + bool lock); + + void (*set_blender_mode)( + struct dc_context *ctx, + uint8_t controller_id, + uint32_t mode); + + void (*set_displaymarks)( + const struct dc *dc, + struct validate_context *context); + + void (*set_display_clock)(struct validate_context *context); +}; + +bool dc_construct_hw_sequencer( + struct adapter_service *adapter_serv, + struct dc *dc); + + +#endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h new file mode 100644 index 000000000000..8e7cc31dfb9c --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h @@ -0,0 +1,106 @@ + +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IPP_H__ +#define __DAL_IPP_H__ + +#include "include/grph_object_id.h" +#include "include/grph_csc_types.h" +#include "include/video_csc_types.h" +#include "include/hw_sequencer_types.h" + +struct dev_c_lut; + +#define MAXTRIX_COEFFICIENTS_NUMBER 12 +#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) +#define MAX_OVL_MATRIX_COUNT 12 + +/* IPP RELATED */ +struct input_pixel_processor { + struct dc_context *ctx; + uint32_t inst; + struct ipp_funcs *funcs; +}; + +enum wide_gamut_degamma_mode { + /* 00 - BITS1:0 Bypass */ + WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_BYPASS, + /* 0x1 - PWL gamma ROM A */ + WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_A, + /* 0x2 - PWL gamma ROM B */ + WIDE_GAMUT_DEGAMMA_MODE_GRAPHICS_PWL_ROM_B, + /* 00 - BITS5:4 Bypass */ + WIDE_GAMUT_DEGAMMA_MODE_OVL_BYPASS, + /* 0x1 - PWL gamma ROM A */ + WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_A, + /* 0x2 - PWL gamma ROM B */ + WIDE_GAMUT_DEGAMMA_MODE_OVL_PWL_ROM_B, +}; + +struct dcp_video_matrix { + enum ovl_color_space color_space; + int32_t value[MAXTRIX_COEFFICIENTS_NUMBER]; +}; + +struct ipp_funcs { + + /* CURSOR RELATED */ + bool (*ipp_cursor_set_position)( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position); + + bool (*ipp_cursor_set_attributes)( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes); + + /* DEGAMMA RELATED */ + bool (*ipp_set_degamma)( + struct input_pixel_processor *ipp, + const struct gamma_parameters *params, + bool force_bypass); + + void (*ipp_program_prescale)( + struct input_pixel_processor *ipp, + enum pixel_format pixel_format); + + void (*ipp_set_legacy_input_gamma_mode)( + struct input_pixel_processor *ipp, + bool is_legacy); + + bool (*ipp_set_legacy_input_gamma_ramp)( + struct input_pixel_processor *ipp, + const struct gamma_ramp *gamma_ramp, + const struct gamma_parameters *params); + + bool (*ipp_set_palette)( + struct input_pixel_processor *ipp, + const struct dev_c_lut *palette, + uint32_t start, + uint32_t length, + enum pixel_format surface_pixel_format); +}; + +#endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h new file mode 100644 index 000000000000..d60c59463fc2 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h @@ -0,0 +1,138 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef LINK_ENCODER_H_ +#define LINK_ENCODER_H_ + +#include "grph_object_defs.h" +#include "signal_types.h" +#include "dc_types.h" + +struct dc_context; +struct adapter_service; +struct encoder_set_dp_phy_pattern_param; +struct link_mst_stream_allocation_table; +struct link_settings; +struct link_training_settings; +struct core_stream; + +struct encoder_init_data { + struct adapter_service *adapter_service; + enum channel_id channel; + struct graphics_object_id connector; + enum hpd_source_id hpd_source; + /* TODO: in DAL2, here was pointer to EventManagerInterface */ + struct graphics_object_id encoder; + struct dc_context *ctx; + enum transmitter transmitter; +}; + +struct encoder_feature_support { + union { + struct { + /* 1 - external encoder; 0 - internal encoder */ + uint32_t EXTERNAL_ENCODER:1; + uint32_t ANALOG_ENCODER:1; + uint32_t STEREO_SYNC:1; + /* check the DDC data pin + * when performing DP Sink detection */ + uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1; + /* CPLIB authentication + * for external DP chip supported */ + uint32_t CPLIB_DP_AUTHENTICATION:1; + uint32_t IS_HBR2_CAPABLE:1; + uint32_t IS_HBR2_VALIDATED:1; + uint32_t IS_TPS3_CAPABLE:1; + uint32_t IS_AUDIO_CAPABLE:1; + uint32_t IS_VCE_SUPPORTED:1; + uint32_t IS_CONVERTER:1; + uint32_t IS_Y_ONLY_CAPABLE:1; + uint32_t IS_YCBCR_CAPABLE:1; + } bits; + uint32_t raw; + } flags; + /* maximum supported deep color depth */ + enum dc_color_depth max_deep_color; + /* maximum supported clock */ + uint32_t max_pixel_clock; +}; + +struct link_enc_status { + int dummy; /*TODO*/ +}; +struct link_encoder { + struct link_encoder_funcs *funcs; + struct adapter_service *adapter_service; + int32_t aux_channel_offset; + struct dc_context *ctx; + struct graphics_object_id id; + struct graphics_object_id connector; + uint32_t input_signals; + uint32_t output_signals; + enum engine_id preferred_engine; + struct encoder_feature_support features; + enum transmitter transmitter; + enum hpd_source_id hpd_source; +}; + +struct link_encoder_funcs { + bool (*validate_output_with_stream)(struct link_encoder *enc, + struct core_stream *stream); + void (*hw_init)(struct link_encoder *enc); + void (*setup)(struct link_encoder *enc, + enum signal_type signal); + void (*enable_tmds_output)(struct link_encoder *enc, + enum clock_source_id clock_source, + enum dc_color_depth color_depth, + bool hdmi, + bool dual_link, + uint32_t pixel_clock); + void (*enable_dp_output)(struct link_encoder *enc, + const struct link_settings *link_settings, + enum clock_source_id clock_source); + void (*enable_dp_mst_output)(struct link_encoder *enc, + const struct link_settings *link_settings, + enum clock_source_id clock_source); + void (*disable_output)(struct link_encoder *link_enc, + enum signal_type signal); + void (*dp_set_lane_settings)(struct link_encoder *enc, + const struct link_training_settings *link_settings); + void (*dp_set_phy_pattern)(struct link_encoder *enc, + const struct encoder_set_dp_phy_pattern_param *para); + void (*update_mst_stream_allocation_table)( + struct link_encoder *enc, + const struct link_mst_stream_allocation_table *table); + void (*set_lcd_backlight_level) (struct link_encoder *enc, + uint32_t level); + void (*backlight_control) (struct link_encoder *enc, + bool enable); + void (*power_control) (struct link_encoder *enc, + bool power_up); + void (*connect_dig_be_to_fe)(struct link_encoder *enc, + enum engine_id engine, + bool connect); +}; + +#endif /* LINK_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h new file mode 100644 index 000000000000..d9a48c037c3e --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h @@ -0,0 +1,68 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_HWSS_H__ +#define __DC_LINK_HWSS_H__ + +#include "inc/core_status.h" + +enum dc_status core_link_read_dpcd( + struct core_link* link, + uint32_t address, + uint8_t *data, + uint32_t size); + +enum dc_status core_link_write_dpcd( + struct core_link* link, + uint32_t address, + const uint8_t *data, + uint32_t size); + +void dp_enable_link_phy( + struct core_link *link, + enum signal_type signal, + const struct link_settings *link_settings); + +void dp_receiver_power_ctrl(struct core_link *link, bool on); + +void dp_disable_link_phy(struct core_link *link, enum signal_type signal); + +void dp_disable_link_phy_mst(struct core_link *link, struct core_stream *stream); + +bool dp_set_hw_training_pattern( + struct core_link *link, + enum hw_dp_training_pattern pattern); + +void dp_set_hw_lane_settings( + struct core_link *link, + const struct link_training_settings *link_settings); + +void dp_set_hw_test_pattern( + struct core_link *link, + enum dp_test_pattern test_pattern); + +enum dp_panel_mode dp_get_panel_mode(struct core_link *link); + +#endif /* __DC_LINK_HWSS_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h new file mode 100644 index 000000000000..7d6335d3bcf4 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h @@ -0,0 +1,83 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_MEM_INPUT_H__ +#define __DAL_MEM_INPUT_H__ + +#include "include/grph_object_id.h" +#include "dc.h" + +struct mem_input { + struct mem_input_funcs *funcs; + struct dc_context *ctx; + uint32_t inst; +}; + +struct mem_input_funcs { + void (*mem_input_program_safe_display_marks)(struct mem_input *mi); + void (*mem_input_program_display_marks)( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t h_total, + uint32_t pixel_clk_in_khz, + uint32_t pstate_blackout_duration_ns); + void (*mem_input_allocate_dmif_buffer)( + struct mem_input *mem_input, + struct dc_crtc_timing *timing, + uint32_t paths_num); + void (*mem_input_deallocate_dmif_buffer)( + struct mem_input *mem_input, uint32_t paths_num); + bool (*mem_input_program_surface_flip_and_addr)( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + bool (*mem_input_program_surface_config)( + struct mem_input *mem_input, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation); +}; + +enum stutter_mode_type { + STUTTER_MODE_LEGACY = 0X00000001, + STUTTER_MODE_ENHANCED = 0X00000002, + STUTTER_MODE_FID_NBP_STATE = 0X00000004, + STUTTER_MODE_WATERMARK_NBP_STATE = 0X00000008, + STUTTER_MODE_SINGLE_DISPLAY_MODEL = 0X00000010, + STUTTER_MODE_MIXED_DISPLAY_MODEL = 0X00000020, + STUTTER_MODE_DUAL_DMIF_BUFFER = 0X00000040, + STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION = 0X00000080, + STUTTER_MODE_NO_ADVANCED_REQUEST = 0X00000100, + STUTTER_MODE_NO_LB_RESET = 0X00000200, + STUTTER_MODE_DISABLED = 0X00000400, + STUTTER_MODE_AGGRESSIVE_MARKS = 0X00000800, + STUTTER_MODE_URGENCY = 0X00001000, + STUTTER_MODE_QUAD_DMIF_BUFFER = 0X00002000, + STUTTER_MODE_NOT_USED = 0X00008000 +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h new file mode 100644 index 000000000000..b097983246df --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h @@ -0,0 +1,308 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_OPP_H__ +#define __DAL_OPP_H__ + +#include "dc_types.h" +#include "grph_object_id.h" +#include "grph_csc_types.h" +#include "dm_services_types.h" + +struct fixed31_32; +struct gamma_parameters; + +/* TODO: Need cleanup */ + +enum clamping_range { + CLAMPING_FULL_RANGE = 0, /* No Clamping */ + CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ + CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ + CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ + /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ + CLAMPING_LIMITED_RANGE_PROGRAMMABLE +}; + +struct clamping_and_pixel_encoding_params { + enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */ + enum clamping_range clamping_level; /* Clamping identifier */ + enum dc_color_depth c_depth; /* Deep color use. */ +}; + +struct bit_depth_reduction_params { + struct { + /* truncate/round */ + /* trunc/round enabled*/ + uint32_t TRUNCATE_ENABLED:1; + /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/ + uint32_t TRUNCATE_DEPTH:2; + /* truncate or round*/ + uint32_t TRUNCATE_MODE:1; + + /* spatial dither */ + /* Spatial Bit Depth Reduction enabled*/ + uint32_t SPATIAL_DITHER_ENABLED:1; + /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/ + uint32_t SPATIAL_DITHER_DEPTH:2; + /* 0-3 to select patterns*/ + uint32_t SPATIAL_DITHER_MODE:2; + /* Enable RGB random dithering*/ + uint32_t RGB_RANDOM:1; + /* Enable Frame random dithering*/ + uint32_t FRAME_RANDOM:1; + /* Enable HighPass random dithering*/ + uint32_t HIGHPASS_RANDOM:1; + + /* temporal dither*/ + /* frame modulation enabled*/ + uint32_t FRAME_MODULATION_ENABLED:1; + /* same as for trunc/spatial*/ + uint32_t FRAME_MODULATION_DEPTH:2; + /* 2/4 gray levels*/ + uint32_t TEMPORAL_LEVEL:1; + uint32_t FRC25:2; + uint32_t FRC50:2; + uint32_t FRC75:2; + } flags; + + uint32_t r_seed_value; + uint32_t b_seed_value; + uint32_t g_seed_value; +}; + + + +enum wide_gamut_regamma_mode { + /* 0x0 - BITS2:0 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B, + /* 0x0 - BITS6:4 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B +}; + +struct pwl_result_data { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + + struct fixed31_32 delta_red; + struct fixed31_32 delta_green; + struct fixed31_32 delta_blue; + + uint32_t red_reg; + uint32_t green_reg; + uint32_t blue_reg; + + uint32_t delta_red_reg; + uint32_t delta_green_reg; + uint32_t delta_blue_reg; +}; + +struct gamma_pixel { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; +}; + +struct gamma_curve { + uint32_t offset; + uint32_t segments_num; +}; + +struct curve_points { + struct fixed31_32 x; + struct fixed31_32 y; + struct fixed31_32 offset; + struct fixed31_32 slope; + + uint32_t custom_float_x; + uint32_t custom_float_y; + uint32_t custom_float_offset; + uint32_t custom_float_slope; +}; + +enum channel_name { + CHANNEL_NAME_RED, + CHANNEL_NAME_GREEN, + CHANNEL_NAME_BLUE +}; + +struct custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +struct custom_float_value { + uint32_t mantissa; + uint32_t exponenta; + uint32_t value; + bool negative; +}; + +struct hw_x_point { + uint32_t custom_float_x; + uint32_t custom_float_x_adjusted; + struct fixed31_32 x; + struct fixed31_32 adjusted_x; + struct fixed31_32 regamma_y_red; + struct fixed31_32 regamma_y_green; + struct fixed31_32 regamma_y_blue; + +}; + +struct pwl_float_data_ex { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; + struct fixed31_32 delta_r; + struct fixed31_32 delta_g; + struct fixed31_32 delta_b; +}; + +enum hw_point_position { + /* hw point sits between left and right sw points */ + HW_POINT_POSITION_MIDDLE, + /* hw point lays left from left (smaller) sw point */ + HW_POINT_POSITION_LEFT, + /* hw point lays stays from right (bigger) sw point */ + HW_POINT_POSITION_RIGHT +}; + +struct gamma_point { + int32_t left_index; + int32_t right_index; + enum hw_point_position pos; + struct fixed31_32 coeff; +}; + +struct pixel_gamma_point { + struct gamma_point r; + struct gamma_point g; + struct gamma_point b; +}; + +struct gamma_coefficients { + struct fixed31_32 a0[3]; + struct fixed31_32 a1[3]; + struct fixed31_32 a2[3]; + struct fixed31_32 a3[3]; + struct fixed31_32 user_gamma[3]; + struct fixed31_32 user_contrast; + struct fixed31_32 user_brightness; +}; + +struct csc_adjustments { + struct fixed31_32 contrast; + struct fixed31_32 saturation; + struct fixed31_32 brightness; + struct fixed31_32 hue; +}; + +struct pwl_float_data { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; +}; + + +/* TODO: Use when we redefine the OPP interface */ +enum opp_regamma { + OPP_REGAMMA_BYPASS = 0, + OPP_REGAMMA_SRGB, + OPP_REGAMMA_3_6, + OPP_REGAMMA_PQ, + OPP_REGAMMA_PQ_INTERIM, +}; + +struct output_pixel_processor { + struct dc_context *ctx; + uint32_t inst; + struct opp_funcs *funcs; +}; + +enum fmt_stereo_action { + FMT_STEREO_ACTION_ENABLE = 0, + FMT_STEREO_ACTION_DISABLE, + FMT_STEREO_ACTION_UPDATE_POLARITY +}; + +struct opp_funcs { + void (*opp_power_on_regamma_lut)( + struct output_pixel_processor *opp, + bool power_on); + + bool (*opp_set_regamma)( + struct output_pixel_processor *opp, + const struct gamma_ramp *ramp, + const struct gamma_parameters *params, + bool force_bypass); + + bool (*opp_map_legacy_and_regamma_hw_to_x_user)( + struct output_pixel_processor *opp, + const struct gamma_ramp *gamma_ramp, + const struct gamma_parameters *params); + + void (*opp_set_csc_adjustment)( + struct output_pixel_processor *opp, + const struct grph_csc_adjustment *adjust); + + void (*opp_set_csc_default)( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + + /* FORMATTER RELATED */ + void (*opp_program_bit_depth_reduction)( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + + void (*opp_program_clamping_and_pixel_encoding)( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params); + + + void (*opp_set_dyn_expansion)( + struct output_pixel_processor *opp, + enum color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h new file mode 100644 index 000000000000..bda92e3c4f66 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h @@ -0,0 +1,80 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ +#define DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ + +#include "core_types.h" +#include "core_status.h" +#include "core_dc.h" + +/* TODO unhardcode, 4 for CZ*/ +#define MEMORY_TYPE_MULTIPLIER 4 + +bool dc_construct_resource_pool(struct adapter_service *adapter_serv, + struct dc *dc, + uint8_t num_virtual_links); + +void build_scaling_params( + const struct dc_surface *surface, + struct core_stream *stream); + +void build_scaling_params_for_context( + const struct dc *dc, + struct validate_context *context); + +void unreference_clock_source( + struct resource_context *res_ctx, + struct clock_source *clock_source); + +void reference_clock_source( + struct resource_context *res_ctx, + struct clock_source *clock_source); + +bool is_same_timing( + const struct dc_crtc_timing *timing1, + const struct dc_crtc_timing *timing2); + +struct clock_source *find_used_clk_src_for_sharing( + struct validate_context *context, + struct core_stream *stream); + +bool logical_attach_surfaces_to_target( + struct dc_surface *surfaces[], + uint8_t surface_count, + struct dc_target *dc_target); + +void pplib_apply_safe_state(const struct dc *dc); + +void pplib_apply_display_requirements( + const struct dc *dc, + const struct validate_context *context); + +void build_info_frame(struct core_stream *stream); + +enum dc_status map_resources( + const struct dc *dc, + struct validate_context *context); + +#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h new file mode 100644 index 000000000000..6bb1d007de21 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h @@ -0,0 +1,88 @@ +/* + * stream_encoder.h + * + */ + +#ifndef STREAM_ENCODER_H_ +#define STREAM_ENCODER_H_ + +#include "include/hw_sequencer_types.h" + +struct dc_bios; +struct dc_context; +struct dc_crtc_timing; + + +struct encoder_info_packet { + bool valid; + uint8_t hb0; + uint8_t hb1; + uint8_t hb2; + uint8_t hb3; + uint8_t sb[28]; +}; + +struct encoder_info_frame { + /* auxiliary video information */ + struct encoder_info_packet avi; + struct encoder_info_packet gamut; + struct encoder_info_packet vendor; + /* source product description */ + struct encoder_info_packet spd; + /* video stream configuration */ + struct encoder_info_packet vsc; +}; + +struct encoder_unblank_param { + struct hw_crtc_timing crtc_timing; + struct link_settings link_settings; +}; + +struct encoder_set_dp_phy_pattern_param { + enum dp_test_pattern dp_phy_pattern; + const uint8_t *custom_pattern; + uint32_t custom_pattern_size; + enum dp_panel_mode dp_panel_mode; +}; + + +struct stream_encoder { + struct stream_encoder_funcs *funcs; + struct dc_context *ctx; + struct dc_bios *bp; + enum engine_id id; +}; + +struct stream_encoder_funcs { + void (*dp_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing); + void (*hdmi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool enable_audio); + void (*dvi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool is_dual_link); + void (*set_mst_bandwidth)( + struct stream_encoder *enc, + struct fixed31_32 avg_time_slots_per_mtp); + void (*update_hdmi_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + void (*stop_hdmi_info_packets)( + struct stream_encoder *enc); + void (*update_dp_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + void (*stop_dp_info_packets)( + struct stream_encoder *enc); + void (*dp_blank)( + struct stream_encoder *enc); + void (*dp_unblank)( + struct stream_encoder *enc, + const struct encoder_unblank_param *param); +}; + +#endif /* STREAM_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h new file mode 100644 index 000000000000..e9ca16938572 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h @@ -0,0 +1,155 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TIMING_GENERATOR_TYPES_H__ +#define __DAL_TIMING_GENERATOR_TYPES_H__ + +#include "include/grph_csc_types.h" + +struct dc_bios; + +/** + * These parameters are required as input when doing blanking/Unblanking +*/ +struct crtc_black_color { + uint32_t black_color_r_cr; + uint32_t black_color_g_y; + uint32_t black_color_b_cb; +}; + +/* Contains CRTC vertical/horizontal pixel counters */ +struct crtc_position { + uint32_t vertical_count; + uint32_t horizontal_count; + uint32_t nominal_vcount; +}; + + +enum dcp_gsl_purpose { + DCP_GSL_PURPOSE_SURFACE_FLIP = 0, + DCP_GSL_PURPOSE_STEREO3D_PHASE, + DCP_GSL_PURPOSE_UNDEFINED +}; + +struct dcp_gsl_params { + enum sync_source gsl_group; + enum dcp_gsl_purpose gsl_purpose; + bool timing_server; + bool overlay_present; + bool gsl_paused; +}; + +#define LEFT_EYE_3D_PRIMARY_SURFACE 1 +#define RIGHT_EYE_3D_PRIMARY_SURFACE 0 + +enum test_pattern_dyn_range { + TEST_PATTERN_DYN_RANGE_VESA = 0, + TEST_PATTERN_DYN_RANGE_CEA +}; + +enum test_pattern_mode { + TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, + TEST_PATTERN_MODE_VERTICALBARS, + TEST_PATTERN_MODE_HORIZONTALBARS, + TEST_PATTERN_MODE_SINGLERAMP_RGB, + TEST_PATTERN_MODE_DUALRAMP_RGB +}; + +enum test_pattern_color_format { + TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, + TEST_PATTERN_COLOR_FORMAT_BPC_8, + TEST_PATTERN_COLOR_FORMAT_BPC_10, + TEST_PATTERN_COLOR_FORMAT_BPC_12 +}; + +enum controller_dp_test_pattern { + CONTROLLER_DP_TEST_PATTERN_D102 = 0, + CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, + CONTROLLER_DP_TEST_PATTERN_PRBS7, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, + CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, + CONTROLLER_DP_TEST_PATTERN_COLORRAMP, + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + CONTROLLER_DP_TEST_PATTERN_RESERVED_8, + CONTROLLER_DP_TEST_PATTERN_RESERVED_9, + CONTROLLER_DP_TEST_PATTERN_RESERVED_A, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA +}; + +enum crtc_state { + CRTC_STATE_VBLANK = 0, + CRTC_STATE_VACTIVE +}; + +struct timing_generator { + struct timing_generator_funcs *funcs; + struct dc_bios *bp; + struct dc_context *ctx; +}; + + +struct dc_crtc_timing; + +struct timing_generator_funcs { + bool (*validate_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing); + void (*program_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + bool use_vbios); + bool (*enable_crtc)(struct timing_generator *tg); + bool (*disable_crtc)(struct timing_generator *tg); + bool (*is_counter_moving)(struct timing_generator *tg); + void (*get_position)(struct timing_generator *tg, + int32_t *h_position, + int32_t *v_position); + uint32_t (*get_frame_count)(struct timing_generator *tg); + void (*set_early_control)(struct timing_generator *tg, + uint32_t early_cntl); + void (*wait_for_state)(struct timing_generator *tg, + enum crtc_state state); + bool (*set_blank)(struct timing_generator *tg, + bool enable_blanking); + void (*set_overscan_blank_color) (struct timing_generator *tg, enum color_space black_color); + void (*set_blank_color)(struct timing_generator *tg, enum color_space black_color); + void (*set_colors)(struct timing_generator *tg, + const struct crtc_black_color *blank_color, + const struct crtc_black_color *overscan_color); + + void (*disable_vga)(struct timing_generator *tg); + bool (*did_triggered_reset_occur)(struct timing_generator *tg); + void (*setup_global_swap_lock)(struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params); + void (*enable_reset_trigger)(struct timing_generator *tg, + const struct trigger_params *trigger_params); + void (*disable_reset_trigger)(struct timing_generator *tg); + void (*tear_down_global_swap_lock)(struct timing_generator *tg); + void (*enable_advanced_request)(struct timing_generator *tg, + bool enable, const struct dc_crtc_timing *timing); +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/inc/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/transform.h new file mode 100644 index 000000000000..22803575ed72 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/inc/transform.h @@ -0,0 +1,217 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TRANSFORM_H__ +#define __DAL_TRANSFORM_H__ + +#include "include/scaler_types.h" +#include "include/grph_csc_types.h" +#include "calcs/scaler_filter.h" +#include "grph_object_id.h" + +struct bit_depth_reduction_params; + +enum scaling_type { + SCALING_TYPE_NO_SCALING = 0, + SCALING_TYPE_UPSCALING, + SCALING_TYPE_DOWNSCALING +}; + +struct transform { + struct transform_funcs *funcs; + struct dc_context *ctx; + uint32_t inst; + struct scaler_filter *filter; +}; + + +struct scaler_taps_and_ratio { + uint32_t h_tap; + uint32_t v_tap; + uint32_t lo_ratio; + uint32_t hi_ratio; +}; + +struct scaler_taps { + uint32_t h_tap; + uint32_t v_tap; +}; + +struct sclv_ratios_inits { + uint32_t chroma_enable; + uint32_t h_int_scale_ratio_luma; + uint32_t h_int_scale_ratio_chroma; + uint32_t v_int_scale_ratio_luma; + uint32_t v_int_scale_ratio_chroma; + struct init_int_and_frac h_init_luma; + struct init_int_and_frac h_init_chroma; + struct init_int_and_frac v_init_luma; + struct init_int_and_frac v_init_chroma; + struct init_int_and_frac h_init_lumabottom; + struct init_int_and_frac h_init_chromabottom; + struct init_int_and_frac v_init_lumabottom; + struct init_int_and_frac v_init_chromabottom; +}; + +enum lb_pixel_depth { + /* do not change the values because it is used as bit vector */ + LB_PIXEL_DEPTH_18BPP = 1, + LB_PIXEL_DEPTH_24BPP = 2, + LB_PIXEL_DEPTH_30BPP = 4, + LB_PIXEL_DEPTH_36BPP = 8 +}; + + +struct raw_gamma_ramp_rgb { + uint32_t red; + uint32_t green; + uint32_t blue; +}; + +enum raw_gamma_ramp_type { + GAMMA_RAMP_TYPE_UNINITIALIZED, + GAMMA_RAMP_TYPE_DEFAULT, + GAMMA_RAMP_TYPE_RGB256, + GAMMA_RAMP_TYPE_FIXED_POINT +}; + +#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256 +struct raw_gamma_ramp { + enum raw_gamma_ramp_type type; + struct raw_gamma_ramp_rgb rgb_256[NUM_OF_RAW_GAMMA_RAMP_RGB_256]; + uint32_t size; +}; + + +/* Colorimetry */ +enum colorimetry { + COLORIMETRY_NO_DATA = 0, + COLORIMETRY_ITU601 = 1, + COLORIMETRY_ITU709 = 2, + COLORIMETRY_EXTENDED = 3 +}; + +/* ColorimetryEx */ +enum colorimetry_ex { + COLORIMETRY_EX_XVYCC601 = 0, + COLORIMETRY_EX_XVYCC709 = 1, + COLORIMETRY_EX_SYCC601 = 2, + COLORIMETRY_EX_ADOBEYCC601 = 3, + COLORIMETRY_EX_ADOBERGB = 4, + COLORIMETRY_EX_RESERVED5 = 5, + COLORIMETRY_EX_RESERVED6 = 6, + COLORIMETRY_EX_RESERVED7 = 7 +}; + +enum ds_color_space { + DS_COLOR_SPACE_UNKNOWN = 0, + DS_COLOR_SPACE_SRGB_FULLRANGE = 1, + DS_COLOR_SPACE_SRGB_LIMITEDRANGE, + DS_COLOR_SPACE_YPBPR601, + DS_COLOR_SPACE_YPBPR709, + DS_COLOR_SPACE_YCBCR601, + DS_COLOR_SPACE_YCBCR709, + DS_COLOR_SPACE_NMVPU_SUPERAA, + DS_COLOR_SPACE_YCBCR601_YONLY, + DS_COLOR_SPACE_YCBCR709_YONLY/*same as YCbCr, but Y in Full range*/ +}; + + +enum active_format_info { + ACTIVE_FORMAT_NO_DATA = 0, + ACTIVE_FORMAT_VALID = 1 +}; + +/* Active format aspect ratio */ +enum active_format_aspect_ratio { + ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8, + ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9, + ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA, + ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB +}; + +enum bar_info { + BAR_INFO_NOT_VALID = 0, + BAR_INFO_VERTICAL_VALID = 1, + BAR_INFO_HORIZONTAL_VALID = 2, + BAR_INFO_BOTH_VALID = 3 +}; + +enum picture_scaling { + PICTURE_SCALING_UNIFORM = 0, + PICTURE_SCALING_HORIZONTAL = 1, + PICTURE_SCALING_VERTICAL = 2, + PICTURE_SCALING_BOTH = 3 +}; + +/* RGB quantization range */ +enum rgb_quantization_range { + RGB_QUANTIZATION_DEFAULT_RANGE = 0, + RGB_QUANTIZATION_LIMITED_RANGE = 1, + RGB_QUANTIZATION_FULL_RANGE = 2, + RGB_QUANTIZATION_RESERVED = 3 +}; + +/* YYC quantization range */ +enum yyc_quantization_range { + YYC_QUANTIZATION_LIMITED_RANGE = 0, + YYC_QUANTIZATION_FULL_RANGE = 1, + YYC_QUANTIZATION_RESERVED2 = 2, + YYC_QUANTIZATION_RESERVED3 = 3 +}; + +struct transform_funcs { + bool (*transform_power_up)(struct transform *xfm); + + bool (*transform_set_scaler)( + struct transform *xfm, + const struct scaler_data *data); + + void (*transform_set_scaler_bypass)(struct transform *xfm); + + bool (*transform_update_viewport)( + struct transform *xfm, + const struct rect *view_port, + bool is_fbc_attached); + + void (*transform_set_scaler_filter)( + struct transform *xfm, + struct scaler_filter *filter); + + void (*transform_set_gamut_remap)( + struct transform *xfm, + const struct grph_csc_adjustment *adjust); + + bool (*transform_set_pixel_storage_depth)( + struct transform *xfm, + enum lb_pixel_depth depth, + const struct bit_depth_reduction_params *bit_depth_params); + + bool (*transform_get_current_pixel_storage_depth)( + struct transform *xfm, + enum lb_pixel_depth *depth); +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/dc/irq_types.h b/drivers/gpu/drm/amd/dal/dc/irq_types.h new file mode 100644 index 000000000000..35a099166613 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/irq_types.h @@ -0,0 +1,199 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IRQ_TYPES_H__ +#define __DAL_IRQ_TYPES_H__ + +struct dc_context; + +typedef void (*interrupt_handler)(void *); + +typedef void *irq_handler_idx; +#define DAL_INVALID_IRQ_HANDLER_IDX NULL + + +/* The order of the IRQ sources is important and MUST match the one's +of base driver */ +enum dc_irq_source { + /* Use as mask to specify invalid irq source */ + DC_IRQ_SOURCE_INVALID = 0, + + DC_IRQ_SOURCE_HPD1, + DC_IRQ_SOURCE_HPD2, + DC_IRQ_SOURCE_HPD3, + DC_IRQ_SOURCE_HPD4, + DC_IRQ_SOURCE_HPD5, + DC_IRQ_SOURCE_HPD6, + + DC_IRQ_SOURCE_HPD1RX, + DC_IRQ_SOURCE_HPD2RX, + DC_IRQ_SOURCE_HPD3RX, + DC_IRQ_SOURCE_HPD4RX, + DC_IRQ_SOURCE_HPD5RX, + DC_IRQ_SOURCE_HPD6RX, + + DC_IRQ_SOURCE_I2C_DDC1, + DC_IRQ_SOURCE_I2C_DDC2, + DC_IRQ_SOURCE_I2C_DDC3, + DC_IRQ_SOURCE_I2C_DDC4, + DC_IRQ_SOURCE_I2C_DDC5, + DC_IRQ_SOURCE_I2C_DDC6, + + DC_IRQ_SOURCE_AZALIA0, + DC_IRQ_SOURCE_AZALIA1, + DC_IRQ_SOURCE_AZALIA2, + DC_IRQ_SOURCE_AZALIA3, + DC_IRQ_SOURCE_AZALIA4, + DC_IRQ_SOURCE_AZALIA5, + + DC_IRQ_SOURCE_DPSINK1, + DC_IRQ_SOURCE_DPSINK2, + DC_IRQ_SOURCE_DPSINK3, + DC_IRQ_SOURCE_DPSINK4, + DC_IRQ_SOURCE_DPSINK5, + DC_IRQ_SOURCE_DPSINK6, + + DC_IRQ_SOURCE_CRTC1VSYNC, + DC_IRQ_SOURCE_CRTC2VSYNC, + DC_IRQ_SOURCE_CRTC3VSYNC, + DC_IRQ_SOURCE_CRTC4VSYNC, + DC_IRQ_SOURCE_CRTC5VSYNC, + DC_IRQ_SOURCE_CRTC6VSYNC, + DC_IRQ_SOURCE_TIMER, + + DC_IRQ_SOURCE_PFLIP_FIRST, + DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST, + DC_IRQ_SOURCE_PFLIP2, + DC_IRQ_SOURCE_PFLIP3, + DC_IRQ_SOURCE_PFLIP4, + DC_IRQ_SOURCE_PFLIP5, + DC_IRQ_SOURCE_PFLIP6, + DC_IRQ_SOURCE_PFLIP_UNDERLAY0, + DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0, + + DC_IRQ_SOURCE_GPIOPAD0, + DC_IRQ_SOURCE_GPIOPAD1, + DC_IRQ_SOURCE_GPIOPAD2, + DC_IRQ_SOURCE_GPIOPAD3, + DC_IRQ_SOURCE_GPIOPAD4, + DC_IRQ_SOURCE_GPIOPAD5, + DC_IRQ_SOURCE_GPIOPAD6, + DC_IRQ_SOURCE_GPIOPAD7, + DC_IRQ_SOURCE_GPIOPAD8, + DC_IRQ_SOURCE_GPIOPAD9, + DC_IRQ_SOURCE_GPIOPAD10, + DC_IRQ_SOURCE_GPIOPAD11, + DC_IRQ_SOURCE_GPIOPAD12, + DC_IRQ_SOURCE_GPIOPAD13, + DC_IRQ_SOURCE_GPIOPAD14, + DC_IRQ_SOURCE_GPIOPAD15, + DC_IRQ_SOURCE_GPIOPAD16, + DC_IRQ_SOURCE_GPIOPAD17, + DC_IRQ_SOURCE_GPIOPAD18, + DC_IRQ_SOURCE_GPIOPAD19, + DC_IRQ_SOURCE_GPIOPAD20, + DC_IRQ_SOURCE_GPIOPAD21, + DC_IRQ_SOURCE_GPIOPAD22, + DC_IRQ_SOURCE_GPIOPAD23, + DC_IRQ_SOURCE_GPIOPAD24, + DC_IRQ_SOURCE_GPIOPAD25, + DC_IRQ_SOURCE_GPIOPAD26, + DC_IRQ_SOURCE_GPIOPAD27, + DC_IRQ_SOURCE_GPIOPAD28, + DC_IRQ_SOURCE_GPIOPAD29, + DC_IRQ_SOURCE_GPIOPAD30, + + DC_IRQ_SOURCE_DC1UNDERFLOW, + DC_IRQ_SOURCE_DC2UNDERFLOW, + DC_IRQ_SOURCE_DC3UNDERFLOW, + DC_IRQ_SOURCE_DC4UNDERFLOW, + DC_IRQ_SOURCE_DC5UNDERFLOW, + DC_IRQ_SOURCE_DC6UNDERFLOW, + + DC_IRQ_SOURCE_DMCU_SCP, + DC_IRQ_SOURCE_VBIOS_SW, + + DC_IRQ_SOURCE_VUPDATE1, + DC_IRQ_SOURCE_VUPDATE2, + DC_IRQ_SOURCE_VUPDATE3, + DC_IRQ_SOURCE_VUPDATE4, + DC_IRQ_SOURCE_VUPDATE5, + DC_IRQ_SOURCE_VUPDATE6, + + DAL_IRQ_SOURCES_NUMBER +}; + +enum irq_type +{ + IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1, + IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1, +}; + +#define DAL_VALID_IRQ_SRC_NUM(src) \ + ((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID) + +/* Number of Page Flip IRQ Sources. */ +#define DAL_PFLIP_IRQ_SRC_NUM \ + (DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1) + +/* the number of contexts may be expanded in the future based on needs */ +enum dc_interrupt_context { + INTERRUPT_LOW_IRQ_CONTEXT = 0, + INTERRUPT_HIGH_IRQ_CONTEXT, + INTERRUPT_CONTEXT_NUMBER +}; + +enum dc_interrupt_porlarity { + INTERRUPT_POLARITY_DEFAULT = 0, + INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT, + INTERRUPT_POLARITY_HIGH, + INTERRUPT_POLARITY_BOTH +}; + +#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \ + (int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \ + (int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \ + (int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid" + +struct dc_timer_interrupt_params { + uint32_t micro_sec_interval; + enum dc_interrupt_context int_context; +}; + +struct dc_interrupt_params { + /* The polarity *change* which will trigger an interrupt. + * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then + * 'current_polarity' must be initialised. */ + enum dc_interrupt_porlarity requested_polarity; + /* If 'requested_polarity == INTERRUPT_POLARITY_BOTH', + * 'current_polarity' should contain the current state, which means + * the interrupt will be triggered when state changes from what is, + * in 'current_polarity'. */ + enum dc_interrupt_porlarity current_polarity; + enum dc_irq_source irq_source; + enum dc_interrupt_context int_context; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h new file mode 100644 index 000000000000..8ebbe650c124 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h @@ -0,0 +1,632 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_ADAPTER_SERVICE_INTERFACE_H__ +#define __DAL_ADAPTER_SERVICE_INTERFACE_H__ + +#include "grph_object_ctrl_defs.h" +#include "gpio_interface.h" +#include "ddc_interface.h" +#include "irq_interface.h" +#include "bios_parser_interface.h" +#include "adapter_service_types.h" +#include "dal_types.h" +#include "asic_capability_types.h" + +/* forward declaration */ +struct i2caux; +struct adapter_service; + + +/* + * enum adapter_feature_id + * + * Definition of all adapter features + * + * The enumeration defines the IDs of all the adapter features. The enum + * organizes all the features into several feature sets. The range of feature + * set N is from ((N-1)*32+1) to (N*32). Because there may be three value-type + * feature, boolean-type, unsigned char-type and unsinged int-type, the number + * of features should be 32, 4 and 1 in the feature set accordingly. + * + * In a boolean-type feature set N, the enumeration value of the feature should + * be ((N-1)*32+1), ((N-1)*32+2), ..., (N*32). + * + * In an unsigned char-type feature set N, the enumeration value of the + * feature should be ((N-1)*32+1), ((N-1)*32+8), ((N-1)*32+16) and (N*32). + * + * In an unsigned int-type feature set N, the enumeration value of the feature + * should be ((N-1)*32+1) + */ +enum adapter_feature_id { + FEATURE_UNKNOWN = 0, + + /* Boolean set, up to 32 entries */ + FEATURE_ENABLE_HW_EDID_POLLING = 1, + FEATURE_SET_01_START = FEATURE_ENABLE_HW_EDID_POLLING, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN, + FEATURE_UNDERFLOW_INTERRUPT, + FEATURE_ALLOW_WATERMARK_ADJUSTMENT, + FEATURE_LIGHT_SLEEP, + FEATURE_DCP_DITHER_FRAME_RANDOM_ENABLE, + FEATURE_DCP_DITHER_RGB_RANDOM_ENABLE, + FEATURE_DCP_DITHER_HIGH_PASS_RANDOM_ENABLE, + FEATURE_DETECT_REQUIRE_HPD_HIGH, + FEATURE_LINE_BUFFER_ENHANCED_PIXEL_DEPTH, /* 10th */ + FEATURE_MAXIMIZE_URGENCY_WATERMARKS, + FEATURE_MAXIMIZE_STUTTER_MARKS, + FEATURE_MAXIMIZE_NBP_MARKS, + FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, + FEATURE_USE_MAX_DISPLAY_CLK, + FEATURE_ALLOW_EDP_RESOURCE_SHARING, + FEATURE_SUPPORT_DP_YUV, + FEATURE_SUPPORT_DP_Y_ONLY, + FEATURE_DISABLE_DP_GTC_SYNC, + FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, /* 20th */ + FEATURE_ENABLE_DFS_BYPASS, + FEATURE_LB_HIGH_RESOLUTION, + FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, + FEATURE_REPORT_CE_MODE_ONLY, + FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, + FEATURE_DDC_READ_FORCE_REPEATED_START, + FEATURE_FORCE_TIMING_RESYNC, + FEATURE_TMDS_DISABLE_DITHERING, + FEATURE_HDMI_DISABLE_DITHERING, + FEATURE_DP_DISABLE_DITHERING, /* 30th */ + FEATURE_EMBEDDED_DISABLE_DITHERING, + FEATURE_DISABLE_AZ_CLOCK_GATING, /* 32th. This set is full */ + FEATURE_SET_01_END = FEATURE_SET_01_START + 31, + + /* Boolean set, up to 32 entries */ + FEATURE_WIRELESS_ENABLE = FEATURE_SET_01_END + 1, + FEATURE_SET_02_START = FEATURE_WIRELESS_ENABLE, + FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, + FEATURE_WIRELESS_LIMIT_720P, + FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO, + FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS, + FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, + FEATURE_ALLOW_SELF_REFRESH, + FEATURE_ALLOW_DYNAMIC_PIXEL_ENCODING_CHANGE, + FEATURE_ALLOW_HSYNC_VSYNC_ADJUSTMENT, + FEATURE_FORCE_PSR, /* 10th */ + FEATURE_PREFER_3D_TIMING, + FEATURE_VARI_BRIGHT_ENABLE, + FEATURE_PSR_ENABLE, + FEATURE_EDID_STRESS_READ, + FEATURE_DP_FRAME_PACK_STEREO3D, + FEATURE_ALLOW_HDMI_WITHOUT_AUDIO, + FEATURE_RESTORE_USAGE_I2C_SW_ENGING, + FEATURE_ABM_2_0, + FEATURE_SUPPORT_MIRABILIS, + FEATURE_LOAD_DMCU_FIRMWARE, /* 20th */ + FEATURE_ENABLE_GPU_SCALING, + FEATURE_DONGLE_SINK_COUNT_CHECK, + FEATURE_INSTANT_UP_SCALE_DOWN_SCALE, + FEATURE_TILED_DISPLAY, + FEATURE_CHANGE_I2C_SPEED_CONTROL, + FEATURE_REPORT_SINGLE_SELECTED_TIMING, + FEATURE_ALLOW_HDMI_HIGH_CLK_DP_DONGLE, + FEATURE_SUPPORT_EXTERNAL_PANEL_DRR, + FEATURE_SUPPORT_SMOOTH_BRIGHTNESS, + FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, /* 30th */ + FEATURE_POWER_GATING_LB_PORTION, /* 31nd. One more left. */ + FEATURE_SET_02_END = FEATURE_SET_02_START + 31, + + /* UInt set, 1 entry: DCP Bit Depth Reduction Mode */ + FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE = FEATURE_SET_02_END + 1, + FEATURE_SET_03_START = FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, + FEATURE_SET_03_END = FEATURE_SET_03_START + 31, + + /* UInt set, 1 entry: DCP Dither Mode */ + FEATURE_DCP_DITHER_MODE = FEATURE_SET_03_END + 1, + FEATURE_SET_04_START = FEATURE_DCP_DITHER_MODE, + FEATURE_SET_04_END = FEATURE_SET_04_START + 31, + + /* UInt set, 1 entry: DCP Programming WA(workaround) */ + FEATURE_DCP_PROGRAMMING_WA = FEATURE_SET_04_END + 1, + FEATURE_SET_06_START = FEATURE_DCP_PROGRAMMING_WA, + FEATURE_SET_06_END = FEATURE_SET_06_START + 31, + + /* UInt set, 1 entry: Maximum co-functional non-DP displays */ + FEATURE_MAX_COFUNC_NON_DP_DISPLAYS = FEATURE_SET_06_END + 1, + FEATURE_SET_07_START = FEATURE_MAX_COFUNC_NON_DP_DISPLAYS, + FEATURE_SET_07_END = FEATURE_SET_07_START + 31, + + /* UInt set, 1 entry: Number of supported HDMI connection */ + FEATURE_SUPPORTED_HDMI_CONNECTION_NUM = FEATURE_SET_07_END + 1, + FEATURE_SET_08_START = FEATURE_SUPPORTED_HDMI_CONNECTION_NUM, + FEATURE_SET_08_END = FEATURE_SET_08_START + 31, + + /* UInt set, 1 entry: Maximum number of controllers */ + FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_08_END + 1, + FEATURE_SET_09_START = FEATURE_MAX_CONTROLLER_NUM, + FEATURE_SET_09_END = FEATURE_SET_09_START + 31, + + /* UInt set, 1 entry: Type of DRR support */ + FEATURE_DRR_SUPPORT = FEATURE_SET_09_END + 1, + FEATURE_SET_10_START = FEATURE_DRR_SUPPORT, + FEATURE_SET_10_END = FEATURE_SET_10_START + 31, + + /* UInt set, 1 entry: Stutter mode support */ + FEATURE_STUTTER_MODE = FEATURE_SET_10_END + 1, + FEATURE_SET_11_START = FEATURE_STUTTER_MODE, + FEATURE_SET_11_END = FEATURE_SET_11_START + 31, + + /* UInt set, 1 entry: Measure PSR setup time */ + FEATURE_PSR_SETUP_TIME_TEST = FEATURE_SET_11_END + 1, + FEATURE_SET_12_START = FEATURE_PSR_SETUP_TIME_TEST, + FEATURE_SET_12_END = FEATURE_SET_12_START + 31, + + /* Boolean set, up to 32 entries */ + FEATURE_POWER_GATING_PIPE_IN_TILE = FEATURE_SET_12_END + 1, + FEATURE_SET_13_START = FEATURE_POWER_GATING_PIPE_IN_TILE, + FEATURE_USE_PPLIB, + FEATURE_DISABLE_LPT_SUPPORT, + FEATURE_DUMMY_FBC_BACKEND, + FEATURE_DISABLE_FBC_COMP_CLK_GATE, + FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL, + FEATURE_PIXEL_PERFECT_OUTPUT, + FEATURE_8BPP_SUPPORTED, + FEATURE_SET_13_END = FEATURE_SET_13_START + 31, + + /* UInt set, 1 entry: Display preferred view + * 0: no preferred view + * 1: native and preferred timing of embedded display will have high + * priority, so other displays will support it always + */ + FEATURE_DISPLAY_PREFERRED_VIEW = FEATURE_SET_13_END + 1, + FEATURE_SET_15_START = FEATURE_DISPLAY_PREFERRED_VIEW, + FEATURE_SET_15_END = FEATURE_SET_15_START + 31, + + /* UInt set, 1 entry: DAL optimization */ + FEATURE_OPTIMIZATION = FEATURE_SET_15_END + 1, + FEATURE_SET_16_START = FEATURE_OPTIMIZATION, + FEATURE_SET_16_END = FEATURE_SET_16_START + 31, + + /* UInt set, 1 entry: Performance measurement */ + FEATURE_PERF_MEASURE = FEATURE_SET_16_END + 1, + FEATURE_SET_17_START = FEATURE_PERF_MEASURE, + FEATURE_SET_17_END = FEATURE_SET_17_START + 31, + + /* UInt set, 1 entry: Minimum backlight value [0-255] */ + FEATURE_MIN_BACKLIGHT_LEVEL = FEATURE_SET_17_END + 1, + FEATURE_SET_18_START = FEATURE_MIN_BACKLIGHT_LEVEL, + FEATURE_SET_18_END = FEATURE_SET_18_START + 31, + + /* UInt set, 1 entry: Maximum backlight value [0-255] */ + FEATURE_MAX_BACKLIGHT_LEVEL = FEATURE_SET_18_END + 1, + FEATURE_SET_19_START = FEATURE_MAX_BACKLIGHT_LEVEL, + FEATURE_SET_19_END = FEATURE_SET_19_START + 31, + + /* UInt set, 1 entry: AMB setting + * + * Each byte will control the ABM configuration to use for a specific + * ABM level. + * + * HW team provided 12 different ABM min/max reduction pairs to choose + * between for each ABM level. + * + * ABM level Byte Setting + * 1 0 Default = 0 (setting 3), can be override to 1-12 + * 2 1 Default = 0 (setting 7), can be override to 1-12 + * 3 2 Default = 0 (setting 8), can be override to 1-12 + * 4 3 Default = 0 (setting 10), can be override to 1-12 + * + * For example, + * FEATURE_PREFERRED_ABM_CONFIG_SET = 0x0C060500, this represents: + * ABM level 1 use default setting (setting 3) + * ABM level 2 uses setting 5 + * ABM level 3 uses setting 6 + * ABM level 4 uses setting 12 + * Internal use only! + */ + FEATURE_PREFERRED_ABM_CONFIG_SET = FEATURE_SET_19_END + 1, + FEATURE_SET_20_START = FEATURE_PREFERRED_ABM_CONFIG_SET, + FEATURE_SET_20_END = FEATURE_SET_20_START + 31, + + /* UInt set, 1 entry: Change SW I2C speed */ + FEATURE_CHANGE_SW_I2C_SPEED = FEATURE_SET_20_END + 1, + FEATURE_SET_21_START = FEATURE_CHANGE_SW_I2C_SPEED, + FEATURE_SET_21_END = FEATURE_SET_21_START + 31, + + /* UInt set, 1 entry: Change HW I2C speed */ + FEATURE_CHANGE_HW_I2C_SPEED = FEATURE_SET_21_END + 1, + FEATURE_SET_22_START = FEATURE_CHANGE_HW_I2C_SPEED, + FEATURE_SET_22_END = FEATURE_SET_22_START + 31, + + /* UInt set, 1 entry: + * When PSR issue occurs, it is sometimes hard to debug since the + * failure occurs immediately at boot. Use this setting to skip or + * postpone PSR functionality and re-enable through DSAT. */ + FEATURE_DEFAULT_PSR_LEVEL = FEATURE_SET_22_END + 1, + FEATURE_SET_23_START = FEATURE_DEFAULT_PSR_LEVEL, + FEATURE_SET_23_END = FEATURE_SET_23_START + 31, + + /* UInt set, 1 entry: Allowed pixel clock range for LVDS */ + FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE = FEATURE_SET_23_END + 1, + FEATURE_SET_24_START = FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE, + FEATURE_SET_24_END = FEATURE_SET_24_START + 31, + + /* UInt set, 1 entry: Max number of clock sources */ + FEATURE_MAX_CLOCK_SOURCE_NUM = FEATURE_SET_24_END + 1, + FEATURE_SET_25_START = FEATURE_MAX_CLOCK_SOURCE_NUM, + FEATURE_SET_25_END = FEATURE_SET_25_START + 31, + + /* UInt set, 1 entry: Select the ABM configuration to use. + * + * This feature set is used to allow packaging option to be defined + * to allow OEM to select between the default ABM configuration or + * alternative predefined configurations that may be more aggressive. + * + * Note that this regkey is meant for external use to select the + * configuration OEM wants. Whereas the other PREFERRED_ABM_CONFIG_SET + * key is only used for internal use and allows full reconfiguration. + */ + FEATURE_ABM_CONFIG = FEATURE_SET_25_END + 1, + FEATURE_SET_26_START = FEATURE_ABM_CONFIG, + FEATURE_SET_26_END = FEATURE_SET_26_START + 31, + + /* UInt set, 1 entry: Select the default speed in which smooth + * brightness feature should converge towards target backlight level. + * + * For example, a setting of 500 means it takes 500ms to transition + * from current backlight level to the new requested backlight level. + */ + FEATURE_SMOOTH_BRTN_ADJ_TIME_IN_MS = FEATURE_SET_26_END + 1, + FEATURE_SET_27_START = FEATURE_SMOOTH_BRTN_ADJ_TIME_IN_MS, + FEATURE_SET_27_END = FEATURE_SET_27_START + 31, + + /* Set 28: UInt set, 1 entry: Allow runtime parameter to force specific + * Static Screen Event triggers for test purposes. */ + FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS = FEATURE_SET_27_END + 1, + FEATURE_SET_28_START = FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS, + FEATURE_SET_28_END = FEATURE_SET_28_START + 31, + + FEATURE_MAXIMUM +}; + +/* Adapter Service type of DRR support*/ +enum as_drr_support { + AS_DRR_SUPPORT_DISABLED = 0x0, + AS_DRR_SUPPORT_ENABLED = 0x1, + AS_DRR_SUPPORT_MIN_FORCED_FPS = 0xA +}; + +/* Adapter service initialize data structure*/ +struct as_init_data { + struct hw_asic_id hw_init_data; + struct bp_init_data bp_init_data; + struct dc_context *ctx; + struct bdf_info bdf_info; + const struct dal_override_parameters *display_param; + struct dc_bios *vbios_override; + enum dce_environment dce_environment; +}; + +/* Create adapter service */ +struct adapter_service *dal_adapter_service_create( + struct as_init_data *init_data); + +/* Destroy adapter service and objects it contains */ +void dal_adapter_service_destroy( + struct adapter_service **as); + +/* Get the DCE version of current ASIC */ +enum dce_version dal_adapter_service_get_dce_version( + const struct adapter_service *as); + +enum dce_environment dal_adapter_service_get_dce_environment( + const struct adapter_service *as); + +/* Get firmware information from BIOS */ +bool dal_adapter_service_get_firmware_info( + struct adapter_service *as, + struct firmware_info *info); + + +/* functions to get a total number of objects of specific type */ +uint8_t dal_adapter_service_get_connectors_num( + struct adapter_service *as); + +/* Get number of controllers */ +uint8_t dal_adapter_service_get_controllers_num( + struct adapter_service *as); + +/* Get number of clock sources */ +uint8_t dal_adapter_service_get_clock_sources_num( + struct adapter_service *as); + +/* Get number of controllers */ +uint8_t dal_adapter_service_get_func_controllers_num( + struct adapter_service *as); + +/* Get number of stream engines */ +uint8_t dal_adapter_service_get_stream_engines_num( + struct adapter_service *as); + +/* functions to get object id based on object index */ +struct graphics_object_id dal_adapter_service_get_connector_obj_id( + struct adapter_service *as, + uint8_t connector_index); + +/* Get number of spread spectrum entries from BIOS */ +uint32_t dal_adapter_service_get_ss_info_num( + struct adapter_service *as, + enum as_signal_type signal); + +/* Get spread spectrum info from BIOS */ +bool dal_adapter_service_get_ss_info( + struct adapter_service *as, + enum as_signal_type signal, + uint32_t idx, + struct spread_spectrum_info *info); + +/* Check if DFS bypass is enabled */ +bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as); + +/* Get memory controller latency */ +uint32_t dal_adapter_service_get_mc_latency( + struct adapter_service *as); + +/* Get the video RAM bit width set on the ASIC */ +uint32_t dal_adapter_service_get_asic_vram_bit_width( + struct adapter_service *as); + +/* Get the bug flags set on this ASIC */ +struct asic_bugs dal_adapter_service_get_asic_bugs( + struct adapter_service *as); + +/* Get efficiency of DRAM */ +uint32_t dal_adapter_service_get_dram_bandwidth_efficiency( + struct adapter_service *as); + +/* Get multiplier for the memory type */ +uint32_t dal_adapter_service_get_memory_type_multiplier( + struct adapter_service *as); + +/* Get parameters for bandwidth tuning */ +bool dal_adapter_service_get_bandwidth_tuning_params( + struct adapter_service *as, + union bandwidth_tuning_params *params); + +/* Get integrated information on BIOS */ +bool dal_adapter_service_get_integrated_info( + struct adapter_service *as, + struct integrated_info *info); + +/* Return if a given feature is supported by the ASIC */ +bool dal_adapter_service_is_feature_supported( + enum adapter_feature_id feature_id); + +/* Get the cached value of a given feature */ +bool dal_adapter_service_get_feature_value( + const enum adapter_feature_id feature_id, + void *data, + uint32_t size); + +/* Get a copy of ASIC feature flags */ +struct asic_feature_flags dal_adapter_service_get_feature_flags( + struct adapter_service *as); + +/* Obtain DDC */ +struct ddc *dal_adapter_service_obtain_ddc( + struct adapter_service *as, + struct graphics_object_id id); + +/* Release DDC */ +void dal_adapter_service_release_ddc( + struct adapter_service *as, + struct ddc *ddc); + +/* Obtain HPD interrupt request */ +struct irq *dal_adapter_service_obtain_hpd_irq( + struct adapter_service *as, + struct graphics_object_id id); + +/* Release interrupt request */ +void dal_adapter_service_release_irq( + struct adapter_service *as, + struct irq *irq); + +/* Obtain GPIO */ +struct gpio *dal_adapter_service_obtain_gpio( + struct adapter_service *as, + enum gpio_id id, + uint32_t en); + +/* Obtain GPIO for stereo3D*/ +struct gpio *dal_adapter_service_obtain_stereo_gpio(struct adapter_service *as); + +/* Release GPIO */ +void dal_adapter_service_release_gpio( + struct adapter_service *as, + struct gpio *gpio); + +/* Get SW I2C speed */ +uint32_t dal_adapter_service_get_sw_i2c_speed(struct adapter_service *as); + +/* Get HW I2C speed */ +uint32_t dal_adapter_service_get_hw_i2c_speed(struct adapter_service *as); + +/* Get line buffer size */ +uint32_t dal_adapter_service_get_line_buffer_size(struct adapter_service *as); + +/* Get information on audio support */ +union audio_support dal_adapter_service_get_audio_support( + struct adapter_service *as); + +/* Get I2C information from BIOS */ +bool dal_adapter_service_get_i2c_info( + struct adapter_service *as, + struct graphics_object_id id, + struct graphics_object_i2c_info *i2c_info); + +/* Get bios parser handler */ +struct dc_bios *dal_adapter_service_get_bios_parser( + struct adapter_service *as); + +/* Get i2c aux handler */ +struct i2caux *dal_adapter_service_get_i2caux( + struct adapter_service *as); + +struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags( + struct adapter_service *as); + +bool dal_adapter_service_initialize_hw_data( + struct adapter_service *as); + +struct graphics_object_id dal_adapter_service_enum_fake_path_resource( + struct adapter_service *as, + uint32_t index); + +struct graphics_object_id dal_adapter_service_enum_stereo_sync_object( + struct adapter_service *as, + uint32_t index); + +struct graphics_object_id dal_adapter_service_enum_sync_output_object( + struct adapter_service *as, + uint32_t index); + +struct graphics_object_id dal_adapter_service_enum_audio_object( + struct adapter_service *as, + uint32_t index); + +void dal_adapter_service_update_audio_connectivity( + struct adapter_service *as, + uint32_t number_of_audio_capable_display_path); + +bool dal_adapter_service_has_embedded_display_connector( + struct adapter_service *as); + +bool dal_adapter_service_get_embedded_panel_info( + struct adapter_service *as, + struct embedded_panel_info *info); + +bool dal_adapter_service_enum_embedded_panel_patch_mode( + struct adapter_service *as, + uint32_t index, + struct embedded_panel_patch_mode *mode); + +bool dal_adapter_service_get_faked_edid_len( + struct adapter_service *as, + uint32_t *len); + +bool dal_adapter_service_get_faked_edid_buf( + struct adapter_service *as, + uint8_t *buf, + uint32_t len); + +uint32_t dal_adapter_service_get_max_cofunc_non_dp_displays(void); + +uint32_t dal_adapter_service_get_single_selected_timing_signals(void); + +bool dal_adapter_service_get_device_tag( + struct adapter_service *as, + struct graphics_object_id connector_object_id, + uint32_t device_tag_index, + struct connector_device_tag_info *info); + +bool dal_adapter_service_is_device_id_supported( + struct adapter_service *as, + struct device_id id); + +bool dal_adapter_service_is_meet_underscan_req(struct adapter_service *as); + +bool dal_adapter_service_underscan_for_hdmi_only(struct adapter_service *as); + +uint32_t dal_adapter_service_get_src_num( + struct adapter_service *as, + struct graphics_object_id id); + +struct graphics_object_id dal_adapter_service_get_src_obj( + struct adapter_service *as, + struct graphics_object_id id, + uint32_t index); + +/* Is this Fusion ASIC */ +bool dal_adapter_service_is_fusion(struct adapter_service *as); + +/* Is this ASIC support dynamic DFSbypass switch */ +bool dal_adapter_service_is_dfsbyass_dynamic(struct adapter_service *as); + +/* Reports whether driver settings allow requested optimization */ +bool dal_adapter_service_should_optimize( + struct adapter_service *as, enum optimization_feature feature); + +/* Determine if driver is in accelerated mode */ +bool dal_adapter_service_is_in_accelerated_mode(struct adapter_service *as); + +struct ddc *dal_adapter_service_obtain_ddc_from_i2c_info( + struct adapter_service *as, + struct graphics_object_i2c_info *info); + +struct bdf_info dal_adapter_service_get_adapter_info( + struct adapter_service *as); + + +/* Determine if this ASIC needs to wait on PLL lock bit */ +bool dal_adapter_service_should_psr_skip_wait_for_pll_lock( + struct adapter_service *as); + +#define SIZEOF_BACKLIGHT_LUT 101 +#define ABSOLUTE_BACKLIGHT_MAX 255 +#define DEFAULT_MIN_BACKLIGHT 12 +#define DEFAULT_MAX_BACKLIGHT 255 +#define BACKLIGHT_CURVE_COEFFB 100 +#define BACKLIGHT_CURVE_COEFFA_FACTOR 10000 +#define BACKLIGHT_CURVE_COEFFB_FACTOR 100 + +struct panel_backlight_levels { + uint32_t ac_level_percentage; + uint32_t dc_level_percentage; +}; + +bool dal_adapter_service_is_lid_open(struct adapter_service *as); + +bool dal_adapter_service_get_panel_backlight_default_levels( + struct adapter_service *as, + struct panel_backlight_levels *levels); + +bool dal_adapter_service_get_panel_backlight_boundaries( + struct adapter_service *as, + struct panel_backlight_boundaries *boundaries); + +uint32_t dal_adapter_service_get_view_port_pixel_granularity( + struct adapter_service *as); + +uint32_t dal_adapter_service_get_num_of_path_per_dp_mst_connector( + struct adapter_service *as); + +uint32_t dal_adapter_service_get_num_of_underlays( + struct adapter_service *as); + +bool dal_adapter_service_get_encoder_cap_info( + struct adapter_service *as, + struct graphics_object_id id, + struct graphics_object_encoder_cap_info *info); + +bool dal_adapter_service_is_mc_tuning_req(struct adapter_service *as); + +#endif /* __DAL_ADAPTER_SERVICE_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_types.h b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h new file mode 100644 index 000000000000..4cb4b4b6eeed --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/adapter_service_types.h @@ -0,0 +1,71 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_ADAPTER_SERVICE_TYPES_H__ +#define __DAL_ADAPTER_SERVICE_TYPES_H__ + +/* TODO: include signal_types.h and remove this enum */ +enum as_signal_type { + AS_SIGNAL_TYPE_NONE = 0L, /* no signal */ + AS_SIGNAL_TYPE_DVI, + AS_SIGNAL_TYPE_HDMI, + AS_SIGNAL_TYPE_LVDS, + AS_SIGNAL_TYPE_DISPLAY_PORT, + AS_SIGNAL_TYPE_GPU_PLL, + AS_SIGNAL_TYPE_UNKNOWN +}; + +/* + * Struct used for algorithm of Bandwidth tuning parameters + * the sequence of the fields is binded with runtime parameter. + */ +union bandwidth_tuning_params { + struct bandwidth_tuning_params_struct { + uint32_t read_delay_stutter_off_usec; + uint32_t ignore_hblank_time;/*bool*/ + uint32_t extra_reordering_latency_usec; + uint32_t extra_mc_latency_usec; + uint32_t data_return_bandwidth_eff;/*in %*/ + uint32_t dmif_request_bandwidth_eff;/*in %*/ + uint32_t sclock_latency_multiplier;/*in unit of 0.01*/ + uint32_t mclock_latency_multiplier;/*in unit of 0.01*/ + uint32_t fix_latency_multiplier;/*in unit of 0.01*/ + /*in unit represent in watermark*/ + uint32_t use_urgency_watermark_offset; + } tuning_info; + uint32_t arr_info[sizeof(struct bandwidth_tuning_params_struct) + / sizeof(uint32_t)]; +}; + +union audio_support { + struct { + uint32_t DP_AUDIO:1; + uint32_t HDMI_AUDIO_ON_DONGLE:1; + uint32_t HDMI_AUDIO_NATIVE:1; + } bits; + uint32_t raw; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h new file mode 100644 index 000000000000..bdeaaf9066a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h @@ -0,0 +1,58 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of enc software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and enc permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_ASIC_CAPABILITY_INTERFACE_H__ +#define __DAL_ASIC_CAPABILITY_INTERFACE_H__ + +/* Include */ +#include "include/asic_capability_types.h" + +/* Forward declaration */ +struct hw_asic_id; + + +/* ASIC capability */ +struct asic_capability { + struct dc_context *ctx; + struct asic_caps caps; + struct asic_stereo_3d_caps stereo_3d_caps; + struct asic_bugs bugs; + struct dal_asic_runtime_flags runtime_flags; + uint32_t data[ASIC_DATA_MAX_NUMBER]; +}; + + +/** + * Interfaces + */ + +/* Create and initialize ASIC capability */ +struct asic_capability *dal_asic_capability_create(struct hw_asic_id *init, + struct dc_context *ctx); + +/* Destroy ASIC capability and free memory space */ +void dal_asic_capability_destroy(struct asic_capability **cap); + +#endif /* __DAL_ASIC_CAPABILITY_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h new file mode 100644 index 000000000000..1cb977618bdf --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h @@ -0,0 +1,134 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_ASIC_CAPABILITY_TYPES_H__ +#define __DAL_ASIC_CAPABILITY_TYPES_H__ + +/* + * ASIC Capabilities + */ +struct asic_caps { + bool CONSUMER_SINGLE_SELECTED_TIMING:1; + bool UNDERSCAN_ADJUST:1; + bool DELTA_SIGMA_SUPPORT:1; + bool PANEL_SELF_REFRESH_SUPPORTED:1; + bool IS_FUSION:1; + bool DP_MST_SUPPORTED:1; + bool UNDERSCAN_FOR_HDMI_ONLY:1; + bool DVI_CLOCK_SHARE_CAPABILITY:1; + bool SUPPORT_CEA861E_FINAL:1; + bool MIRABILIS_SUPPORTED:1; + bool MIRABILIS_ENABLED_BY_DEFAULT:1; + bool DEVICE_TAG_REMAP_SUPPORTED:1; + bool HEADLESS_NO_OPM_SUPPORTED:1; + bool WIRELESS_LIMIT_TO_720P:1; + bool WIRELESS_FULL_TIMING_ADJUSTMENT:1; + bool WIRELESS_TIMING_ADJUSTMENT:1; + bool WIRELESS_COMPRESSED_AUDIO:1; + bool VCE_SUPPORTED:1; + bool HPD_CHECK_FOR_EDID:1; + bool NO_VCC_OFF_HPD_POLLING:1; + bool NEED_MC_TUNING:1; + bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1; + bool DFSBYPASS_DYNAMIC_SUPPORT:1; + bool SUPPORT_8BPP:1; +}; + + +/* + * ASIC Stereo 3D Caps + */ +struct asic_stereo_3d_caps { + bool SUPPORTED:1; + bool DISPLAY_BASED_ON_WS:1; + bool HDMI_FRAME_PACK:1; + bool INTERLACE_FRAME_PACK:1; + bool DISPLAYPORT_FRAME_PACK:1; + bool DISPLAYPORT_FRAME_ALT:1; + bool INTERLEAVE:1; +}; + + +/* + * ASIC Bugs + */ +struct asic_bugs { + bool MST_SYMBOL_MISALIGNMENT:1; + bool PSR_2X_LANE_GANGING:1; + bool LB_WA_IS_SUPPORTED:1; + bool ROM_REGISTER_ACCESS:1; + bool PSR_WA_OVERSCAN_CRC_ERROR:1; +}; + + +/* + * ASIC Data + */ +enum asic_data { + ASIC_DATA_FIRST = 0, + ASIC_DATA_CONTROLLERS_NUM = ASIC_DATA_FIRST, + ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM, + ASIC_DATA_DCE_VERSION, + ASIC_DATA_DCE_VERSION_MINOR, + ASIC_DATA_VRAM_TYPE, + ASIC_DATA_VRAM_BITWIDTH, + ASIC_DATA_FEATURE_FLAGS, + ASIC_DATA_LINEBUFFER_NUM, + ASIC_DATA_LINEBUFFER_SIZE, + ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY, + ASIC_DATA_MC_LATENCY, + ASIC_DATA_MC_LATENCY_SLOW, + ASIC_DATA_CLOCKSOURCES_NUM, + ASIC_DATA_MEMORYTYPE_MULTIPLIER, + ASIC_DATA_STUTTERMODE, + ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR, + ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS, + ASIC_DATA_REVISION_ID, + ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE, + ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY, + ASIC_DATA_DIGFE_NUM, + ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM, + ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN, + ASIC_DATA_NUM_OF_VIDEO_PLANES, + ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ, + ASIC_DATA_MAX_NUMBER /* end of enum */ +}; + + +/* + * ASIC Feature Flags + */ +struct asic_feature_flags { + union { + uint32_t raw; + struct { + uint32_t LEGACY_CLIENT:1; + uint32_t PACKED_PIXEL_FORMAT:1; + uint32_t WORKSTATION_STEREO:1; + uint32_t WORKSTATION:1; + } bits; + }; +}; + +#endif /* __DAL_ASIC_CAPABILITY_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/audio_interface.h b/drivers/gpu/drm/amd/dal/include/audio_interface.h new file mode 100644 index 000000000000..bf2176279f0e --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/audio_interface.h @@ -0,0 +1,184 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_AUDIO_INTERFACE_H__ +#define __DAL_AUDIO_INTERFACE_H__ + +#include "audio_types.h" +#include "adapter_service_interface.h" +#include "signal_types.h" +#include "link_service_types.h" + +/* forward declaration */ +struct audio; +struct dal_adapter_service; + +/***** audio initialization data *****/ +/* + * by audio, it means audio endpoint id. ASIC may have many endpoints. + * upper sw layer will create one audio object instance for each endpoints. + * ASIC support internal audio only. So enum number is used to differ + * each endpoint + */ +struct audio_init_data { + struct adapter_service *as; + struct graphics_object_id audio_stream_id; + struct dc_context *ctx; +}; + +enum audio_result { + AUDIO_RESULT_OK, + AUDIO_RESULT_ERROR, +}; + +/****** audio object create, destroy ******/ +struct audio *dal_audio_create( + const struct audio_init_data *init_data); + +void dal_audio_destroy( + struct audio **audio); + +/****** graphics object interface ******/ +const struct graphics_object_id dal_audio_get_graphics_object_id( + const struct audio *audio); + +/* Enumerate Graphics Object supported Input/Output Signal Types */ +uint32_t dal_audio_enumerate_input_signals( + struct audio *audio); + +uint32_t dal_audio_enumerate_output_signals( + struct audio *audio); + +/* Check if signal supported by GraphicsObject */ +bool dal_audio_is_input_signal_supported( + struct audio *audio, + enum signal_type signal); + +bool dal_audio_is_output_signal_supported( + struct audio *audio, + enum signal_type signal); + + +/***** programming interface *****/ + +/* perform power up sequence (boot up, resume, recovery) */ +enum audio_result dal_audio_power_up( + struct audio *audio); + +/* perform power down (shut down, stand by) */ +enum audio_result dal_audio_power_down( + struct audio *audio); + +/* setup audio */ +enum audio_result dal_audio_setup( + struct audio *audio, + struct audio_output *output, + struct audio_info *info); + +/* enable audio */ +enum audio_result dal_audio_enable_output( + struct audio *audio, + enum engine_id engine_id, + enum signal_type signal); + +/* disable audio */ +enum audio_result dal_audio_disable_output( + struct audio *audio, + enum engine_id engine_id, + enum signal_type signal); + +/* enable azalia audio endpoint */ +enum audio_result dal_audio_enable_azalia_audio_jack_presence( + struct audio *audio, + enum engine_id engine_id); + +/* disable azalia audio endpoint */ +enum audio_result dal_audio_disable_azalia_audio_jack_presence( + struct audio *audio, + enum engine_id engine_id); + +/* unmute audio */ +enum audio_result dal_audio_unmute( + struct audio *audio, + enum engine_id engine_id, + enum signal_type signal); + +/* mute audio */ +enum audio_result dal_audio_mute( + struct audio *audio, + enum engine_id engine_id, + enum signal_type signal); + + +/***** information interface *****/ + +struct audio_feature_support dal_audio_get_supported_features( + struct audio *audio); + +/* get audio bandwidth information */ +void dal_audio_check_audio_bandwidth( + struct audio *audio, + const struct audio_crtc_info *info, + uint32_t channel_count, + enum signal_type signal, + union audio_sample_rates *sample_rates); + +/* Enable multi channel split */ +void dal_audio_enable_channel_splitting_mapping( + struct audio *audio, + enum engine_id engine_id, + enum signal_type signal, + const struct audio_channel_associate_info *audio_mapping, + bool enable); + +/* get current multi channel split. */ +enum audio_result dal_audio_get_channel_splitting_mapping( + struct audio *audio, + enum engine_id engine_id, + struct audio_channel_associate_info *audio_mapping); + +/* set payload value for the unsolicited response */ +void dal_audio_set_unsolicited_response_payload( + struct audio *audio, + enum audio_payload payload); + +/*Assign GTC group and enable GTC value embedding*/ +void dal_audio_enable_gtc_embedding_with_group( + struct audio *audio, + uint32_t group_num, + uint32_t audio_latency); + +/* Disable GTC value embedding */ +void dal_audio_disable_gtc_embedding( + struct audio *audio); + +/* Update audio wall clock source */ +void dal_audio_setup_audio_wall_dto( + struct audio *audio, + enum signal_type signal, + const struct audio_crtc_info *crtc_info, + const struct audio_pll_info *pll_info); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/audio_types.h b/drivers/gpu/drm/amd/dal/include/audio_types.h new file mode 100644 index 000000000000..54f5546a574c --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/audio_types.h @@ -0,0 +1,277 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __AUDIO_TYPES_H__ +#define __AUDIO_TYPES_H__ + +#include "grph_object_defs.h" +#include "signal_types.h" + +#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 +#define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18 +#define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF + + +struct audio_pll_hw_settings { + uint32_t feed_back_divider; + uint32_t step_size_integer; + uint32_t step_size_fraction; + uint32_t step_range; +}; + +struct audio_clock_info { + /* pixel clock frequency*/ + uint32_t pixel_clock_in_10khz; + /* N - 32KHz audio */ + uint32_t n_32khz; + /* CTS - 32KHz audio*/ + uint32_t cts_32khz; + uint32_t n_44khz; + uint32_t cts_44khz; + uint32_t n_48khz; + uint32_t cts_48khz; +}; + +struct azalia_clock_info { + uint32_t pixel_clock_in_10khz; + uint32_t audio_dto_phase; + uint32_t audio_dto_module; + uint32_t audio_dto_wall_clock_ratio; +}; + +enum audio_dto_source { + DTO_SOURCE_UNKNOWN = 0, + DTO_SOURCE_ID0, + DTO_SOURCE_ID1, + DTO_SOURCE_ID2, + DTO_SOURCE_ID3, + DTO_SOURCE_ID4, + DTO_SOURCE_ID5 +}; + +union audio_sample_rates { + struct sample_rates { + uint8_t RATE_32:1; + uint8_t RATE_44_1:1; + uint8_t RATE_48:1; + uint8_t RATE_88_2:1; + uint8_t RATE_96:1; + uint8_t RATE_176_4:1; + uint8_t RATE_192:1; + } rate; + + uint8_t all; +}; + +enum audio_format_code { + AUDIO_FORMAT_CODE_FIRST = 1, + AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, + + AUDIO_FORMAT_CODE_AC3, + /*Layers 1 & 2 */ + AUDIO_FORMAT_CODE_MPEG1, + /*MPEG1 Layer 3 */ + AUDIO_FORMAT_CODE_MP3, + /*multichannel */ + AUDIO_FORMAT_CODE_MPEG2, + AUDIO_FORMAT_CODE_AAC, + AUDIO_FORMAT_CODE_DTS, + AUDIO_FORMAT_CODE_ATRAC, + AUDIO_FORMAT_CODE_1BITAUDIO, + AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, + AUDIO_FORMAT_CODE_DTS_HD, + AUDIO_FORMAT_CODE_MAT_MLP, + AUDIO_FORMAT_CODE_DST, + AUDIO_FORMAT_CODE_WMAPRO, + AUDIO_FORMAT_CODE_LAST, + AUDIO_FORMAT_CODE_COUNT = + AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST +}; + +struct audio_mode { + /* ucData[0] [6:3] */ + enum audio_format_code format_code; + /* ucData[0] [2:0] */ + uint8_t channel_count; + /* ucData[1] */ + union audio_sample_rates sample_rates; + union { + /* for LPCM */ + uint8_t sample_size; + /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ + uint8_t max_bit_rate; + /* for Audio Formats 9-15 */ + uint8_t vendor_specific; + }; +}; + +struct audio_speaker_flags { + uint32_t FL_FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RR:1; + uint32_t RC:1; + uint32_t FLC_FRC:1; + uint32_t RLC_RRC:1; + uint32_t SUPPORT_AI:1; +}; + +struct audio_speaker_info { + uint32_t ALLSPEAKERS:7; + uint32_t SUPPORT_AI:1; +}; + +struct audio_info_flags { + + union { + + struct audio_speaker_flags speaker_flags; + struct audio_speaker_info info; + + uint8_t all; + }; +}; + + +/*struct audio_info_flags { + struct audio_speaker_flags { + uint32_t FL_FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RR:1; + uint32_t RC:1; + uint32_t FLC_FRC:1; + uint32_t RLC_RRC:1; + uint32_t SUPPORT_AI:1; + }; + + struct audio_speaker_info { + uint32_t ALLSPEAKERS:7; + uint32_t SUPPORT_AI:1; + }; + + union { + struct audio_speaker_flags speaker_flags; + struct audio_speaker_info info; + }; +}; +*/ + +union audio_cea_channels { + uint8_t all; + struct audio_cea_channels_bits { + uint32_t FL:1; + uint32_t FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RC:1; + uint32_t RR:1; + uint32_t RC_RLC_FLC:1; + uint32_t RRC_FRC:1; + } channels; +}; + +struct audio_info { + struct audio_info_flags flags; + uint32_t video_latency; + uint32_t audio_latency; + uint32_t display_index; + uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; + uint32_t manufacture_id; + uint32_t product_id; + /* PortID used for ContainerID when defined */ + uint32_t port_id[2]; + uint32_t mode_count; + /* this field must be last in this struct */ + struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; +}; + +struct audio_crtc_info { + uint32_t h_total; + uint32_t h_active; + uint32_t v_active; + uint32_t pixel_repetition; + uint32_t requested_pixel_clock; /* in KHz */ + uint32_t calculated_pixel_clock; /* in KHz */ + uint32_t refresh_rate; + enum dc_color_depth color_depth; + bool interlaced; +}; + +/* PLL information required for AZALIA DTO calculation */ + +struct audio_pll_info { + uint32_t dp_dto_source_clock_in_khz; + uint32_t feed_back_divider; + enum audio_dto_source dto_source; + bool ss_enabled; + uint32_t ss_percentage; + uint32_t ss_percentage_divider; +}; + +struct audio_channel_associate_info { + union { + struct { + uint32_t ALL_CHANNEL_FL:4; + uint32_t ALL_CHANNEL_FR:4; + uint32_t ALL_CHANNEL_FC:4; + uint32_t ALL_CHANNEL_Sub:4; + uint32_t ALL_CHANNEL_SL:4; + uint32_t ALL_CHANNEL_SR:4; + uint32_t ALL_CHANNEL_BL:4; + uint32_t ALL_CHANNEL_BR:4; + } bits; + uint32_t u32all; + }; +}; + +struct audio_output { + /* Front DIG id. */ + enum engine_id engine_id; + /* encoder output signal */ + enum signal_type signal; + /* video timing */ + struct audio_crtc_info crtc_info; + /* PLL for audio */ + struct audio_pll_info pll_info; +}; + +struct audio_feature_support { + /* supported engines*/ + uint32_t ENGINE_DIGA:1; + uint32_t ENGINE_DIGB:1; + uint32_t ENGINE_DIGC:1; + uint32_t ENGINE_DIGD:1; + uint32_t ENGINE_DIGE:1; + uint32_t ENGINE_DIGF:1; + uint32_t ENGINE_DIGG:1; + uint32_t MULTISTREAM_AUDIO:1; +}; + +enum audio_payload { + CHANNEL_SPLIT_MAPPINGCHANG = 0x9, +}; + +#endif /* __AUDIO_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h new file mode 100644 index 000000000000..e4291b9ff320 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h @@ -0,0 +1,98 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_BIOS_PARSER_INTERFACE_H__ +#define __DAL_BIOS_PARSER_INTERFACE_H__ + +#include "dc_bios_types.h" + +struct adapter_service; +struct bios_parser; + +struct bp_init_data { + struct dc_context *ctx; + uint8_t *bios; +}; + +struct dc_bios *dal_bios_parser_create( + struct bp_init_data *init, + struct adapter_service *as); + +void dal_bios_parser_destroy( + struct dc_bios **dcb); + +/*****************************************************************************/ +/* Interfaces of BIOS Parser Helper */ +bool dal_bios_parser_is_lid_open( + struct bios_parser *bp); +bool dal_bios_parser_is_lid_status_changed( + struct bios_parser *bp); +bool dal_bios_parser_is_display_config_changed( + struct bios_parser *bp); +bool dal_bios_parser_is_accelerated_mode( + struct bios_parser *bp); +void dal_bios_parser_set_scratch_lcd_scale( + struct bios_parser *bp, + enum lcd_scale scale); +enum lcd_scale dal_bios_parser_get_scratch_lcd_scale( + struct bios_parser *bp); +void dal_bios_parser_get_bios_event_info( + struct bios_parser *bp, + struct bios_event_info *info); +void dal_bios_parser_update_requested_backlight_level( + struct bios_parser *bp, + uint32_t backlight_8bit); +uint32_t dal_bios_parser_get_requested_backlight_level( + struct bios_parser *bp); +void dal_bios_parser_take_backlight_control( + struct bios_parser *bp, + bool cntl); +bool dal_bios_parser_is_active_display( + struct bios_parser *bp, + enum signal_type signal, + const struct connector_device_tag_info *device_tag); +enum controller_id dal_bios_parser_get_embedded_display_controller_id( + struct bios_parser *bp); +uint32_t dal_bios_parser_get_embedded_display_refresh_rate( + struct bios_parser *bp); +void dal_bios_parser_set_scratch_connected( + struct bios_parser *bp, + struct graphics_object_id connector_id, + bool connected, + const struct connector_device_tag_info *device_tag); +void dal_bios_parser_prepare_scratch_active_and_requested( + struct bios_parser *bp, + enum controller_id controller_id, + enum signal_type signal, + const struct connector_device_tag_info *device_tag); +void dal_bios_parser_set_scratch_active_and_requested( + struct bios_parser *bp); +void dal_bios_parser_set_scratch_critical_state( + struct bios_parser *bp, + bool state); +void dal_bios_parser_set_scratch_acc_mode_change( + struct bios_parser *bp); + +#endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_types.h b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h new file mode 100644 index 000000000000..550ac874985b --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/bios_parser_types.h @@ -0,0 +1,327 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_BIOS_PARSER_TYPES_H__ + +#define __DAL_BIOS_PARSER_TYPES_H__ + +#include "dm_services.h" +#include "include/signal_types.h" +#include "include/grph_object_ctrl_defs.h" +#include "include/gpio_types.h" +#include "include/adapter_service_types.h" /* for as_signal_type */ +#include "include/link_service_types.h" + +enum bp_result { + BP_RESULT_OK = 0, /* There was no error */ + BP_RESULT_BADINPUT, /*Bad input parameter */ + BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */ + BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */ + BP_RESULT_NORECORD, /* Record can't be found */ + BP_RESULT_FAILURE +}; + +enum bp_encoder_control_action { + /* direct VBIOS translation! Just to simplify the translation */ + ENCODER_CONTROL_DISABLE = 0, + ENCODER_CONTROL_ENABLE, + ENCODER_CONTROL_SETUP, + ENCODER_CONTROL_INIT +}; + +enum bp_transmitter_control_action { + /* direct VBIOS translation! Just to simplify the translation */ + TRANSMITTER_CONTROL_DISABLE = 0, + TRANSMITTER_CONTROL_ENABLE, + TRANSMITTER_CONTROL_BACKLIGHT_OFF, + TRANSMITTER_CONTROL_BACKLIGHT_ON, + TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS, + TRANSMITTER_CONTROL_LCD_SETF_TEST_START, + TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP, + TRANSMITTER_CONTROL_INIT, + TRANSMITTER_CONTROL_DEACTIVATE, + TRANSMITTER_CONTROL_ACTIAVATE, + TRANSMITTER_CONTROL_SETUP, + TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS, + /* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only + * (power up the panel) + */ + TRANSMITTER_CONTROL_POWER_ON, + /* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only + * (power down the panel) + */ + TRANSMITTER_CONTROL_POWER_OFF +}; + +enum bp_external_encoder_control_action { + EXTERNAL_ENCODER_CONTROL_DISABLE = 0, + EXTERNAL_ENCODER_CONTROL_ENABLE = 1, + EXTERNAL_ENCODER_CONTROL_INIT = 0x7, + EXTERNAL_ENCODER_CONTROL_SETUP = 0xf, + EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10, + EXTERNAL_ENCODER_CONTROL_BLANK = 0x11, + EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12 +}; + +enum bp_pipe_control_action { + ASIC_PIPE_DISABLE = 0, + ASIC_PIPE_ENABLE, + ASIC_PIPE_INIT +}; + +struct bp_encoder_control { + enum bp_encoder_control_action action; + enum engine_id engine_id; + enum transmitter transmitter; + enum signal_type signal; + enum lane_count lanes_number; + enum dc_color_depth color_depth; + bool enable_dp_audio; + uint32_t pixel_clock; /* khz */ +}; + +struct bp_external_encoder_control { + enum bp_external_encoder_control_action action; + enum engine_id engine_id; + enum link_rate link_rate; + enum lane_count lanes_number; + enum signal_type signal; + enum dc_color_depth color_depth; + bool coherent; + struct graphics_object_id encoder_id; + struct graphics_object_id connector_obj_id; + uint32_t pixel_clock; /* in KHz */ +}; + +struct bp_crtc_source_select { + enum engine_id engine_id; + enum controller_id controller_id; + /* from GPU Tx aka asic_signal */ + enum signal_type signal; + /* sink_signal may differ from asicSignal if Translator encoder */ + enum signal_type sink_signal; + enum display_output_bit_depth display_output_bit_depth; + bool enable_dp_audio; +}; + +struct bp_transmitter_control { + enum bp_transmitter_control_action action; + enum engine_id engine_id; + enum transmitter transmitter; /* PhyId */ + enum lane_count lanes_number; + enum clock_source_id pll_id; /* needed for DCE 4.0 */ + enum signal_type signal; + enum dc_color_depth color_depth; /* not used for DCE6.0 */ + enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ + struct graphics_object_id connector_obj_id; + /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should + * be pixel clock * deep_color_ratio (in KHz) + */ + uint32_t pixel_clock; + uint32_t lane_select; + uint32_t lane_settings; + bool coherent; + bool multi_path; + bool single_pll_mode; +}; + +struct bp_blank_crtc_parameters { + enum controller_id controller_id; + uint32_t black_color_rcr; + uint32_t black_color_gy; + uint32_t black_color_bcb; +}; + +struct bp_hw_crtc_timing_parameters { + enum controller_id controller_id; + /* horizontal part */ + uint32_t h_total; + uint32_t h_addressable; + uint32_t h_overscan_left; + uint32_t h_overscan_right; + uint32_t h_sync_start; + uint32_t h_sync_width; + + /* vertical part */ + uint32_t v_total; + uint32_t v_addressable; + uint32_t v_overscan_top; + uint32_t v_overscan_bottom; + uint32_t v_sync_start; + uint32_t v_sync_width; + + struct timing_flags { + uint32_t INTERLACE:1; + uint32_t PIXEL_REPETITION:4; + uint32_t HSYNC_POSITIVE_POLARITY:1; + uint32_t VSYNC_POSITIVE_POLARITY:1; + uint32_t HORZ_COUNT_BY_TWO:1; + } flags; +}; + +struct bp_hw_crtc_overscan_parameters { + enum controller_id controller_id; + uint32_t h_overscan_left; + uint32_t h_overscan_right; + uint32_t v_overscan_top; + uint32_t v_overscan_bottom; +}; + +struct bp_adjust_pixel_clock_parameters { + /* Input: Signal Type - to be converted to Encoder mode */ + enum signal_type signal_type; + /* Input: Encoder object id */ + struct graphics_object_id encoder_object_id; + /* Input: Pixel Clock (requested Pixel clock based on Video timing + * standard used) in KHz + */ + uint32_t pixel_clock; + /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */ + uint32_t adjusted_pixel_clock; + /* Output: If non-zero, this refDiv value should be used to calculate + * other ppll params */ + uint32_t reference_divider; + /* Output: If non-zero, this postDiv value should be used to calculate + * other ppll params */ + uint32_t pixel_clock_post_divider; + /* Input: Enable spread spectrum */ + bool ss_enable; +}; + +struct bp_pixel_clock_parameters { + enum controller_id controller_id; /* (Which CRTC uses this PLL) */ + enum clock_source_id pll_id; /* Clock Source Id */ + /* signal_type -> Encoder Mode - needed by VBIOS Exec table */ + enum signal_type signal_type; + /* Adjusted Pixel Clock (after VBIOS exec table) + * that becomes Target Pixel Clock (KHz) */ + uint32_t target_pixel_clock; + /* Calculated Reference divider of Display PLL */ + uint32_t reference_divider; + /* Calculated Feedback divider of Display PLL */ + uint32_t feedback_divider; + /* Calculated Fractional Feedback divider of Display PLL */ + uint32_t fractional_feedback_divider; + /* Calculated Pixel Clock Post divider of Display PLL */ + uint32_t pixel_clock_post_divider; + struct graphics_object_id encoder_object_id; /* Encoder object id */ + /* VBIOS returns a fixed display clock when DFS-bypass feature + * is enabled (KHz) */ + uint32_t dfs_bypass_display_clock; + /* color depth to support HDMI deep color */ + enum transmitter_color_depth color_depth; + + struct program_pixel_clock_flags { + uint32_t FORCE_PROGRAMMING_OF_PLL:1; + /* Use Engine Clock as source for Display Clock when + * programming PLL */ + uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1; + /* Use external reference clock (refDivSrc for PLL) */ + uint32_t SET_EXTERNAL_REF_DIV_SRC:1; + /* Force program PHY PLL only */ + uint32_t PROGRAM_PHY_PLL_ONLY:1; + /* Support for YUV420 */ + uint32_t SUPPORT_YUV_420:1; + /* Use XTALIN reference clock source */ + uint32_t SET_XTALIN_REF_SRC:1; + /* Use GENLK reference clock source */ + uint32_t SET_GENLOCK_REF_DIV_SRC:1; + } flags; +}; + +struct bp_display_clock_parameters { + uint32_t target_display_clock; /* KHz */ + /* Actual Display Clock set due to clock divider granularity KHz */ + uint32_t actual_display_clock; + /* Actual Post Divider ID used to generate the actual clock */ + uint32_t actual_post_divider_id; +}; + +enum bp_dce_clock_type { + DCECLOCK_TYPE_DISPLAY_CLOCK = 0, + DCECLOCK_TYPE_DPREFCLK = 1 +}; + +/* DCE Clock Parameters structure for SetDceClock Exec command table */ +struct bp_set_dce_clock_parameters { + enum clock_source_id pll_id; /* Clock Source Id */ + /* Display clock or DPREFCLK value */ + uint32_t target_clock_frequency; + /* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */ + enum bp_dce_clock_type clock_type; + + struct set_dce_clock_flags { + uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1; + /* Use XTALIN reference clock source */ + uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1; + /* Use PCIE reference clock source */ + uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1; + /* Use GENLK reference clock source */ + uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1; + } flags; +}; + +struct spread_spectrum_flags { + /* 1 = Center Spread; 0 = down spread */ + uint32_t CENTER_SPREAD:1; + /* 1 = external; 0 = internal */ + uint32_t EXTERNAL_SS:1; + /* 1 = delta-sigma type parameter; 0 = ver1 */ + uint32_t DS_TYPE:1; +}; + +struct bp_spread_spectrum_parameters { + enum clock_source_id pll_id; + uint32_t percentage; + uint32_t ds_frac_amount; + + union { + struct { + uint32_t step; + uint32_t delay; + uint32_t range; /* In Hz unit */ + } ver1; + struct { + uint32_t feedback_amount; + uint32_t nfrac_amount; + uint32_t ds_frac_size; + } ds; + }; + + struct spread_spectrum_flags flags; +}; + +struct bp_encoder_cap_info { + uint32_t DP_HBR2_CAP:1; + uint32_t DP_HBR2_EN:1; + uint32_t RESERVED:30; +}; + +struct bp_gpio_cntl_info { + uint32_t id; + enum gpio_pin_output_state state; +}; + +#endif /*__DAL_BIOS_PARSER_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h new file mode 100644 index 000000000000..78f88b129a35 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h @@ -0,0 +1,117 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_ASIC_ID_H__ +#define __DAL_ASIC_ID_H__ + +/* + * ASIC internal revision ID + */ + +/* DCE80 (based on ci_id.h in Perforce) */ + +#define CI_BONAIRE_M_A0 0x14 +#define CI_BONAIRE_M_A1 0x15 +#define CI_HAWAII_P_A0 0x28 + +#define CI_UNKNOWN 0xFF + +#define ASIC_REV_IS_BONAIRE_M(rev) \ + ((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0)) + +#define ASIC_REV_IS_HAWAII_P(rev) \ + (rev >= CI_HAWAII_P_A0) + +/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */ +#define KV_SPECTRE_A0 0x01 + +/* KV2 with Spooky GFX core, including downgraded from Spectre core, + * 3-4-1-1 (CU-Pix-Primitive-RB) */ +#define KV_SPOOKY_A0 0x41 + +/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ +#define KB_KALINDI_A0 0x81 + +/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ +#define KB_KALINDI_A1 0x82 + +/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ +#define BV_KALINDI_A2 0x85 + +/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ +#define ML_GODAVARI_A0 0xA1 + +/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ +#define ML_GODAVARI_A1 0xA2 + +#define KV_UNKNOWN 0xFF + +#define ASIC_REV_IS_KALINDI(rev) \ + ((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN)) + +#define ASIC_REV_IS_BHAVANI(rev) \ + ((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0)) + +#define ASIC_REV_IS_GODAVARI(rev) \ + ((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN)) + +/* VI Family */ +/* DCE10 */ +#define VI_TONGA_P_A0 20 +#define VI_TONGA_P_A1 21 +#define VI_FIJI_P_A0 60 + +#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \ + (eChipRev < 40)) +#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \ + (eChipRev < 80)) + +/* DCE11 */ +#define CZ_CARRIZO_A0 0x01 + +#define STONEY_A0 0x61 +#define CZ_UNKNOWN 0xFF + +#define ASIC_REV_IS_STONEY(rev) \ + ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) + +/* + * ASIC chip ID + */ +/* DCE80 */ +#define DEVICE_ID_KALINDI_9834 0x9834 +#define DEVICE_ID_TEMASH_9839 0x9839 +#define DEVICE_ID_TEMASH_983D 0x983D + + +/* Asic Family IDs for different asic family. */ +#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */ +#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */ +#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ +#define FAMILY_CZ 135 /* Carrizo */ + +#define FAMILY_UNKNOWN 0xFF + +#endif /* __DAL_ASIC_ID_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dal_register_logger.h b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h new file mode 100644 index 000000000000..176d811327af --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h @@ -0,0 +1,43 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_REGISTER_LOGGER__ +#define __DAL_REGISTER_LOGGER__ + +/**************** + * API functions + ***************/ + +/* dal_reg_logger_push - begin Register Logging */ +void dal_reg_logger_push(const char *caller_func); +/* dal_reg_logger_pop - stop Register Logging */ +void dal_reg_logger_pop(void); + + +/* for internal use of the Logger only */ +void dal_reg_logger_rw_count_increment(void); +bool dal_reg_logger_should_dump_register(void); + +#endif /* __DAL_REGISTER_LOGGER__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h new file mode 100644 index 000000000000..373977685b70 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dal_types.h @@ -0,0 +1,305 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TYPES_H__ +#define __DAL_TYPES_H__ + +#include "signal_types.h" +#include "dc_types.h" + +struct dal_logger; +struct dc_bios; + +enum dce_version { + DCE_VERSION_UNKNOWN = (-1), +#if defined(CONFIG_DRM_AMD_DAL_DCE10_0) + DCE_VERSION_10_0, +#endif +#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) + DCE_VERSION_11_0, +#endif + DCE_VERSION_MAX +}; + +/* + * ASIC Runtime Flags + */ +struct dal_asic_runtime_flags { + union { + uint32_t raw; + struct { + uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1; + uint32_t SUPPORT_XRBIAS:1; + uint32_t SKIP_POWER_DOWN_ON_RESUME:1; + uint32_t FULL_DETECT_ON_RESUME:1; + uint32_t GSL_FRAMELOCK:1; + uint32_t NO_LOW_BPP_MODES:1; + uint32_t BLOCK_ON_INITIAL_DETECTION:1; + uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1; + uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1; + uint32_t MODIFIABLE_FRAME_DURATION:1; + uint32_t MIRACAST_SUPPORTED:1; + uint32_t CONNECTED_STANDBY_SUPPORTED:1; + uint32_t GNB_WAKEUP_SUPPORTED:1; + } bits; + } flags; +}; + +struct hw_asic_id { + uint32_t chip_id; + uint32_t chip_family; + uint32_t pci_revision_id; + uint32_t hw_internal_rev; + uint32_t vram_type; + uint32_t vram_width; + uint32_t feature_flags; + struct dal_asic_runtime_flags runtime_flags; + uint32_t fake_paths_num; + void *atombios_base_address; +}; + +/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/ + +struct bdf_info { + uint16_t BUS_NUMBER:8; + uint16_t DEVICE_NUMBER:5; + uint16_t FUNCTION_NUMBER:3; +}; + +#define DAL_PARAM_INVALID_INT 0x80000000 + +/* shift values for bool override parameter mask + * bmask is for this struct,if we touch this feature + * bval indicates every bit fields for this struct too,1 is enable this feature + * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 , + * finally will show log like this: + * Overridden FEATURE_LIGHT_SLEEP is enabled now + * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now + * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now + * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now + * Overridden FEATURE_USE_PPLIB is enabled now + * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now + * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now */ +enum bool_param_shift { + DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0, + DAL_PARAM_LIGHT_SLEEP, + DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS, + DAL_PARAM_USE_MAX_DISPLAY_CLK, + DAL_PARAM_ENABLE_DFS_BYPASS, + DAL_PARAM_POWER_GATING_PIPE_IN_TILE, + DAL_PARAM_POWER_GATING_LB_PORTION, + DAL_PARAM_PSR_ENABLE, + DAL_PARAM_VARI_BRIGHT_ENABLE, + DAL_PARAM_USE_PPLIB, + DAL_PARAM_DISABLE_LPT_SUPPORT, + DAL_PARAM_DUMMY_FBC_BACKEND, + DAL_PARAM_ENABLE_GPU_SCALING, + DAL_BOOL_PARAM_MAX +}; + +/* array index for integer override parameters*/ +enum int_param_array_index { + DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0, + DAL_PARAM_DRR_SUPPORT, + DAL_INT_PARAM_MAX +}; + +struct dal_override_parameters { + uint32_t bool_param_enable_mask; + uint32_t bool_param_values; + uint32_t int_param_values[DAL_INT_PARAM_MAX]; +}; + + +struct dal_init_data { + struct hw_asic_id asic_id; + struct view_port_alignment vp_alignment; + struct bdf_info bdf_info; + struct dal_override_parameters display_param; + void *driver; /* ctx */ + void *cgs_device; + uint8_t num_virtual_links; + /* If 'vbios_override' not NULL, it will be called instead + * of the real VBIOS. Intended use is Diagnostics on FPGA. */ + struct dc_bios *vbios_override; + enum dce_environment dce_environment; +}; + +struct dal_dc_init_data { + struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ + struct adapter_service *adapter_srv; +}; + +struct dal_dev_c_lut { + uint8_t red; + uint8_t green; + uint8_t blue; + uint8_t reserved; +}; + +struct dal_dev_gamma_lut { + uint16_t red; + uint16_t green; + uint16_t blue; +}; + +struct dc_context { + struct dc *dc; + + void *driver_context; /* e.g. amdgpu_device */ + + struct dal_logger *logger; + void *cgs_device; + + enum dce_environment dce_environment; +}; + +/* Wireless display structs */ + +union dal_remote_display_cea_mode_bitmap { + struct { + uint32_t CEA_640X480_60P:1;/*0*/ + uint32_t CEA_720X480_60P:1;/*1*/ + uint32_t CEA_720X480_60I:1;/*2*/ + uint32_t CEA_720X576_50P:1;/*3*/ + uint32_t CEA_720X576_50I:1;/*4*/ + uint32_t CEA_1280X720_30P:1;/*5*/ + uint32_t CEA_1280X720_60P:1;/*6*/ + uint32_t CEA_1920X1080_30P:1;/*7*/ + uint32_t CEA_1920X1080_60P:1;/*8*/ + uint32_t CEA_1920X1080_60I:1;/*9*/ + uint32_t CEA_1280X720_25P:1;/*10*/ + uint32_t CEA_1280X728_50P:1;/*11*/ + uint32_t CEA_1920X1080_25P:1;/*12*/ + uint32_t CEA_1920X1080_50P:1;/*13*/ + uint32_t CEA_1920X1080_50I:1;/*14*/ + uint32_t CEA_1280X1024_24P:1;/*15*/ + uint32_t CEA_1920X1080_24P:1;/*16*/ + uint32_t RESERVED:15;/*[17-31]*/ + } flags; + uint32_t raw; +}; + +union dal_remote_display_vesa_mode_bitmap { + struct { + uint32_t VESA_800X600_30P:1;/*0*/ + uint32_t VESA_800X600_60P:1;/*1*/ + uint32_t VESA_1024X768_30P:1;/*2*/ + uint32_t VESA_1024X768_60P:1;/*3*/ + uint32_t VESA_1152X864_30P:1;/*4*/ + uint32_t VESA_1152X864_60P:1;/*5*/ + uint32_t VESA_1280X768_30P:1;/*6*/ + uint32_t VESA_1280X768_60P:1;/*7*/ + uint32_t VESA_1280X800_30P:1;/*8*/ + uint32_t VESA_1280X800_60P:1;/*9*/ + uint32_t VESA_1360X768_30P:1;/*10*/ + uint32_t VESA_1360X768_60P:1;/*11*/ + uint32_t VESA_1366X768_30P:1;/*12*/ + uint32_t VESA_1366X768_60P:1;/*13*/ + uint32_t VESA_1280X1024_30P:1;/*14*/ + uint32_t VESA_1280X1024_60P:1;/*15*/ + uint32_t VESA_1400X1050_30P:1;/*16*/ + uint32_t VESA_1400X1050_60P:1;/*17*/ + uint32_t VESA_1440X900_30P:1;/*18*/ + uint32_t VESA_1440X900_60P:1;/*19*/ + uint32_t VESA_1600X900_30P:1;/*20*/ + uint32_t VESA_1600X900_60P:1;/*21*/ + uint32_t VESA_1600X1200_30P:1;/*22*/ + uint32_t VESA_1600X1200_60P:1;/*23*/ + uint32_t VESA_1680X1024_30P:1;/*24*/ + uint32_t VESA_1680X1024_60P:1;/*25*/ + uint32_t VESA_1680X1050_30P:1;/*26*/ + uint32_t VESA_1680X1050_60P:1;/*27*/ + uint32_t VESA_1920X1200_30P:1;/*28*/ + uint32_t VESA_1920X1200_60P:1;/*29*/ + uint32_t RESERVED:2;/*[30-31]*/ + } flags; + uint32_t raw; +}; + +union dal_remote_display_hh_mode_bitmap { + struct { + uint32_t HH_800X480_30P:1;/*0*/ + uint32_t HH_800X480_60P:1;/*1*/ + uint32_t HH_854X480_30P:1;/*2*/ + uint32_t HH_854X480_60P:1;/*3*/ + uint32_t HH_864X480_30P:1;/*4*/ + uint32_t HH_864X480_60P:1;/*5*/ + uint32_t HH_640X360_30P:1;/*6*/ + uint32_t HH_640X360_60P:1;/*7*/ + uint32_t HH_960X540_30P:1;/*8*/ + uint32_t HH_960X540_60P:1;/*9*/ + uint32_t HH_848X480_30P:1;/*10*/ + uint32_t HH_848X480_60P:1;/*11*/ + uint32_t RESERVED:20;/*[12-31]*/ + } flags; + uint32_t raw; +}; + +union dal_remote_display_stereo_3d_mode_bitmap { + struct { + uint32_t STEREO_1920X1080_24P_TOP_AND_BOTTOM:1;/*0*/ + uint32_t STEREO_1280X720_60P_TOP_AND_BOTTOM:1;/*1*/ + uint32_t STEREO_1280X720_50P_TOP_AND_BOTTOM:1;/*2*/ + uint32_t STEREO_1920X1080_24X2P_FRAME_ALTERNATE:1;/*3*/ + uint32_t STEREO_1280X720_60X2P_FRAME_ALTERNATE:1;/*4*/ + uint32_t STEREO_1280X720_30X2P_FRAME_ALTERNATE:1;/*5*/ + uint32_t STEREO_1280X720_50X2P_FRAME_ALTERNATE:1;/*6*/ + uint32_t STEREO_1280X720_25X2P_FRAME_ALTERNATE:1;/*7*/ + uint32_t STEREO_1920X1080_24P_FRAME_PACKING:1;/* 8*/ + uint32_t STEREO_1280X720_60P_FRAME_PACKING:1;/* 9*/ + uint32_t STEREO_1280X720_30P_FRAME_PACKING:1;/*10*/ + uint32_t STEREO_1280X720_50P_FRAME_PACKING:1;/*11*/ + uint32_t STEREO_1280X720_25P_FRAME_PACKING:1;/*12*/ + uint32_t RESERVED:19; /*[13-31]*/ + } flags; + uint32_t raw; +}; + +union dal_remote_display_audio_bitmap { + struct { + uint32_t LPCM_44100HZ_16BITS_2_CHANNELS:1;/*0*/ + uint32_t LPCM_48000HZ_16BITS_2_CHANNELS:1;/*1*/ + uint32_t AAC_48000HZ_16BITS_2_CHANNELS:1;/*2*/ + uint32_t AAC_48000HZ_16BITS_4_CHANNELS:1;/*3*/ + uint32_t AAC_48000HZ_16BITS_6_CHANNELS:1;/*4*/ + uint32_t AAC_48000HZ_16BITS_8_CHANNELS:1;/*5*/ + uint32_t AC3_48000HZ_16BITS_2_CHANNELS:1;/*6*/ + uint32_t AC3_48000HZ_16BITS_4_CHANNELS:1;/*7*/ + uint32_t AC3_48000HZ_16BITS_6_CHANNELS:1;/*8*/ + uint32_t RESERVED:23;/*[9-31]*/ + } flags; + uint32_t raw; +}; + +struct dal_remote_display_receiver_capability { + union dal_remote_display_cea_mode_bitmap cea_mode; + union dal_remote_display_vesa_mode_bitmap vesa_mode; + union dal_remote_display_hh_mode_bitmap hh_mode; + union dal_remote_display_stereo_3d_mode_bitmap stereo_3d_mode; + union dal_remote_display_audio_bitmap audio; +}; + +#endif /* __DAL_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h b/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h new file mode 100644 index 000000000000..b7fb9ff16a97 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h @@ -0,0 +1,77 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_CLOCK_GENERATOR_INTERFACE_H__ +#define __DC_CLOCK_GENERATOR_INTERFACE_H__ + +#include "grph_object_ctrl_defs.h" +#include "set_mode_types.h" + +/* Parameter for programming the DCCP_DISP_SLOW_SELECT*/ +struct dccg_mapping_params { + uint32_t controllers_num; + enum controller_id *controllers; +}; + +/* Parameters related to HW DeSpread of DP Reference Clock*/ +struct dccg_dp_ref_clk_ds_params { + struct { + /* Flag for Enabled SS on DP Reference Clock*/ + bool SS_ENABLED:1; + /* Flag for HW De Spread enabled + * (if enabled SS on DP Reference Clock)*/ + bool DS_ENABLED:1; + /* Flag for HW De Spread Calculations enabled for DS_DTO_INCR + * and DS_DTO_MODULO (if 0 SW programs DS_DTO_INCR and + * DS_DTO_MODULO)*/ + bool DS_CALCULATIONS:1; + } flags; + /*DP Reference clock SS percentage + * (if enabled downspread on DP Reference Clock)*/ + uint32_t ss_percentage; + /*DP Reference clock SS percentage Divider (1000 or 100)*/ + uint32_t ss_percentage_divider; +}; + +struct dc_clock_generator; + +void dal_dc_clock_generator_destroy(struct dc_clock_generator **dc); +void dal_dc_clock_generator_set_display_pipe_mapping( + struct dc_clock_generator *dc_clk_gen, + struct dccg_mapping_params *params); +bool dal_dc_clock_generator_get_dp_ref_clk_ds_params( + struct dc_clock_generator *dc_clk_gen, + struct dccg_dp_ref_clk_ds_params *params); +bool dal_dc_clock_generator_enable_gtc_counter( + struct dc_clock_generator *dc_clk_gen, + uint32_t dprefclk); +void dal_dc_clock_generator_disable_gtc_counter( + struct dc_clock_generator *dc_clk_gen); +void dal_dc_clock_generator_set_gtc_group_offset( + struct dc_clock_generator *dc_clk_gen, + enum gtc_group group_num, + uint32_t offset); + +#endif /* __DC_CLOCK_GENERATOR_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dcs_types.h b/drivers/gpu/drm/amd/dal/include/dcs_types.h new file mode 100644 index 000000000000..8c650571ff69 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dcs_types.h @@ -0,0 +1,742 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DCS_TYPES_H__ +#define __DAL_DCS_TYPES_H__ + +#include "signal_types.h" + +#include "dc_types.h" + +#define NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS 10 +#define MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT 21 +#define MAX_NUMBER_OF_HDMI_VSDB_VICS 7 + +struct drr_config { + /* minimum frame per second for dynamic + * refresh rate feature; 0 if drr support not found*/ + uint32_t min_fps_in_microhz; + bool force_lock_on_event; + bool lock_to_master_vsync; + + struct { + uint8_t FORCED_BY_REGKEY_OR_ESCAPE:1; + uint8_t FORCED_BY_VBIOS:1; + uint8_t SUPPORTED_BY_EDID:1; + } support_method; +}; + +struct timing_limits { + uint32_t min_pixel_clock_in_khz; + uint32_t max_pixel_clock_in_khz; +}; + +struct vendor_product_id_info { + uint32_t manufacturer_id; + uint32_t product_id; + uint32_t serial_id; + uint32_t manufacture_week; + uint32_t manufacture_year; +}; + +struct display_range_limits { + uint32_t min_v_rate_hz; + uint32_t max_v_rate_hz; + uint32_t min_h_rate_khz; + uint32_t max_h_rateIn_khz; + uint32_t max_pix_clk_khz; + bool use_override; +}; + +struct monitor_user_select_limits { + bool use_ati_override; + uint32_t max_h_res; + uint32_t max_v_res; + uint32_t max_refresh_rate; +}; + +enum edid_screen_aspect_ratio { + EDID_SCREEN_AR_UNKNOWN = 0, + EDID_SCREEN_AR_PROJECTOR, + EDID_SCREEN_AR_16X9, + EDID_SCREEN_AR_16X10, + EDID_SCREEN_AR_4X3, + EDID_SCREEN_AR_5X4, + EDID_SCREEN_AR_9X16, + EDID_SCREEN_AR_10X16, + EDID_SCREEN_AR_3X4, + EDID_SCREEN_AR_4X5 +}; + +struct edid_screen_info { + enum edid_screen_aspect_ratio aspect_ratio; + uint32_t width; + uint32_t height; +}; + +struct display_characteristics { + uint8_t gamma; + uint8_t color_characteristics[NUM_OF_BYTE_EDID_COLOR_CHARACTERISTICS]; +}; + +union cv_smart_dongle_modes { + uint8_t all; + struct cv_smart_dongle_switches { + uint8_t MODE_1080I:1; + uint8_t MODE_720P:1; + uint8_t MODE_540P:1; + uint8_t MODE_480P:1; + uint8_t MODE_480I:1; + uint8_t MODE_16_9:1; + } switches; +}; + +struct cea_audio_mode { + uint8_t format_code; /* ucData[0] [6:3]*/ + uint8_t channel_count; /* ucData[0] [2:0]*/ + uint8_t sample_rate; /* ucData[1]*/ + union { + uint8_t sample_size; /* for LPCM*/ + /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ + uint8_t max_bit_rate; + uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ + }; +}; + +union cea_speaker_allocation_data_block { + struct { + uint32_t FL_FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RR:1; + uint32_t RC:1; + uint32_t FLC_FRC:1; + uint32_t RLC_RRC:1; + } bits; + uint32_t raw; +}; + +struct cea_colorimetry_data_block { + struct { + uint32_t XV_YCC601:1; + uint32_t XV_YCC709:1; + uint32_t S_YCC601:1; + uint32_t ADOBE_YCC601:1; + uint32_t ADOBE_RGB:1; + + } flag; + struct { + uint32_t MD0:1; + uint32_t MD1:1; + uint32_t MD2:1; + uint32_t MD3:1; + } metadata_flag; +}; + +union cea_video_capability_data_block { + struct { + uint8_t S_CE0:1; + uint8_t S_CE1:1; + uint8_t S_IT0:1; + uint8_t S_IT1:1; + uint8_t S_PT0:1; + uint8_t S_PT1:1; + uint8_t QS:1; + uint8_t QY:1; + } bits; + uint8_t raw; +}; + +enum stereo_3d_multi_presence { + STEREO_3D_MULTI_NOT_PRESENT = 0, + STEREO_3D_MULTI_ALL_FORMATS, + STEREO_3D_MULTI_MASKED_FORMATS, + STEREO_3D_MULTI_RESERVED +}; + +enum cea_hdmi_vic { + CEA_HDMI_VIC_RESERVED = 0, + CEA_HDMI_VIC_4KX2K_30, + CEA_HDMI_VIC_4KX2K_25, + CEA_HDMI_VIC_4KX2K_24, + CEA_HDMI_VIC_4KX2K_24_SMPTE +}; + +struct cea_hdmi_vsdb_extended_caps { + uint32_t reserved; + uint32_t image_size; + enum stereo_3d_multi_presence stereo_3d_multi_present; + bool stereo_3d_present; + uint32_t hdmi_3d_len; + uint32_t hdmi_vic_len; +}; + +struct cea_vendor_specific_data_block { + + uint32_t ieee_id; + + struct commonent_phy { + uint32_t PHY_ADDR_A:4; + uint32_t PHY_ADDR_B:4; + uint32_t PHY_ADDR_C:4; + uint32_t PHY_ADDR_D:4; + } commonent_phy_addr; + + struct byte6 { + uint32_t SUPPORTS_AI:1; + uint32_t DC_48BIT:1; + uint32_t DC_36BIT:1; + uint32_t DC_30BIT:1; + uint32_t DC_Y444:1; + uint32_t DVI_DUAL:1; + uint32_t RESERVED:2; + } byte6;/* link capabilities*/ + bool byte6_valid; + + uint32_t max_tmds_clk_mhz; + + struct byte8 { + uint32_t LATENCY_FIELDS_PRESENT:1; + uint32_t ILATENCY_FIELDS_PRESENT:1; + uint32_t HDMI_VIDEO_PRESENT:1; + uint32_t RESERVED:1; + uint32_t CNC3_GAME:1; + uint32_t CNC2_CINEMA:1; + uint32_t CNC1_PHOTO:1; + uint32_t CNC0_GRAPHICS:1; + } byte8; + /*bit 6-7: latency flags to indicate valid latency fields*/ + /*bit 5: support of additional video format capabilities*/ + /* bit 0-3: flags indicating which content type is supported*/ + uint32_t video_latency; + uint32_t audio_latency; + uint32_t i_video_latency; + uint32_t i_audio_latency; + + struct cea_hdmi_vsdb_extended_caps hdmi_vsdb_extended_caps; + + enum stereo_3d_multi_presence stereo_3d_multi_present; + + struct { + bool FRAME_PACKING:1; + bool SIDE_BY_SIDE_HALF:1; + bool TOP_AND_BOTTOM:1; + } stereo_3d_all_support; + uint16_t stereo_3d_mask; + + enum cea_hdmi_vic hdmi_vic[MAX_NUMBER_OF_HDMI_VSDB_VICS]; + struct stereo_3d_extended_support { + struct { + bool FRAME_PACKING:1; + bool SIDE_BY_SIDE_HALF:1; + bool TOP_AND_BOTTOM:1; + } format; + uint32_t vic_index; + uint32_t value; + uint32_t size; + } stereo_3d_extended_support[MAX_NUMBER_OF_HDMI_VSDB_3D_EXTENDED_SUPPORT]; +}; + +struct cea861_support { + + uint32_t revision; + union { + struct { + uint32_t NATIVE_COUNT:4; + uint32_t BASE_AUDIO:1; + uint32_t YCRCB444:1; + uint32_t YCRCB422:1; + uint32_t UNDER_SCAN:1; + } features; + uint8_t raw_features; + }; +}; + +struct dcs_customized_mode { + struct { + uint32_t READ_ONLY:1; + uint32_t ADD_BY_DRIVER:1; + uint32_t INTERLACED:1; + uint32_t BASE_MODE:1; + } flags; + struct dc_mode_info base_mode_info; + struct dc_mode_info customized_mode_info; +}; + +struct dcs_override_mode_timing { + /* possible timing standards, bit vector of TimingStandard*/ + uint32_t possible_timing_standards; + /* indicate driver default timing is used , no override*/ + bool use_driver_default_timing; + struct dc_mode_timing mode_timing; +}; + +struct dcs_override_mode_timing_list { + uint32_t max_num_overrides; + uint32_t num_overrides; + struct dcs_override_mode_timing mode_timings[1]; +}; + +/* "interface type" is different from Signal Type because + * an "interface type" can be driven by more than one Signal Type. + * For example, INTERFACE_TYPE_DVI can be driven by + * Single or Dual link DVI signal. */ +enum dcs_interface_type { + INTERFACE_TYPE_VGA = 0, + INTERFACE_TYPE_DVI, + INTERFACE_TYPE_CV, + INTERFACE_TYPE_TV, + INTERFACE_TYPE_LVDS, + INTERFACE_TYPE_DP, + INTERFACE_TYPE_WIRELESS, + INTERFACE_TYPE_CF, + INTERFACE_TYPE_EDP +}; + + +union panel_misc_info { + struct { + uint32_t H_CUT_OFF:1; + uint32_t H_SYNC_POLARITY:1;/*0=Active High, 1=Active Low*/ + uint32_t V_SYNC_POLARITY:1; /*0=Active High, 1=Active Low*/ + uint32_t V_CUT_OFF:1; + uint32_t H_REPLICATION_BY_2:1; + uint32_t V_REPLICATION_BY_2:1; + uint32_t COMPOSITE_SYNC:1; + uint32_t INTERLACE:1; + uint32_t DOUBLE_CLOCK:1; + uint32_t RGB888:1; + uint32_t GREY_LEVEL:2; + uint32_t SPATIAL:1; + uint32_t TEMPORAL:1; + uint32_t API_ENABLED:1; + } bits; + uint32_t raw; +}; + +union hdtv_mode_support { + struct { + uint32_t HDTV_SUPPORT_480I:1; + uint32_t HDTV_SUPPORT_480P:1; + uint32_t HDTV_SUPPORT_576I25:1; + uint32_t HDTV_SUPPORT_576P50:1; + uint32_t HDTV_SUPPORT_720P:1; + uint32_t HDTV_SUPPORT_720P50:1; + uint32_t HDTV_SUPPORT_1080I:1; + uint32_t HDTV_SUPPORT_1080I25:1; + uint32_t HDTV_SUPPORT_1080P:1; + uint32_t HDTV_SUPPORT_1080P50:1; + uint32_t HDTV_SUPPORT_1080P24:1; + uint32_t HDTV_SUPPORT_1080P25:1; + uint32_t HDTV_SUPPORT_1080P30:1; + uint32_t HDTV_SUPPORT_16X9:1; + } bits; + uint32_t raw; +}; + +enum edid_retrieve_status { + EDID_RETRIEVE_SUCCESS = 0, + EDID_RETRIEVE_FAIL, + EDID_RETRIEVE_SAME_EDID, + EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS +}; + +#define DCS_DECODE_EDID_RETRIEVE_STATUS(status) \ + (status == EDID_RETRIEVE_SUCCESS) ? "EDID_RETRIEVE_SUCCESS" : \ + (status == EDID_RETRIEVE_FAIL) ? "EDID_RETRIEVE_FAIL" : \ + (status == EDID_RETRIEVE_SAME_EDID) ? "EDID_RETRIEVE_SAME_EDID" : \ + (status == EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS) ? \ + "EDID_RETRIEVE_FAIL_WITH_PREVIOUS_SUCCESS" : "Unknown" + + +#ifndef TV_SIGNALFORMAT_DEFINED +#define TV_SIGNALFORMAT_DEFINED +enum tv_signal_format { + TV_SIGNAL_FORMAT_UNKNOWN, + TV_SIGNAL_FORMAT_NTSC, + TV_SIGNAL_FORMAT_NTSC_J, + TV_SIGNAL_FORMAT_PAL, + TV_SIGNAL_FORMAT_PAL_M, + TV_SIGNAL_FORMAT_PAL_CN, + TV_SIGNAL_FORMAT_SECAM +}; +#endif + +enum tv_signal_format_result { + TV_SIGNAL_FORMAT_RESULT_OK, + TV_SIGNAL_FORMAT_SET_MODE_REQ, + TV_SIGNAL_FORMAT_REBOOT_REQ, + TV_SIGNAL_FORMAT_ERROR +}; + +enum pixel_encoding_mask { + PIXEL_ENCODING_MASK_YCBCR444 = 0x01, + PIXEL_ENCODING_MASK_YCBCR422 = 0x02, + PIXEL_ENCODING_MASK_RGB = 0x04, +}; + +struct display_pixel_encoding_support { + uint32_t mask; +}; + +enum color_depth_index { + COLOR_DEPTH_INDEX_UNKNOWN, + COLOR_DEPTH_INDEX_666 = 0x01, + COLOR_DEPTH_INDEX_888 = 0x02, + COLOR_DEPTH_INDEX_101010 = 0x04, + COLOR_DEPTH_INDEX_121212 = 0x08, + COLOR_DEPTH_INDEX_141414 = 0x10, + COLOR_DEPTH_INDEX_161616 = 0x20, + COLOR_DEPTH_INDEX_LAST = 0x40, +}; + +struct display_color_depth_support { + uint32_t mask; + bool deep_color_native_res_only; +}; + +struct display_color_and_pixel_support { + struct display_color_depth_support color_depth_support; + struct display_pixel_encoding_support pixel_encoding_support; + bool deep_color_y444_support; +}; + +enum dcs_packed_pixel_format { + DCS_PACKED_PIXEL_FORMAT_NOT_PACKED = 0, + DCS_PACKED_PIXEL_FORMAT_SPLIT_G70_B54_R70_B10 = 1, + DCS_PACKED_PIXEL_FORMAT_R70_G76 = 2, + DCS_PACKED_PIXEL_FORMAT_SPLIT_B70_G10_R70_G76 = 3, + DCS_PACKED_PIXEL_FORMAT_G70_B54_R70_B10 = 4, + DCS_PACKED_PIXEL_FORMAT_G70_B54 = 5, + DCS_PACKED_PIXEL_FORMAT_B70_R30_G70_R74 = 6, + DCS_PACKED_PIXEL_FORMAT_B70_G70_R70 = 7, + DCS_PACKED_PIXEL_FORMAT_B70_R32_G70_R76 = 8, +}; + +enum monitor_manufacturer_id { + MONITOR_MANUFACTURER_ID_0 = 0x0000, + MONITOR_MANUFACTURER_ID_1 = 0x3834, + MONITOR_MANUFACTURER_ID_2 = 0x4d24, + MONITOR_MANUFACTURER_ID_3 = 0x293E, + MONITOR_MANUFACTURER_ID_4 = 0x635a, + MONITOR_MANUFACTURER_ID_5 = 0x1006, + MONITOR_MANUFACTURER_ID_6 = 0xc32a, + MONITOR_MANUFACTURER_ID_7 = 0x4d24, + MONITOR_MANUFACTURER_ID_8 = 0x110e, + MONITOR_MANUFACTURER_ID_9 = 0xaf0d, + MONITOR_MANUFACTURER_ID_10 = 0x6D1E, + MONITOR_MANUFACTURER_ID_11 = 0xA338, + MONITOR_MANUFACTURER_ID_12 = 0xC315, + MONITOR_MANUFACTURER_ID_13 = 0xD94D, + MONITOR_MANUFACTURER_ID_14 = 0x104D, + MONITOR_MANUFACTURER_ID_15 = 0x855C, + MONITOR_MANUFACTURER_ID_16 = 0x4251, + MONITOR_MANUFACTURER_ID_17 = 0xA934, + MONITOR_MANUFACTURER_ID_18 = 0x0C41, + /* TODO: Update when EDID is available */ + MONITOR_MANUFACTURER_ID_19 = 0xDEAD, + MONITOR_MANUFACTURER_ID_20 = 0x6904, + MONITOR_MANUFACTURER_ID_21 = 0xAC10, + MONITOR_MANUFACTURER_ID_22 = 0x2D4C, + MONITOR_MANUFACTURER_ID_23 = 0x144E, + MONITOR_MANUFACTURER_ID_24 = 0x6c50, + MONITOR_MANUFACTURER_ID_26 = 0x0c41, + MONITOR_MANUFACTURER_ID_27 = 0x143E, + MONITOR_MANUFACTURER_ID_25 = 0xffff, + MONITOR_MANUFACTURER_ID_28 = 0x3421, + MONITOR_MANUFACTURER_ID_29 = 0x2D19, + MONITOR_MANUFACTURER_ID_30 = 0x8B52, + MONITOR_MANUFACTURER_ID_31 = 0x7204, + MONITOR_MANUFACTURER_ID_32 = 0xF022, + MONITOR_MANUFACTURER_ID_33 = 0x0E11, + MONITOR_MANUFACTURER_ID_34 = 0xD241, + MONITOR_MANUFACTURER_ID_35 = 0xAE30, + MONITOR_MANUFACTURER_ID_36 = 0xF91E, + MONITOR_MANUFACTURER_ID_37 = 0xAB4C, +}; + +enum monitor_product_id { + MONITOR_PRODUCT_ID_0 = 0x0000, + MONITOR_PRODUCT_ID_1 = 0x0BCC, + MONITOR_PRODUCT_ID_2 = 0x251F, + MONITOR_PRODUCT_ID_3 = 0x5241, + MONITOR_PRODUCT_ID_4 = 0x6919, + MONITOR_PRODUCT_ID_5 = 0xee18, + MONITOR_PRODUCT_ID_6 = 0xf008, + MONITOR_PRODUCT_ID_7 = 0x2f0c, + MONITOR_PRODUCT_ID_7_2 = 0x3411, + MONITOR_PRODUCT_ID_9 = 0x4208, + MONITOR_PRODUCT_ID_10 = 0xE51D, + MONITOR_PRODUCT_ID_11 = 0x7E22, + MONITOR_PRODUCT_ID_12 = 0x0E23, + MONITOR_PRODUCT_ID_13 = 0x9d08, + MONITOR_PRODUCT_ID_14 = 0x9236, + MONITOR_PRODUCT_ID_15 = 0x9227, + MONITOR_PRODUCT_ID_16 = 0x0220, + MONITOR_PRODUCT_ID_17 = 0x4920, + MONITOR_PRODUCT_ID_18 = 0x251f, + MONITOR_PRODUCT_ID_19 = 0x1395, + MONITOR_PRODUCT_ID_20 = 0xc04e, + MONITOR_PRODUCT_ID_21 = 0x5787, + MONITOR_PRODUCT_ID_22 = 0x5A71, + MONITOR_PRODUCT_ID_23 = 0x6622, + MONITOR_PRODUCT_ID_24 = 0x20C1, + MONITOR_PRODUCT_ID_25 = 0x2110, + MONITOR_PRODUCT_ID_26 = 0x2006, + MONITOR_PRODUCT_ID_27 = 0x1827, + MONITOR_PRODUCT_ID_28 = 0x0EA0, + MONITOR_PRODUCT_ID_29 = 0x03D0, + MONITOR_PRODUCT_ID_30 = 0x01D2, + MONITOR_PRODUCT_ID_31 = 0x2801, + MONITOR_PRODUCT_ID_32 = 0x0FB3, + MONITOR_PRODUCT_ID_33 = 0x0FB1, + MONITOR_PRODUCT_ID_34 = 0xA045, + MONITOR_PRODUCT_ID_35 = 0x0001, + MONITOR_PRODUCT_ID_36 = 0xA296, + MONITOR_PRODUCT_ID_38 = 0x21DC, + MONITOR_PRODUCT_ID_37 = 0x21EA, + MONITOR_PRODUCT_ID_39 = 0x4093, + MONITOR_PRODUCT_ID_40 = 0x4094, + MONITOR_PRODUCT_ID_41 = 0x4094, + MONITOR_PRODUCT_ID_42 = 0x32A2, + MONITOR_PRODUCT_ID_43 = 0xE009, + MONITOR_PRODUCT_ID_44 = 0xA010, + MONITOR_PRODUCT_ID_45 = 0x405C, + MONITOR_PRODUCT_ID_46 = 0xF017, + MONITOR_PRODUCT_ID_47 = 0xD026, + MONITOR_PRODUCT_ID_48 = 0x4036, + MONITOR_PRODUCT_ID_49 = 0x4065, + MONITOR_PRODUCT_ID_50 = 0xA02A, + MONITOR_PRODUCT_ID_51 = 0xA02C, + MONITOR_PRODUCT_ID_46_HDMI = 0xF016, + MONITOR_PRODUCT_ID_53 = 0xF048, + MONITOR_PRODUCT_ID_54 = 0xA0A2, + MONITOR_PRODUCT_ID_55 = 0x4083, + MONITOR_PRODUCT_ID_56 = 0x0E74, + MONITOR_PRODUCT_ID_57 = 0x2771, + MONITOR_PRODUCT_ID_58 = 0x0814, + MONITOR_PRODUCT_ID_59 = 0xffff, + MONITOR_PRODUCT_ID_60 = 0x3339, + MONITOR_PRODUCT_ID_61 = 0x01F5, + MONITOR_PRODUCT_ID_62 = 0x02A5, + MONITOR_PRODUCT_ID_63 = 0x06AC, + MONITOR_PRODUCT_ID_64 = 0x04D5, + MONITOR_PRODUCT_ID_65 = 0x079D, + MONITOR_PRODUCT_ID_66 = 0x079F, + MONITOR_PRODUCT_ID_67 = 0x0797, + MONITOR_PRODUCT_ID_68 = 0x0B80, + MONITOR_PRODUCT_ID_69 = 0x7D06, + MONITOR_PRODUCT_ID_70 = 0x0131, + MONITOR_PRODUCT_ID_71 = 0x8545, + MONITOR_PRODUCT_ID_72 = 0x0002, + MONITOR_PRODUCT_ID_73 = 0x0125, + MONITOR_PRODUCT_ID_74 = 0x00D0, + MONITOR_PRODUCT_ID_75 = 0x26F7, + MONITOR_PRODUCT_ID_76 = 0x26F9, + MONITOR_PRODUCT_ID_77 = 0x2807, + MONITOR_PRODUCT_ID_78 = 0x26F3, + MONITOR_PRODUCT_ID_79 = 0x2676, + MONITOR_PRODUCT_ID_80 = 0x0A72, + MONITOR_PRODUCT_ID_81 = 0x2693, + MONITOR_PRODUCT_ID_82 = 0x2615, + MONITOR_PRODUCT_ID_83 = 0x2613, + MONITOR_PRODUCT_ID_84 = 0x262D, + MONITOR_PRODUCT_ID_85 = 0x264B, + MONITOR_PRODUCT_ID_86 = 0x2869, + MONITOR_PRODUCT_ID_87 = 0x286C, + MONITOR_PRODUCT_ID_88 = 0x288F, + MONITOR_PRODUCT_ID_89 = 0x2954, + MONITOR_PRODUCT_ID_90 = 0x6522, + MONITOR_PRODUCT_ID_91 = 0x0FAE, + MONITOR_PRODUCT_ID_92 = 0x0A0C, + MONITOR_PRODUCT_ID_93 = 0x00BF, + MONITOR_PRODUCT_ID_94 = 0x0, +}; + +enum monitor_patch_type { + MONITOR_PATCH_TYPE_NONE, + MONITOR_PATCH_TYPE_ERROR_CHECKSUM, + MONITOR_PATCH_TYPE_HDTV_WITH_PURE_DFP_EDID, + MONITOR_PATCH_TYPE_DO_NOT_USE_DETAILED_TIMING, + MONITOR_PATCH_TYPE_DO_NOT_USE_RANGE_LIMITATION, + MONITOR_PATCH_TYPE_EDID_EXTENTION_ERROR_CHECK_SUM, + MONITOR_PATCH_TYPE_TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE, + MONITOR_PATCH_TYPE_RESTRICT_VESA_MODE_TIMING, + MONITOR_PATCH_TYPE_DO_NOT_USE_EDID_MAX_PIX_CLK, + MONITOR_PATCH_TYPE_VENDOR_0, + MONITOR_PATCH_TYPE_RANDOM_CRT, + MONITOR_PATCH_TYPE_VENDOR_1, + MONITOR_PATCH_TYPE_LIMIT_PANEL_SUPPORT_RGB_ONLY, + MONITOR_PATCH_TYPE_PACKED_PIXEL_FORMAT, + MONITOR_PATCH_TYPE_LARGE_PANEL, + MONITOR_PATCH_TYPE_STEREO_SUPPORT, + /* 0 (default) - mean patch will not be applied, however it can be + * explicitly set to 1 + */ + MONITOR_PATCH_TYPE_DUAL_EDID_PANEL, + MONITOR_PATCH_TYPE_IGNORE_19X12_STD_TIMING, + MONITOR_PATCH_TYPE_MULTIPLE_PACKED_TYPE, + MONITOR_PATCH_TYPE_RESET_TX_ON_DISPLAY_POWER_ON, + MONITOR_PATCH_TYPE_VENDOR_2, + MONITOR_PATCH_TYPE_RESTRICT_PROT_DUAL_LINK_DVI, + MONITOR_PATCH_TYPE_FORCE_LINK_RATE, + MONITOR_PATCH_TYPE_DELAY_AFTER_DP_RECEIVER_POWER_UP, + MONITOR_PATCH_TYPE_KEEP_DP_RECEIVER_POWERED, + MONITOR_PATCH_TYPE_DELAY_BEFORE_READ_EDID, + MONITOR_PATCH_TYPE_DELAY_AFTER_PIXEL_FORMAT_CHANGE, + MONITOR_PATCH_TYPE_INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX, + MONITOR_PATCH_TYPE_NO_DEFAULT_TIMINGS, + MONITOR_PATCH_TYPE_ADD_CEA861_DETAILED_TIMING_VIC16, + MONITOR_PATCH_TYPE_ADD_CEA861_DETAILED_TIMING_VIC31, + MONITOR_PATCH_TYPE_DELAY_BEFORE_UNMUTE, + MONITOR_PATCH_TYPE_RETRY_LINK_TRAINING_ON_FAILURE, + MONITOR_PATCH_TYPE_ALLOW_AUX_WHEN_HPD_LOW, + MONITOR_PATCH_TYPE_TILED_DISPLAY, + MONITOR_PATCH_TYPE_DISABLE_PSR_ENTRY_ABORT, + MONITOR_PATCH_TYPE_EDID_EXTENTION_ERROR_CHECKSUM, + MONITOR_PATCH_TYPE_ALLOW_ONLY_CE_MODE, + MONITOR_PATCH_TYPE_VID_STREAM_DIFFER_TO_SYNC, + MONITOR_PATCH_TYPE_EXTRA_DELAY_ON_DISCONNECT, + MONITOR_PATCH_TYPE_DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS, + MONITOR_PATCH_TYPE_SINGLE_MODE_PACKED_PIXEL +}; + +/* Single entry in the monitor table */ +struct monitor_patch_info { + enum monitor_manufacturer_id manufacturer_id; + enum monitor_product_id product_id; + enum monitor_patch_type type; + uint32_t param; +}; + +union dcs_monitor_patch_flags { + struct { + bool ERROR_CHECKSUM:1; + bool HDTV_WITH_PURE_DFP_EDID:1; + bool DO_NOT_USE_DETAILED_TIMING:1; + bool DO_NOT_USE_RANGE_LIMITATION:1; + bool EDID_EXTENTION_ERROR_CHECKSUM:1; + bool TURN_OFF_DISPLAY_BEFORE_MODE_CHANGE:1; + bool RESTRICT_VESA_MODE_TIMING:1; + bool DO_NOT_USE_EDID_MAX_PIX_CLK:1; + bool VENDOR_0:1; + bool RANDOM_CRT:1;/* 10 bits used including this one-*/ + bool VENDOR_1:1; + bool LIMIT_PANEL_SUPPORT_RGB_ONLY:1; + bool PACKED_PIXEL_FORMAT:1; + bool LARGE_PANEL:1; + bool STEREO_SUPPORT:1; + bool DUAL_EDID_PANEL:1; + bool IGNORE_19X12_STD_TIMING:1; + bool MULTIPLE_PACKED_TYPE:1; + bool RESET_TX_ON_DISPLAY_POWER_ON:1; + bool ALLOW_ONLY_CE_MODE:1;/* 20 bits used including this one*/ + bool RESTRICT_PROT_DUAL_LINK_DVI:1; + bool FORCE_LINK_RATE:1; + bool DELAY_AFTER_DP_RECEIVER_POWER_UP:1; + bool KEEP_DP_RECEIVER_POWERED:1; + bool DELAY_BEFORE_READ_EDID:1; + bool DELAY_AFTER_PIXEL_FORMAT_CHANGE:1; + bool INCREASE_DEFER_WRITE_RETRY_I2C_OVER_AUX:1; + bool NO_DEFAULT_TIMINGS:1; + bool ADD_CEA861_DETAILED_TIMING_VIC16:1; + bool ADD_CEA861_DETAILED_TIMING_VIC31:1; /* 30 bits*/ + bool DELAY_BEFORE_UNMUTE:1; + bool RETRY_LINK_TRAINING_ON_FAILURE:1; + bool ALLOW_AUX_WHEN_HPD_LOW:1; + bool TILED_DISPLAY:1; + bool DISABLE_PSR_ENTRY_ABORT:1; + bool INTERMITTENT_EDID_ERROR:1;/* 36 bits total*/ + bool VID_STREAM_DIFFER_TO_SYNC:1;/* 37 bits total*/ + bool EXTRA_DELAY_ON_DISCONNECT:1;/* 38 bits total*/ + bool DELAY_AFTER_DISABLE_BACKLIGHT_DFS_BYPASS:1;/* 39 bits total*/ + } flags; + uint64_t raw; +}; + +struct dcs_edid_supported_max_bw { + uint32_t pix_clock_khz; + uint32_t bits_per_pixel; +}; + +struct dcs_stereo_3d_features { + struct { +/* 3D Format supported by monitor (implies supported by driver)*/ + uint32_t SUPPORTED:1; +/* 3D Format supported on all timings +(no need to check every timing for 3D support)*/ + uint32_t ALL_TIMINGS:1; +/* 3D Format supported in clone mode*/ + uint32_t CLONE_MODE:1; +/* Scaling allowed when driving 3D Format*/ + uint32_t SCALING:1; +/* Left and right images packed by SW within single frame*/ + uint32_t SINGLE_FRAME_SW_PACKED:1; + } flags; +}; + +struct dcs_container_id { + /*128bit GUID in binary form*/ + uint8_t guid[16]; + /* 8 byte port ID -> ELD.PortID*/ + uint32_t port_id[2]; + /* 2 byte manufacturer name -> ELD.ManufacturerName*/ + uint16_t manufacturer_name; + /* 2 byte product code -> ELD.ProductCode*/ + uint16_t product_code; +}; + +struct dcs_display_tile { +/*unique Id of Tiled Display. 0 - means display is not part in Tiled Display*/ + uint64_t id; + uint32_t rows;/* size of Tiled Display in tiles*/ + uint32_t cols;/* size of Tiled Display in tiles*/ + uint32_t width;/* size of current Tile in pixels*/ + uint32_t height;/* size of current Tile in pixels*/ + uint32_t row;/* location of current Tile*/ + uint32_t col;/* location of current Tile*/ + struct { + /*in pixels*/ + uint32_t left; + uint32_t right; + uint32_t top; + uint32_t bottom; + } bezel;/* bezel information of current tile*/ + + struct { + uint32_t SEPARATE_ENCLOSURE:1; + uint32_t BEZEL_INFO_PRESENT:1; + uint32_t CAN_SCALE:1; + } flags; + + struct { + uint32_t manufacturer_id; + uint32_t product_id; + uint32_t serial_id; + } topology_id; +}; + +#endif /* __DAL_DCS_TYPES_H__ */ + diff --git a/drivers/gpu/drm/amd/dal/include/ddc_interface.h b/drivers/gpu/drm/amd/dal/include/ddc_interface.h new file mode 100644 index 000000000000..22fd31f6de7f --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/ddc_interface.h @@ -0,0 +1,74 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DDC_INTERFACE_H__ +#define __DAL_DDC_INTERFACE_H__ + +#include "gpio_types.h" + +struct ddc; + +enum gpio_result dal_ddc_open( + struct ddc *ddc, + enum gpio_mode mode, + enum gpio_ddc_config_type config_type); + +enum gpio_result dal_ddc_get_clock( + const struct ddc *ddc, + uint32_t *value); + +enum gpio_result dal_ddc_set_clock( + const struct ddc *ddc, + uint32_t value); + +enum gpio_result dal_ddc_get_data( + const struct ddc *ddc, + uint32_t *value); + +enum gpio_result dal_ddc_set_data( + const struct ddc *ddc, + uint32_t value); + +enum gpio_result dal_ddc_change_mode( + struct ddc *ddc, + enum gpio_mode mode); + +bool dal_ddc_is_hw_supported( + const struct ddc *ddc); + +enum gpio_ddc_line dal_ddc_get_line( + const struct ddc *ddc); + +bool dal_ddc_check_line_aborted( + const struct ddc *ddc); + +enum gpio_result dal_ddc_set_config( + struct ddc *ddc, + enum gpio_ddc_config_type config_type); + +void dal_ddc_close( + struct ddc *ddc); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/ddc_service_types.h b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h new file mode 100644 index 000000000000..cbdb6dfe4ff3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/ddc_service_types.h @@ -0,0 +1,221 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_DDC_SERVICE_TYPES_H__ +#define __DAL_DDC_SERVICE_TYPES_H__ + +#define DP_BRANCH_DEVICE_ID_1 0x0010FA +#define DP_BRANCH_DEVICE_ID_2 0x0022B9 +#define DP_SINK_DEVICE_ID_1 0x4CE000 +#define DP_BRANCH_DEVICE_ID_3 0x00001A +#define DP_BRANCH_DEVICE_ID_4 0x0080e1 +#define DP_BRANCH_DEVICE_ID_5 0x006037 +#define DP_SINK_DEVICE_ID_2 0x001CF8 + + +enum ddc_result { + DDC_RESULT_UNKNOWN = 0, + DDC_RESULT_SUCESSFULL, + DDC_RESULT_FAILED_CHANNEL_BUSY, + DDC_RESULT_FAILED_TIMEOUT, + DDC_RESULT_FAILED_PROTOCOL_ERROR, + DDC_RESULT_FAILED_NACK, + DDC_RESULT_FAILED_INCOMPLETE, + DDC_RESULT_FAILED_OPERATION, + DDC_RESULT_FAILED_INVALID_OPERATION, + DDC_RESULT_FAILED_BUFFER_OVERFLOW +}; + +enum ddc_service_type { + DDC_SERVICE_TYPE_CONNECTOR, + DDC_SERVICE_TYPE_DISPLAY_PORT_MST, +}; + +enum ddc_transaction_type { + DDC_TRANSACTION_TYPE_NONE = 0, + DDC_TRANSACTION_TYPE_I2C, + DDC_TRANSACTION_TYPE_I2C_OVER_AUX, + DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER, + DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER +}; + +enum display_dongle_type { + DISPLAY_DONGLE_NONE = 0, + /* Active converter types*/ + DISPLAY_DONGLE_DP_VGA_CONVERTER, + DISPLAY_DONGLE_DP_DVI_CONVERTER, + DISPLAY_DONGLE_DP_HDMI_CONVERTER, + /* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/ + DISPLAY_DONGLE_DP_DVI_DONGLE, + DISPLAY_DONGLE_DP_HDMI_DONGLE, + /* Other types of dongle*/ + DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE, +}; + +enum dcs_dpcd_revision { + DCS_DPCD_REV_10 = 0x10, + DCS_DPCD_REV_11 = 0x11, + DCS_DPCD_REV_12 = 0x12 +}; + +/** + * display sink capability + */ +struct display_sink_capability { + /* dongle type (DP converter, CV smart dongle) */ + enum display_dongle_type dongle_type; + + /********************************************************** + capabilities going INTO SINK DEVICE (stream capabilities) + **********************************************************/ + /* Dongle's downstream count. */ + uint32_t downstrm_sink_count; + /* Is dongle's downstream count info field (downstrm_sink_count) + * valid. */ + bool downstrm_sink_count_valid; + + /* Maximum additional audio delay in microsecond (us) */ + uint32_t additional_audio_delay; + /* Audio latency value in microsecond (us) */ + uint32_t audio_latency; + /* Interlace video latency value in microsecond (us) */ + uint32_t video_latency_interlace; + /* Progressive video latency value in microsecond (us) */ + uint32_t video_latency_progressive; + /* Dongle caps: Maximum pixel clock supported over dongle for HDMI */ + uint32_t max_hdmi_pixel_clock; + /* Dongle caps: Maximum deep color supported over dongle for HDMI */ + enum dc_color_depth max_hdmi_deep_color; + + /************************************************************ + capabilities going OUT OF SOURCE DEVICE (link capabilities) + ************************************************************/ + /* support for Spread Spectrum(SS) */ + bool ss_supported; + /* DP link settings (laneCount, linkRate, Spread) */ + uint32_t dp_link_lane_count; + uint32_t dp_link_rate; + uint32_t dp_link_spead; + + enum dcs_dpcd_revision dpcd_revision; + /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, + indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ + bool is_dp_hdmi_s3d_converter; + /* to check if we have queried the display capability + * for eDP panel already. */ + bool is_edp_sink_cap_valid; + + enum ddc_transaction_type transaction_type; + enum signal_type signal; +}; + +struct dp_receiver_id_info { + uint32_t dpcd_rev; + uint32_t sink_id; + int8_t sink_id_str[6]; + int8_t sink_hw_revision; + int8_t sink_fw_revision[2]; + uint32_t branch_id; + int8_t branch_name[6]; + enum display_dongle_type dongle_type; +}; + +struct av_sync_data { + uint8_t av_granularity;/* DPCD 00023h */ + uint8_t aud_dec_lat1;/* DPCD 00024h */ + uint8_t aud_dec_lat2;/* DPCD 00025h */ + uint8_t aud_pp_lat1;/* DPCD 00026h */ + uint8_t aud_pp_lat2;/* DPCD 00027h */ + uint8_t vid_inter_lat;/* DPCD 00028h */ + uint8_t vid_prog_lat;/* DPCD 00029h */ + uint8_t aud_del_ins1;/* DPCD 0002Bh */ + uint8_t aud_del_ins2;/* DPCD 0002Ch */ + uint8_t aud_del_ins3;/* DPCD 0002Dh */ +}; + +/** EDID retrieval related constants, also used by MstMgr **/ + +#define DDC_EDID_SEGMENT_SIZE 256 +#define DDC_EDID_BLOCK_SIZE 128 +#define DDC_EDID_BLOCKS_PER_SEGMENT \ + (DDC_EDID_SEGMENT_SIZE / DDC_EDID_BLOCK_SIZE) + +#define DDC_EDID_EXT_COUNT_OFFSET 0x7E + +#define DDC_EDID_ADDRESS_START 0x50 +#define DDC_EDID_ADDRESS_END 0x52 +#define DDC_EDID_SEGMENT_ADDRESS 0x30 + +/* signatures for Edid 1x */ +#define DDC_EDID1X_VENDORID_SIGNATURE_OFFSET 8 +#define DDC_EDID1X_VENDORID_SIGNATURE_LEN 4 +#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_OFFSET 126 +#define DDC_EDID1X_EXT_CNT_AND_CHECKSUM_LEN 2 +#define DDC_EDID1X_CHECKSUM_OFFSET 127 +/* signatures for Edid 20*/ +#define DDC_EDID_20_SIGNATURE_OFFSET 0 +#define DDC_EDID_20_SIGNATURE 0x20 + +#define DDC_EDID20_VENDORID_SIGNATURE_OFFSET 1 +#define DDC_EDID20_VENDORID_SIGNATURE_LEN 4 +#define DDC_EDID20_CHECKSUM_OFFSET 255 +#define DDC_EDID20_CHECKSUM_LEN 1 + +/*DP to VGA converter*/ +static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa"; +/*DP to Dual link DVI converter*/ +static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa"; +/*Travis*/ +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; +/*Nutmeg*/ +static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; +/*DP to VGA converter*/ +static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga"; +/*DP to Dual link DVI converter*/ +static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; +/*DP to Dual link DVI converter 2*/ +static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa"; + +static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0"; + +/* Identifies second generation PSR TCON from Parade: Device ID string: + * yy-xx-**-**-**-** + */ +/* xx - Hw ID high byte */ +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE = + 0x06; + +/* yy - HW ID low byte, the same silicon has several package/feature flavors */ +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 = + 0x61; +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 = + 0x62; +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 = + 0x63; +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 = + 0x72; +static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 = + 0x73; + +#endif /* __DAL_DDC_SERVICE_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h new file mode 100644 index 000000000000..211847cefe80 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h @@ -0,0 +1,186 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DISPLAY_CLOCK_INTERFACE_H__ +#define __DISPLAY_CLOCK_INTERFACE_H__ + +#include "hw_sequencer_types.h" +#include "grph_object_defs.h" +#include "signal_types.h" +#include "scaler_types.h" + +/* Timing related information*/ +struct dc_timing_params { + uint32_t INTERLACED:1; + uint32_t HCOUNT_BY_TWO:1; + uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/ + uint32_t PREFETCH:1; + + uint32_t h_total; + uint32_t h_addressable; + uint32_t h_sync_width; +}; + +/* Scaling related information*/ +struct dc_scaling_params { + uint32_t h_overscan_right; + uint32_t h_overscan_left; + uint32_t h_taps; + uint32_t v_taps; +}; + +/*Display Request Mode (1 and 2 valid when scaler is OFF)*/ +enum display_request_mode { + REQUEST_ONLY_AT_EVERY_READ_POINTER_INCREMENT = 0, + REQUEST_WAITING_FOR_THE_FIRST_READ_POINTER_ONLY, + REQUEST_WITHOUT_WAITING_FOR_READ_POINTER +}; + +/* FBC minimum CompressionRatio*/ +enum fbc_compression_ratio { + FBC_COMPRESSION_NOT_USED = 0, + FBC_MINIMUM_COMPRESSION_RATIO_1 = 1, + FBC_MINIMUM_COMPRESSION_RATIO_2 = 2, + FBC_MINIMUM_COMPRESSION_RATIO_4 = 4, + FBC_MINIMUM_COMPRESSION_RATIO_8 = 8 +}; + +/* VScalerEfficiency */ +enum v_scaler_efficiency { + V_SCALER_EFFICIENCY_LB36BPP = 0, + V_SCALER_EFFICIENCY_LB30BPP = 1, + V_SCALER_EFFICIENCY_LB24BPP = 2, + V_SCALER_EFFICIENCY_LB18BPP = 3 +}; + +/* Parameters required for minimum Engine + * and minimum Display clock calculations*/ +struct min_clock_params { + uint32_t id; + uint32_t requested_pixel_clock; /* in KHz */ + uint32_t actual_pixel_clock; /* in KHz */ + struct view source_view; + struct view dest_view; + struct dc_timing_params timing_info; + struct dc_scaling_params scaling_info; + struct color_quality color_info; + enum signal_type signal_type; + enum dc_color_depth deep_color_depth; + enum v_scaler_efficiency scaler_efficiency; + bool line_buffer_prefetch_enabled; +}; + +/* Enumerations for Source selection of the Display clock */ +enum display_clock_source_select { + USE_PIXEL_CLOCK_PLL = 0, + USE_EXTERNAL_CLOCK, + USE_ENGINE_CLOCK +}; + +/* Result of Minimum System and Display clock calculations. + * Minimum System clock and Display clock, source and path to be used + * for Display clock*/ +struct minimum_clocks_calculation_result { + uint32_t min_sclk_khz; + uint32_t min_dclk_khz; + uint32_t min_mclk_khz; + uint32_t min_deep_sleep_sclk; +}; + +/* Enumeration of all clocks states */ +enum clocks_state { + CLOCKS_STATE_INVALID, + CLOCKS_STATE_ULTRA_LOW, + CLOCKS_STATE_LOW, + CLOCKS_STATE_NOMINAL, + CLOCKS_STATE_PERFORMANCE +}; + +/* Structure containing all state-dependent clocks + * (dependent on "enum clocks_state") */ +struct state_dependent_clocks { + uint32_t display_clk_khz; + uint32_t pixel_clk_khz; +}; + +struct display_clock_state { + uint32_t DFS_BYPASS_ACTIVE:1; +}; + +struct display_clock; + +#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) +struct display_clock *dal_display_clock_dce110_create( + struct dc_context *ctx, + struct adapter_service *as); +#endif + +void dal_display_clock_destroy(struct display_clock **to_destroy); +bool dal_display_clock_validate( + struct display_clock *disp_clk, + struct min_clock_params *params); +uint32_t dal_display_clock_calculate_min_clock( + struct display_clock *disp_clk, + uint32_t path_num, + struct min_clock_params *params); +uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk); +void dal_display_clock_set_clock( + struct display_clock *disp_clk, + uint32_t requested_clock_khz); +uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk); +enum clocks_state dal_display_clock_get_min_clocks_state( + struct display_clock *disp_clk); +enum clocks_state dal_display_clock_get_required_clocks_state( + struct display_clock *disp_clk, + struct state_dependent_clocks *req_clocks); +bool dal_display_clock_set_min_clocks_state( + struct display_clock *disp_clk, + enum clocks_state clocks_state); +uint32_t dal_display_clock_get_dp_ref_clk_frequency( + struct display_clock *disp_clk); +/*the second parameter of "switchreferenceclock" is + * a dummy argument for all pre dce 6.0 versions*/ +void dal_display_clock_switch_reference_clock( + struct display_clock *disp_clk, + bool use_external_ref_clk, + uint32_t requested_clock_khz); +void dal_display_clock_set_dp_ref_clock_source( + struct display_clock *disp_clk, + enum clock_source_id clk_src); +void dal_display_clock_store_max_clocks_state( + struct display_clock *disp_clk, + enum clocks_state max_clocks_state); +void dal_display_clock_set_clock_state( + struct display_clock *disp_clk, + struct display_clock_state clk_state); +struct display_clock_state dal_display_clock_get_clock_state( + struct display_clock *disp_clk); +uint32_t dal_display_clock_get_dfs_bypass_threshold( + struct display_clock *disp_clk); +void dal_display_clock_invalid_clock_state( + struct display_clock *disp_clk); + + +#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/display_path_interface.h b/drivers/gpu/drm/amd/dal/include/display_path_interface.h new file mode 100644 index 000000000000..7bf2ef28f455 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/display_path_interface.h @@ -0,0 +1,436 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DISPLAY_PATH_INTERFACE_H__ +#define __DISPLAY_PATH_INTERFACE_H__ + +#include "display_path_types.h" +#include "dcs_types.h" +#include "grph_object_ctrl_defs.h" +#include "signal_types.h" +#include "controller_types.h" + +struct encoder; +struct controller; +struct connector; +struct audio; +struct clock_source; +struct link_service; +struct goc_link_service_data; +struct drr_config; + +struct display_path; + +struct display_path *dal_display_path_create(void); + +struct display_path *dal_display_path_clone( + const struct display_path *self, + bool copy_active_state); + +void dal_display_path_destroy( + struct display_path **to_destroy); + +bool dal_display_path_validate( + struct display_path *path, + enum signal_type sink_signal); + +bool dal_display_path_add_link( + struct display_path *path, + struct encoder *encoder); + +bool dal_display_path_add_connector( + struct display_path *path, + struct connector *connector); + +struct connector *dal_display_path_get_connector( + struct display_path *path); + +int32_t dal_display_path_acquire( + struct display_path *path); + +bool dal_display_path_is_acquired( + const struct display_path *path); + +int32_t dal_display_path_get_ref_counter( + const struct display_path *path); + +int32_t dal_display_path_release( + struct display_path *path); + +void dal_display_path_release_resources( + struct display_path *path); + +void dal_display_path_acquire_links( + struct display_path *path); + +bool dal_display_path_is_source_blanked( + const struct display_path *path); + +bool dal_display_path_is_source_unblanked( + const struct display_path *path); + +void dal_display_path_set_source_blanked( + struct display_path *path, + enum display_tri_state state); + +bool dal_display_path_is_target_blanked( + const struct display_path *path); + +bool dal_display_path_is_target_unblanked( + const struct display_path *path); + +void dal_display_path_set_target_blanked( + struct display_path *path, + enum display_tri_state state); + +bool dal_display_path_is_target_powered_on( + const struct display_path *path); + +bool dal_display_path_is_target_powered_off( + const struct display_path *path); + +void dal_display_path_set_target_powered_on( + struct display_path *path, + enum display_tri_state state); + +bool dal_display_path_is_target_connected( + const struct display_path *path); + +void dal_display_path_set_target_connected( + struct display_path *path, + bool c); + +uint32_t dal_display_path_get_display_index( + const struct display_path *path); + +void dal_display_path_set_display_index( + struct display_path *path, + uint32_t index); + +struct connector_device_tag_info *dal_display_path_get_device_tag( + struct display_path *path); + +void dal_display_path_set_device_tag( + struct display_path *path, + struct connector_device_tag_info tag); + +enum clock_sharing_group dal_display_path_get_clock_sharing_group( + const struct display_path *path); + +void dal_display_path_set_clock_sharing_group( + struct display_path *path, + enum clock_sharing_group clock); + +union display_path_properties dal_display_path_get_properties( + const struct display_path *path); + +void dal_display_path_set_properties( + struct display_path *path, + union display_path_properties p); + +struct dcs *dal_display_path_get_dcs( + const struct display_path *path); + +void dal_display_path_set_dcs( + struct display_path *path, + struct dcs *dcs); + +uint32_t dal_display_path_get_number_of_links( + const struct display_path *path); + +void dal_display_path_set_controller( + struct display_path *path, + struct controller *controller); + +struct controller *dal_display_path_get_controller( + const struct display_path *path); + +void dal_display_path_set_clock_source( + struct display_path *path, + struct clock_source *clock); + +struct clock_source *dal_display_path_get_clock_source( + const struct display_path *path); + +void dal_display_path_set_alt_clock_source( + struct display_path *path, + struct clock_source *clock); + +struct clock_source *dal_display_path_get_alt_clock_source( + const struct display_path *path); + +void dal_display_path_set_fbc_info( + struct display_path *path, + struct fbc_info *clock); + +struct fbc_info *dal_display_path_get_fbc_info( + struct display_path *path); + +void dal_display_path_set_drr_config( + struct display_path *path, + struct drr_config *clock); + +void dal_display_path_get_drr_config( + const struct display_path *path, + struct drr_config *clock); + +void dal_display_path_set_static_screen_triggers( + struct display_path *path, + const struct static_screen_events *events); + +void dal_display_path_get_static_screen_triggers( + const struct display_path *path, + struct static_screen_events *events); + +bool dal_display_path_is_psr_supported( + const struct display_path *path); + +bool dal_display_path_is_drr_supported( + const struct display_path *path); + +void dal_display_path_set_link_service_data( + struct display_path *path, + uint32_t idx, + const struct goc_link_service_data *data); + +bool dal_display_path_get_link_service_data( + const struct display_path *path, + uint32_t idx, + struct goc_link_service_data *data); + +struct link_service *dal_display_path_get_link_query_interface( + const struct display_path *path, + uint32_t idx); + +void dal_display_path_set_link_query_interface( + struct display_path *path, + uint32_t idx, + struct link_service *link); + +struct link_service *dal_display_path_get_link_config_interface( + const struct display_path *path, + uint32_t idx); + +struct link_service *dal_display_path_get_link_service_interface( + const struct display_path *path, + uint32_t idx); + +struct encoder *dal_display_path_get_upstream_encoder( + const struct display_path *path, + uint32_t idx); + +struct encoder *dal_display_path_get_upstream_object( + const struct display_path *path, + uint32_t idx); + +struct encoder *dal_display_path_get_downstream_encoder( + const struct display_path *path, + uint32_t idx); + +struct encoder *dal_display_path_get_downstream_object( + const struct display_path *path, + uint32_t idx); + +struct audio *dal_display_path_get_audio( + const struct display_path *path, + uint32_t idx); + +void dal_display_path_set_audio( + struct display_path *path, + uint32_t idx, + struct audio *a); + +struct audio *dal_display_path_get_audio_object( + const struct display_path *path, + uint32_t idx); + +void dal_display_path_set_audio_active_state( + struct display_path *path, + uint32_t idx, + bool state); + +enum engine_id dal_display_path_get_stream_engine( + const struct display_path *path, + uint32_t idx); + +void dal_display_path_set_stream_engine( + struct display_path *path, + uint32_t idx, + enum engine_id id); + +bool dal_display_path_is_link_active( + const struct display_path *path, + uint32_t idx); + +void dal_display_path_set_link_active_state( + struct display_path *path, + uint32_t idx, + bool state); + +enum signal_type dal_display_path_get_config_signal( + const struct display_path *path, + uint32_t idx); + +enum signal_type dal_display_path_get_query_signal( + const struct display_path *path, + uint32_t idx); + +struct link_service *dal_display_path_get_mst_link_service( + const struct display_path *path); + +void dal_display_path_set_sync_output_object( + struct display_path *path, + enum sync_source o_source, + struct encoder *o_object); + +struct encoder *dal_display_path_get_sync_output_object( + const struct display_path *path); + +void dal_display_path_set_stereo_sync_object( + struct display_path *path, + struct encoder *stereo_sync); + +struct encoder *dal_display_path_get_stereo_sync_object( + const struct display_path *path); + +void dal_display_path_set_sync_input_source( + struct display_path *path, + enum sync_source s); + +enum sync_source dal_display_path_get_sync_input_source( + const struct display_path *path); + +void dal_display_path_set_sync_output_source( + struct display_path *path, + enum sync_source s); + +enum sync_source dal_display_path_get_sync_output_source( + const struct display_path *path); + +bool dal_display_path_set_pixel_clock_safe_range( + struct display_path *path, + struct pixel_clock_safe_range *range); + +bool dal_display_path_get_pixel_clock_safe_range( + const struct display_path *path, + struct pixel_clock_safe_range *range); + +void dal_display_path_set_ddi_channel_mapping( + struct display_path *path, + union ddi_channel_mapping mapping); + +bool dal_display_path_set_sink_signal( + struct display_path *path, + enum signal_type sink_signal); + +enum signal_type dal_display_path_sink_signal_to_asic_signal( + struct display_path *path, + enum signal_type sink_signal); + +enum signal_type dal_display_path_sink_signal_to_link_signal( + struct display_path *path, + enum signal_type sink_signal, + uint32_t idx); + +enum signal_type dal_display_path_downstream_to_upstream_signal( + struct display_path *path, + enum signal_type signal, + uint32_t idx); + +bool dal_display_path_is_audio_present( + const struct display_path *path, + uint32_t *audio_pin); + +bool dal_display_path_is_dp_auth_supported( + struct display_path *path); + +bool dal_display_path_is_vce_supported( + const struct display_path *path); + +bool dal_display_path_is_sls_capable( + const struct display_path *path); + +bool dal_display_path_is_gen_lock_capable( + const struct display_path *path); + +struct transmitter_configuration dal_display_path_get_transmitter_configuration( + const struct display_path *path, + bool physical); + +bool dal_display_path_is_ss_supported( + const struct display_path *path); + +bool dal_display_path_is_ss_configurable( + const struct display_path *path); + +void dal_display_path_set_ss_support( + struct display_path *path, + bool s); + +enum signal_type dal_display_path_get_active_signal( + struct display_path *path, + uint32_t idx); + +bool dal_display_path_contains_object( + struct display_path *path, + struct graphics_object_id id); + +/* Multi-plane declarations. + * This structure should also be used for Stereo. */ +struct display_path_plane { + struct controller *controller; + /* During dal_tm_acquire_plane_resources() set blnd_mode, because + * "layer index" is known at that point, and we must decide how + * "controller" should do the blending */ + enum blender_mode blnd_mode; + /* Some use-cases allow to power-gate FE. + * For example, with Full Screen Video on Underlay we can + * disable the 'root' plane. + * This flag indicates that FE should be power-gated */ + bool disabled; +}; + +bool dal_display_path_add_plane( + struct display_path *path, + struct display_path_plane *plane); + +uint8_t dal_display_path_get_number_of_planes( + const struct display_path *path); + +struct display_path_plane *dal_display_path_get_plane_at_index( + const struct display_path *path, + uint8_t index); + +struct controller *dal_display_path_get_controller_for_layer_index( + const struct display_path *path, + uint8_t layer_index); + +void dal_display_path_release_planes( + struct display_path *path); + +void dal_display_path_release_non_root_planes( + struct display_path *path); + +#endif /* __DISPLAY_PATH_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_interface.h b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h new file mode 100644 index 000000000000..c712cc25e731 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dmcu_interface.h @@ -0,0 +1,87 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DMCU_INTERFACE_H__ +#define __DAL_DMCU_INTERFACE_H__ + +#include "grph_object_defs.h" +#include "dmcu_types.h" + +/* Interface functions */ + +/* DMCU setup related interface functions */ +struct dmcu *dal_dmcu_create( + struct dmcu_init_data *init_data); +void dal_dmcu_destroy(struct dmcu **dmcu); +void dal_dmcu_release_hw(struct dmcu *dmcu); + +void dal_dmcu_power_up(struct dmcu *dmcu); +void dal_dmcu_power_down(struct dmcu *dmcu); + +void dal_dmcu_configure_wait_loop( + struct dmcu *dmcu, + uint32_t display_clock); + +/* PSR feature related interface functions */ +void dal_dmcu_psr_setup( + struct dmcu *dmcu, + struct dmcu_context *dmcu_context); +void dal_dmcu_psr_enable(struct dmcu *dmcu); +void dal_dmcu_psr_disable(struct dmcu *dmcu); +void dal_dmcu_psr_block(struct dmcu *dmcu, bool block_psr); +bool dal_dmcu_psr_is_blocked(struct dmcu *dmcu); +void dal_dmcu_psr_set_level( + struct dmcu *dmcu, + union dmcu_psr_level psr_level); +void dal_dmcu_psr_allow_power_down_crtc( + struct dmcu *dmcu, + bool should_allow_crtc_power_down); +bool dal_dmcu_psr_submit_command( + struct dmcu *dmcu, + struct dmcu_context *dmcu_context, + struct dmcu_config_data *config_data); +void dal_dmcu_psr_get_config_data( + struct dmcu *dmcu, + uint32_t v_total, + struct dmcu_config_data *config_data); + +/* ABM feature related interface functions */ +void dal_dmcu_abm_enable( + struct dmcu *dmcu, + enum controller_id controller_id, + uint32_t vsync_rate_hz); +void dal_dmcu_abm_disable(struct dmcu *dmcu); +bool dal_dmcu_abm_enable_smooth_brightness(struct dmcu *dmcu); +bool dal_dmcu_abm_disable_smooth_brightness(struct dmcu *dmcu); +void dal_dmcu_abm_varibright_control( + struct dmcu *dmcu, + const struct varibright_control *varibright_control); +bool dal_dmcu_abm_set_backlight_level( + struct dmcu *dmcu, + uint8_t backlight_8_bit); +uint8_t dal_dmcu_abm_get_user_backlight_level(struct dmcu *dmcu); +uint8_t dal_dmcu_abm_get_current_backlight_level(struct dmcu *dmcu); + +#endif /* __DAL_DMCU_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dmcu_types.h b/drivers/gpu/drm/amd/dal/include/dmcu_types.h new file mode 100644 index 000000000000..1f3107d5b9b8 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dmcu_types.h @@ -0,0 +1,199 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DMCU_TYPES_H__ +#define __DAL_DMCU_TYPES_H__ + +/* Forward declaration */ +struct dmcu; + +/* Required information for creation and initialization of a controller */ +struct dmcu_init_data { + struct dal_context *dal_context; + struct adapter_service *as; + uint32_t max_engine_clock_in_khz; +}; + +/* Interface structure defines */ + +enum dmcu_action { + DMCU_ACTION_PSR_ENABLE, + DMCU_ACTION_PSR_EXIT, + DMCU_ACTION_PSR_RFB_UPDATE, + DMCU_ACTION_PSR_SET, + DMCU_ACTION_PSR_CLEAR_COUNT, + DMCU_ACTION_PSR_COUNT_REQUEST, + DMCU_ACTION_PSR_STATE_REQUEST, + DMCU_ACTION_PSR_SET_LEVEL, + DMCU_ACTION_PSR_ADVANCE_STATE, + DMCU_ACTION_PSR_SET_WAITLOOP +}; + +enum dmcu_output { + DMCU_OUTPUT_PSR_ACK, + DMCU_OUTPUT_PSR_NACK, + DMCU_OUTPUT_PSR_AUX_ERR, + DMCU_OUTPUT_PSR_COUNT_STATUS, + DMCU_OUTPUT_PSR_STATE_STATUS, + DMCU_OUTPUT_PSR_RFB_UPDATE_ERR, + DMCU_OUTPUT_PSR_ERR, + DMCU_OUTPUT_PSR_GET_REPLY, + DMCU_OUTPUT_PSR_ENTRY_ERROR, + DMCU_OUTPUT_PSR_LT_ERROR, + DMCU_OUTPUT_PSR_FORCE_SR_ERROR, + DMCU_OUTPUT_PSR_SDP_SEND_TIMEOUT +}; + +/* PSR states, based similarly on states defined in eDP specification. */ +enum psr_state { + STATE0, /* PSR is disabled */ + STATE1, /* PSR is enabled, but inactive */ + STATE1A, + STATE2, /* PSR is transitioning to active state */ + STATE2A, + STATE3, /* PSR is active; Display is in self refresh */ + STATE3INIT, + STATE4, /* RFB single frame update */ + STATE4A, + STATE4B, + STATE4C, + STATE4D, + STATE5, /* Exiting from PSR active state */ + STATE5A, + STATE5B, + STATE5C +}; + +enum phy_type { + PHY_TYPE_UNKNOWN = 1, + PHY_TYPE_PCIE_PHY = 2, + PHY_TYPE_UNIPHY = 3, +}; + +struct dmcu_context { + enum channel_id channel; + enum transmitter transmitter_id; + enum engine_id engine_id; + enum controller_id controller_id; + enum phy_type phy_type; + enum physical_phy_id smu_physical_phy_id; + + /* Vertical total pixels from crtc timing. + * This is used for static screen detection. + * ie. If we want to detect half a frame, + * we use this to determine the hyst lines.*/ + uint32_t crtc_timing_vertical_total; + + /* PSR supported from panel capabilities + * and current display configuration */ + bool psr_supported_display_config; + + /* Whether fast link training is supported by the panel */ + bool psr_exit_link_training_required; + + /* If RFB setup time is greater than the total VBLANK time, it is not + * possible for the sink to capture the video frame in the same frame + * the SDP is sent. In this case, the frame capture indication bit + * should be set and an extra static frame should be transmitted to + * the sink */ + bool psr_frame_capture_indication_required; + + /* Set the last possible line SDP may be transmitted without violating + * the RFB setup time */ + bool sdp_transmit_line_num_deadline; + + /* The VSync rate in Hz used to calculate the step size + * for smooth brightness feature */ + uint32_t vsync_rate_hz; +}; + +union dmcu_psr_level { + struct { + bool SKIP_CRC:1; + bool SKIP_DP_VID_STREAM_DISABLE:1; + bool SKIP_PHY_POWER_DOWN:1; + bool SKIP_AUX_ACK_CHECK:1; + bool SKIP_CRTC_DISABLE:1; + bool SKIP_AUX_RFB_CAPTURE_CHECK:1; + bool SKIP_SMU_NOTIFICATION:1; + bool SKIP_AUTO_STATE_ADVANCE:1; + bool DISABLE_PSR_ENTRY_ABORT:1; + } bits; + uint32_t u32all; +}; + +struct dmcu_config_data { + /* Command sent to DMCU. */ + enum dmcu_action action; + /* PSR Level controls which HW blocks to power down during PSR active, + * and also other sequence modifications. */ + union dmcu_psr_level psr_level; + /* To indicate that first changed frame from active state should not + * result in exit to inactive state, but instead perform an automatic + * single frame RFB update. */ + bool rfb_update_auto_en; + /* Number of consecutive static frames to detect before entering PSR + * active state. */ + uint32_t hyst_frames; + /* Partial frames before entering PSR active. Note this parameter is in + * units of 100 lines. i.e. Wait a value of 5 means wait 500 additional + * lines. */ + uint32_t hyst_lines; + /* Number of repeated AUX retries before indicating failure to driver. + * In a working case, first attempt to write/read AUX should pass. */ + uint32_t aux_repeat; + /* Additional delay after remote frame capture before continuing to + * power down. This is mainly for debug purposes to identify timing + * issues. */ + uint32_t frame_delay; + /* Controls how long the delay of a wait loop is. It should be tuned + * to 1 us, and needs to be reconfigured every time DISPCLK changes. */ + uint32_t wait_loop_num; +}; + +struct dmcu_output_data { + /* DMCU reply */ + enum dmcu_output output; + /* The current PSR state. */ + uint32_t psr_state; + /* The number of frames during PSR active state. */ + uint32_t psr_count; +}; + +enum varibright_command { + VARIBRIGHT_CMD_SET_VB_LEVEL = 0, + VARIBRIGHT_CMD_USER_ENABLE, + VARIBRIGHT_CMD_POST_DISPLAY_CONFIG, + VARIBRIGHT_CMD_UNKNOWN +}; + +struct varibright_control { + enum varibright_command command; + uint8_t level; + bool enable; + bool activate; +}; + +#endif /* __DAL_DMCU_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/dpcd_defs.h b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h new file mode 100644 index 000000000000..bd410ccdc3a5 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/dpcd_defs.h @@ -0,0 +1,873 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DPCD_DEFS_H__ +#define __DAL_DPCD_DEFS_H__ + +enum dpcd_address { +/* addresses marked with 1.2 are only defined since DP 1.2 spec */ + + /* Reciever Capability Field */ + DPCD_ADDRESS_DPCD_REV = 0x00000, + DPCD_ADDRESS_MAX_LINK_RATE = 0x00001, + DPCD_ADDRESS_MAX_LANE_COUNT = 0x00002, + DPCD_ADDRESS_MAX_DOWNSPREAD = 0x00003, + DPCD_ADDRESS_NORP = 0x00004, + DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT = 0x00005, + DPCD_ADDRESS_MAIN_LINK_CHANNEL_CODING = 0x00006, + DPCD_ADDRESS_DOWNSTREAM_PORT_COUNT = 0x00007, + DPCD_ADDRESS_RECEIVE_PORT0_CAP0 = 0x00008, + DPCD_ADDRESS_RECEIVE_PORT0_CAP1 = 0x00009, + DPCD_ADDRESS_RECEIVE_PORT1_CAP0 = 0x0000A, + DPCD_ADDRESS_RECEIVE_PORT1_CAP1 = 0x0000B, + + DPCD_ADDRESS_I2C_SPEED_CNTL_CAP = 0x0000C,/*1.2*/ + DPCD_ADDRESS_EDP_CONFIG_CAP = 0x0000D,/*1.2*/ + DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL = 0x000E,/*1.2*/ + + DPCD_ADDRESS_MSTM_CAP = 0x00021,/*1.2*/ + + /* Audio Video Sync Data Feild */ + DPCD_ADDRESS_AV_GRANULARITY = 0x0023, + DPCD_ADDRESS_AUDIO_DECODE_LATENCY1 = 0x0024, + DPCD_ADDRESS_AUDIO_DECODE_LATENCY2 = 0x0025, + DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY1 = 0x0026, + DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY2 = 0x0027, + DPCD_ADDRESS_VIDEO_INTERLACED_LATENCY = 0x0028, + DPCD_ADDRESS_VIDEO_PROGRESSIVE_LATENCY = 0x0029, + DPCD_ADDRESS_AUDIO_DELAY_INSERT1 = 0x0002B, + DPCD_ADDRESS_AUDIO_DELAY_INSERT2 = 0x0002C, + DPCD_ADDRESS_AUDIO_DELAY_INSERT3 = 0x0002D, + + /* Audio capability */ + DPCD_ADDRESS_NUM_OF_AUDIO_ENDPOINTS = 0x00022, + + DPCD_ADDRESS_GUID_START = 0x00030,/*1.2*/ + DPCD_ADDRESS_GUID_END = 0x0003f,/*1.2*/ + + DPCD_ADDRESS_PSR_SUPPORT_VER = 0x00070, + DPCD_ADDRESS_PSR_CAPABILITY = 0x00071, + + DPCD_ADDRESS_DWN_STRM_PORT0_CAPS = 0x00080,/*1.2a*/ + + /* Link Configuration Field */ + DPCD_ADDRESS_LINK_BW_SET = 0x00100, + DPCD_ADDRESS_LANE_COUNT_SET = 0x00101, + DPCD_ADDRESS_TRAINING_PATTERN_SET = 0x00102, + DPCD_ADDRESS_LANE0_SET = 0x00103, + DPCD_ADDRESS_LANE1_SET = 0x00104, + DPCD_ADDRESS_LANE2_SET = 0x00105, + DPCD_ADDRESS_LANE3_SET = 0x00106, + DPCD_ADDRESS_DOWNSPREAD_CNTL = 0x00107, + DPCD_ADDRESS_I2C_SPEED_CNTL = 0x00109,/*1.2*/ + + DPCD_ADDRESS_EDP_CONFIG_SET = 0x0010A, + DPCD_ADDRESS_LINK_QUAL_LANE0_SET = 0x0010B, + DPCD_ADDRESS_LINK_QUAL_LANE1_SET = 0x0010C, + DPCD_ADDRESS_LINK_QUAL_LANE2_SET = 0x0010D, + DPCD_ADDRESS_LINK_QUAL_LANE3_SET = 0x0010E, + + DPCD_ADDRESS_LANE0_SET2 = 0x0010F,/*1.2*/ + DPCD_ADDRESS_LANE2_SET2 = 0x00110,/*1.2*/ + + DPCD_ADDRESS_MSTM_CNTL = 0x00111,/*1.2*/ + + DPCD_ADDRESS_PSR_ENABLE_CFG = 0x0170, + + /* Payload Table Configuration Field 1.2 */ + DPCD_ADDRESS_PAYLOAD_ALLOCATE_SET = 0x001C0, + DPCD_ADDRESS_PAYLOAD_ALLOCATE_START_TIMESLOT = 0x001C1, + DPCD_ADDRESS_PAYLOAD_ALLOCATE_TIMESLOT_COUNT = 0x001C2, + + DPCD_ADDRESS_SINK_COUNT = 0x0200, + DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR = 0x0201, + + /* Link / Sink Status Field */ + DPCD_ADDRESS_LANE_01_STATUS = 0x00202, + DPCD_ADDRESS_LANE_23_STATUS = 0x00203, + DPCD_ADDRESS_LANE_ALIGN_STATUS_UPDATED = 0x0204, + DPCD_ADDRESS_SINK_STATUS = 0x0205, + + /* Adjust Request Field */ + DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1 = 0x0206, + DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3 = 0x0207, + DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2 = 0x020C, + + /* Test Request Field */ + DPCD_ADDRESS_TEST_REQUEST = 0x0218, + DPCD_ADDRESS_TEST_LINK_RATE = 0x0219, + DPCD_ADDRESS_TEST_LANE_COUNT = 0x0220, + DPCD_ADDRESS_TEST_PATTERN = 0x0221, + DPCD_ADDRESS_TEST_MISC1 = 0x0232, + + /* Phy Test Pattern Field */ + DPCD_ADDRESS_TEST_PHY_PATTERN = 0x0248, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0 = 0x0250, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_15_8 = 0x0251, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_23_16 = 0x0252, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_31_24 = 0x0253, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_39_32 = 0x0254, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_47_40 = 0x0255, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_55_48 = 0x0256, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_63_56 = 0x0257, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_71_64 = 0x0258, + DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 = 0x0259, + + /* Test Response Field*/ + DPCD_ADDRESS_TEST_RESPONSE = 0x0260, + + /* Audio Test Pattern Field 1.2*/ + DPCD_ADDRESS_TEST_AUDIO_MODE = 0x0271, + DPCD_ADDRESS_TEST_AUDIO_PATTERN_TYPE = 0x0272, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_1 = 0x0273, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_2 = 0x0274, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_3 = 0x0275, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_4 = 0x0276, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_5 = 0x0277, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_6 = 0x0278, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_7 = 0x0279, + DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_8 = 0x027A, + + /* Payload Table Status Field */ + DPCD_ADDRESS_PAYLOAD_TABLE_UPDATE_STATUS = 0x002C0,/*1.2*/ + DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT1 = 0x002C1,/*1.2*/ + DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT63 = 0x002FF,/*1.2*/ + + /* Source Device Specific Field */ + DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300, + DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301, + DPCD_ADDRESS_AMD_INTERNAL_DEBUG_START = 0x030C, + DPCD_ADDRESS_AMD_INTERNAL_DEBUG_END = 0x030F, + DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_START = 0x0310, + DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_END = 0x037F, + DPCD_ADDRESS_SOURCE_RESERVED_START = 0x0380, + DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF, + + /* Sink Device Specific Field */ + DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400, + DPCD_ADDRESS_SINK_DEVICE_ID_END = 0x0402, + DPCD_ADDRESS_SINK_DEVICE_STR_START = 0x0403, + DPCD_ADDRESS_SINK_DEVICE_STR_END = 0x0408, + DPCD_ADDRESS_SINK_REVISION_START = 0x409, + DPCD_ADDRESS_SINK_REVISION_END = 0x40B, + + /* Branch Device Specific Field */ + DPCD_ADDRESS_BRANCH_DEVICE_ID_START = 0x0500, + DPCD_ADDRESS_BRANCH_DEVICE_ID_END = 0x0502, + DPCD_ADDRESS_BRANCH_DEVICE_STR_START = 0x0503, + DPCD_ADDRESS_BRANCH_DEVICE_STR_END = 0x0508, + + DPCD_ADDRESS_POWER_STATE = 0x0600, + + /* EDP related */ + DPCD_ADDRESS_EDP_REV = 0x0700, + DPCD_ADDRESS_EDP_CAPABILITY = 0x0701, + DPCD_ADDRESS_EDP_BACKLIGHT_ADJUST_CAP = 0x0702, + DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703, + + DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720, + DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721, + DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722, + DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723, + DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT = 0x0724, + DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MIN = 0x0725, + DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MAX = 0x0726, + DPCD_ADDRESS_EDP_BACKLIGHT_CONTROL_STATUS = 0x0727, + DPCD_ADDRESS_EDP_BACKLIGHT_FREQ_SET = 0x0728, + DPCD_ADDRESS_EDP_REVERVED = 0x0729, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MSB = 0x072A, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MID = 0x072B, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_LSB = 0x072C, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MSB = 0x072D, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MID = 0x072E, + DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_LSB = 0x072F, + + DPCD_ADDRESS_EDP_DBC_MINIMUM_BRIGHTNESS_SET = 0x0732, + DPCD_ADDRESS_EDP_DBC_MAXIMUM_BRIGHTNESS_SET = 0x0733, + + /* Sideband MSG Buffers 1.2 */ + DPCD_ADDRESS_DOWN_REQ_START = 0x01000, + DPCD_ADDRESS_DOWN_REQ_END = 0x011ff, + + DPCD_ADDRESS_UP_REP_START = 0x01200, + DPCD_ADDRESS_UP_REP_END = 0x013ff, + + DPCD_ADDRESS_DOWN_REP_START = 0x01400, + DPCD_ADDRESS_DOWN_REP_END = 0x015ff, + + DPCD_ADDRESS_UP_REQ_START = 0x01600, + DPCD_ADDRESS_UP_REQ_END = 0x017ff, + + /* ESI (Event Status Indicator) Field 1.2 */ + DPCD_ADDRESS_SINK_COUNT_ESI = 0x02002, + DPCD_ADDRESS_DEVICE_IRQ_ESI0 = 0x02003, + DPCD_ADDRESS_DEVICE_IRQ_ESI1 = 0x02004, + /*@todo move dpcd_address_Lane01Status back here*/ + + DPCD_ADDRESS_PSR_ERROR_STATUS = 0x2006, + DPCD_ADDRESS_PSR_EVENT_STATUS = 0x2007, + DPCD_ADDRESS_PSR_SINK_STATUS = 0x2008, + DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009, + DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A, + + /* Travis specific addresses */ + DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0, + DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET = 0x5f1, + DPCD_ADDRESS_TRAVIS_SINK_ACCESS_REG = 0x5f2, +}; + +enum dpcd_revision { + DPCD_REV_10 = 0x10, + DPCD_REV_11 = 0x11, + DPCD_REV_12 = 0x12 +}; + +enum dp_pwr_state { + DP_PWR_STATE_D0 = 1,/* direct HW translation! */ + DP_PWR_STATE_D3 +}; + +/* these are the types stored at DOWNSTREAMPORT_PRESENT */ +enum dpcd_downstream_port_type { + DOWNSTREAM_DP = 0, + DOWNSTREAM_VGA, + DOWNSTREAM_DVI_HDMI, + DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ +}; + +enum dpcd_link_test_patterns { + LINK_TEST_PATTERN_NONE = 0, + LINK_TEST_PATTERN_COLOR_RAMP, + LINK_TEST_PATTERN_VERTICAL_BARS, + LINK_TEST_PATTERN_COLOR_SQUARES +}; + +enum dpcd_test_color_format { + TEST_COLOR_FORMAT_RGB = 0, + TEST_COLOR_FORMAT_YCBCR422, + TEST_COLOR_FORMAT_YCBCR444 +}; + +enum dpcd_test_bit_depth { + TEST_BIT_DEPTH_6 = 0, + TEST_BIT_DEPTH_8, + TEST_BIT_DEPTH_10, + TEST_BIT_DEPTH_12, + TEST_BIT_DEPTH_16 +}; + +/* PHY (encoder) test patterns +The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) */ +enum dpcd_phy_test_patterns { + PHY_TEST_PATTERN_NONE = 0, + PHY_TEST_PATTERN_D10_2, + PHY_TEST_PATTERN_SYMBOL_ERROR, + PHY_TEST_PATTERN_PRBS7, + PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ + PHY_TEST_PATTERN_HBR2_COMPLIANCE_EYE/* For DP1.2 only */ +}; + +enum dpcd_test_dyn_range { + TEST_DYN_RANGE_VESA = 0, + TEST_DYN_RANGE_CEA +}; + +enum dpcd_audio_test_pattern { + AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ + AUDIO_TEST_PATTERN_SAWTOOTH +}; + +enum dpcd_audio_sampling_rate { + AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ + AUDIO_SAMPLING_RATE_44_1KHZ, + AUDIO_SAMPLING_RATE_48KHZ, + AUDIO_SAMPLING_RATE_88_2KHZ, + AUDIO_SAMPLING_RATE_96KHZ, + AUDIO_SAMPLING_RATE_176_4KHZ, + AUDIO_SAMPLING_RATE_192KHZ +}; + +enum dpcd_audio_channels { + AUDIO_CHANNELS_1 = 0,/* direct HW translation */ + AUDIO_CHANNELS_2, + AUDIO_CHANNELS_3, + AUDIO_CHANNELS_4, + AUDIO_CHANNELS_5, + AUDIO_CHANNELS_6, + AUDIO_CHANNELS_7, + AUDIO_CHANNELS_8, + + AUDIO_CHANNELS_COUNT +}; + +enum dpcd_audio_test_pattern_periods { + DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ + DPCD_AUDIO_TEST_PATTERN_PERIOD_3, + DPCD_AUDIO_TEST_PATTERN_PERIOD_6, + DPCD_AUDIO_TEST_PATTERN_PERIOD_12, + DPCD_AUDIO_TEST_PATTERN_PERIOD_24, + DPCD_AUDIO_TEST_PATTERN_PERIOD_48, + DPCD_AUDIO_TEST_PATTERN_PERIOD_96, + DPCD_AUDIO_TEST_PATTERN_PERIOD_192, + DPCD_AUDIO_TEST_PATTERN_PERIOD_384, + DPCD_AUDIO_TEST_PATTERN_PERIOD_768, + DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 +}; + +/* This enum is for programming DPCD TRAINING_PATTERN_SET */ +enum dpcd_training_patterns { + DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ + DPCD_TRAINING_PATTERN_1, + DPCD_TRAINING_PATTERN_2, + DPCD_TRAINING_PATTERN_3 +}; + +/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus +It defines the possible PSR states. */ +enum dpcd_psr_sink_states { + PSR_SINK_STATE_INACTIVE = 0, + PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, + PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, + PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, + PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, + PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, +}; + +/* This enum defines the Panel's eDP revision at DPCD 700h + * 00h = eDP v1.1 or lower + * 01h = eDP v1.2 + * 02h = eDP v1.3 (PSR support starts here) + * 03h = eDP v1.4 + * If unknown revision, treat as eDP v1.1, meaning least functionality set. + * This enum has values matched to eDP spec, thus values should not change. + */ +enum dpcd_edp_revision { + DPCD_EDP_REVISION_EDP_V1_1 = 0, + DPCD_EDP_REVISION_EDP_V1_2 = 1, + DPCD_EDP_REVISION_EDP_V1_3 = 2, + DPCD_EDP_REVISION_EDP_V1_4 = 3, + DPCD_EDP_REVISION_EDP_UNKNOWN = DPCD_EDP_REVISION_EDP_V1_1, +}; + +union dpcd_rev { + struct { + uint8_t MINOR:4; + uint8_t MAJOR:4; + } bits; + uint8_t raw; +}; + +union max_lane_count { + struct { + uint8_t MAX_LANE_COUNT:5; + uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; + uint8_t TPS3_SUPPORTED:1; + uint8_t ENHANCED_FRAME_CAP:1; + } bits; + uint8_t raw; +}; + +union max_down_spread { + struct { + uint8_t MAX_DOWN_SPREAD:1; + uint8_t RESERVED:5; + uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; + uint8_t RESERVED1:1; + } bits; + uint8_t raw; +}; + +union mstm_cap { + struct { + uint8_t MST_CAP:1; + uint8_t RESERVED:7; + } bits; + uint8_t raw; +}; + +union mstm_cntl { + struct { + uint8_t MST_EN:1; + uint8_t UP_REQ_EN:1; + uint8_t UPSTREAM_IS_SRC:1; + uint8_t RESERVED:5; + } bits; + uint8_t raw; +}; + +union lane_count_set { + struct { + uint8_t LANE_COUNT_SET:5; + uint8_t POST_LT_ADJ_REQ_GRANTED:1; + uint8_t RESERVED:1; + uint8_t ENHANCED_FRAMING:1; + } bits; + uint8_t raw; +}; + +/* for DPCD_ADDRESS_I2C_SPEED_CNTL_CAP + * and DPCD_ADDRESS_I2C_SPEED_CNTL + */ +union i2c_speed { + struct { + uint8_t _1KBPS:1; + uint8_t _5KBPS:1; + uint8_t _10KBPS:1; + uint8_t _100KBPS:1; + uint8_t _400KBPS:1; + uint8_t _1MBPS:1; + uint8_t reserved:2; + } bits; + uint8_t raw; +}; + +union payload_table_update_status { + struct { + uint8_t VC_PAYLOAD_TABLE_UPDATED:1; + uint8_t ACT_HANDLED:1; + } bits; + uint8_t raw; +}; + +union device_irq_esi_0 { + struct { + uint8_t REMOTE_CONTROL_CMD_PENDING:1; + uint8_t AUTOMATED_TEST_REQUEST:1; + uint8_t CP_IRQ:1; + uint8_t MCCS_IRQ:1; + uint8_t DOWN_REP_MSG_RDY:1; + uint8_t UP_REQ_MSG_RDY:1; + uint8_t SINK_SPECIFIC_IRQ:1; + uint8_t RESERVED:1; + } bits; + uint8_t raw; +}; + +union lane_status { + struct { + uint8_t CR_DONE_0:1; + uint8_t CHANNEL_EQ_DONE_0:1; + uint8_t SYMBOL_LOCKED_0:1; + uint8_t RESERVED0:1; + uint8_t CR_DONE_1:1; + uint8_t CHANNEL_EQ_DONE_1:1; + uint8_t SYMBOL_LOCKED_1:1; + uint8_t RESERVED_1:1; + } bits; + uint8_t raw; +}; + +union device_service_irq { + struct { + uint8_t REMOTE_CONTROL_CMD_PENDING:1; + uint8_t AUTOMATED_TEST:1; + uint8_t CP_IRQ:1; + uint8_t MCCS_IRQ:1; + uint8_t DOWN_REP_MSG_RDY:1; + uint8_t UP_REQ_MSG_RDY:1; + uint8_t SINK_SPECIFIC:1; + uint8_t reserved:1; + } bits; + uint8_t raw; +}; + +union downstream_port { + struct { + uint8_t PRESENT:1; + uint8_t TYPE:2; + uint8_t FORMAT_CONV:1; + uint8_t DETAILED_CAPS:1; + uint8_t RESERVED:3; + } bits; + uint8_t raw; +}; + +union sink_count { + struct { + uint8_t SINK_COUNT:6; + uint8_t CPREADY:1; + uint8_t RESERVED:1; + } bits; + uint8_t raw; +}; + +union lane_align_status_updated { + struct { + uint8_t INTERLANE_ALIGN_DONE:1; + uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; + uint8_t RESERVED:4; + uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; + uint8_t LINK_STATUS_UPDATED:1; + } bits; + uint8_t raw; +}; + +union lane_adjust { + struct { + uint8_t VOLTAGE_SWING_LANE:2; + uint8_t PRE_EMPHASIS_LANE:2; + uint8_t RESERVED:4; + } bits; + uint8_t raw; +}; + +/* Automated test structures */ +union test_request { + struct { + uint8_t LINK_TRAINING:1; + uint8_t LINK_TEST_PATTERN:1; + uint8_t EDID_READ:1; + uint8_t PHY_TEST_PATTERN:1; + uint8_t AUDIO_TEST_PATTERN:1; + uint8_t AUDIO_TEST_NO_VIDEO:1; + uint8_t RESERVED:1; + uint8_t TEST_STEREO_3D:1; + } bits; + uint8_t raw; +}; + +union test_response { + struct { + uint8_t ACK:1; + uint8_t NO_ACK:1; + uint8_t RESERVED:6; + } bits; + uint8_t raw; +}; + +union link_test_pattern { + struct { + uint8_t PATTERN:2;/*DpcdLinkTestPatterns*/ + uint8_t RESERVED:6; + } bits; + uint8_t raw; +}; + +union test_misc { + struct dpcd_test_misc_bits { + uint8_t SYNC_CLOCK:1; + uint8_t CLR_FORMAT:2;/*DpcdTestColorFormat*/ + uint8_t DYN_RANGE:1;/*DpcdTestDynRange*/ + uint8_t YCBCR:1;/*DpcdTestYCbCrStandard*/ + uint8_t BPC:3;/*DpcdTestBitDepth*/ + } bits; + uint8_t raw; +}; + +union phy_test_pattern { + struct { + /* This field is 2 bits for DP1.1 and 3 bits for DP1.2.*/ + uint8_t PATTERN:3; + uint8_t RESERVED:5;/* BY spec, bit7:2 is 0 for DP1.1.*/ + } bits; + uint8_t raw; +}; + +union audio_test_mode { + struct { + uint8_t SAMPLING_RATE:4; + uint8_t CHANNEL_COUNT:4; + } bits; + uint8_t raw; +}; + +union audio_tes_tpattern_period { + struct { + uint8_t PATTERN_PERIOD:4; + uint8_t RESERVED:4; + } bits; + uint8_t raw; +}; + +struct audio_test_pattern_type { + uint8_t value; +}; + +union dpcd_training_pattern { + struct { + uint8_t TRAINING_PATTERN_SET:2; + uint8_t LINK_QUAL_PATTERN_SET:2; + uint8_t RECOVERED_CLOCK_OUT_EN:1; + uint8_t SCRAMBLING_DISABLE:1; + uint8_t RESERVED:2; + } bits; + uint8_t raw; +}; + +/* Training Lane is used to configure downstream DP device's voltage swing +and pre-emphasis levels*/ +/* The DPCD addresses are from 0x103 to 0x106*/ +union dpcd_training_lane { + struct { + uint8_t VOLTAGE_SWING_SET:2; + uint8_t MAX_SWING_REACHED:1; + uint8_t PRE_EMPHASIS_SET:2; + uint8_t MAX_PRE_EMPHASIS_REACHED:1; + uint8_t RESERVED:2; + } bits; + uint8_t raw; +}; + +/*Training Lane Set 2 is used to configure downstream DP device's +post cursor 2 level of Training Pattern 2 or 3*/ +/* The DPCD addresses are 0x10F (TRAINING_LANE0_1_SET2) +and 0x110 (TRAINING_LANE2_3_SET2)*/ +union dpcd_training_lane_set2 { + struct { + uint8_t POST_CURSOR2_SET:2; + uint8_t MAX_POST_CURSOR2_REACHED:1; + uint8_t RESERVED:1; + } bits; + uint8_t raw; +}; + +union dpcd_psr_configuration { + struct { + uint8_t ENABLE:1; + uint8_t TRANSMITTER_ACTIVE_IN_PSR:1; + uint8_t CRC_VERIFICATION:1; + uint8_t FRAME_CAPTURE_INDICATION:1; + uint8_t LINE_CAPTURE_INDICATION:1; + uint8_t IRQ_HPD_WITH_CRC_ERROR:1; + uint8_t RESERVED:2; + } bits; + uint8_t raw; +}; + +union psr_error_status { + struct { + uint8_t LINK_CRC_ERROR:1; + uint8_t RFB_STORAGE_ERROR:1; + uint8_t RESERVED:6; + } bits; + uint8_t raw; +}; + +union psr_event_status_ind { + struct { + uint8_t SINK_PSR_CAP_CHANGE:1; + uint8_t RESERVED:7; + } bits; + uint8_t raw; +}; + +union psr_sink_psr_status { + struct { + uint8_t SINK_SELF_REFRESH_STATUS:3; + uint8_t RESERVED:5; + } bits; + uint8_t raw; +}; + +/* EDP related 0x701 */ +union edp_generial_cap1 { + struct { + uint8_t TCON_BACKLIGHT_ADJUSTMENT_CAPABLE:1; + uint8_t BACKLIGHT_PIN_ENABLE_CAPABLE:1; + uint8_t BACKLIGHT_AUX_ENABLE_CAPABLE:1; + uint8_t PANEL_SELFTEST_PIN_ENABLE_CAPABLE:1; + uint8_t BACKLIGHT_SELFTEST_AUX_ENABLE_CAPABLE:1; + uint8_t FRC_ENABLE_CAPABLE:1; + uint8_t COLOR_ENGINE_CAPABLE:1; + /*bit 7, pane can be controlled by 0x600*/ + uint8_t SET_POWER_CAPABLE:1; + } bits; + uint8_t raw; +}; + +/* TMDS-converter related */ +union dwnstream_port_caps_byte0 { + struct { + uint8_t DWN_STRM_PORTX_TYPE:3; + uint8_t DWN_STRM_PORTX_HPD:1; + uint8_t RESERVERD:4; + } bits; + uint8_t raw; +}; + +/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ +enum dpcd_downstream_port_detailed_type { + DOWN_STREAM_DETAILED_DP = 0, + DOWN_STREAM_DETAILED_VGA, + DOWN_STREAM_DETAILED_DVI, + DOWN_STREAM_DETAILED_HDMI, + DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ + DOWN_STREAM_DETAILED_DP_PLUS_PLUS +}; + +union dwnstream_port_caps_byte2 { + struct { + uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; + uint8_t RESERVED:6; + } bits; + uint8_t raw; +}; + +union dp_downstream_port_present { + uint8_t byte; + struct { + uint8_t PORT_PRESENT:1; + uint8_t PORT_TYPE:2; + uint8_t FMT_CONVERSION:1; + uint8_t DETAILED_CAPS:1; + uint8_t RESERVED:3; + } fields; +}; + + +union dwnstream_port_caps_byte3_dvi { + struct { + uint8_t RESERVED1:1; + uint8_t DUAL_LINK:1; + uint8_t HIGH_COLOR_DEPTH:1; + uint8_t RESERVED2:5; + } bits; + uint8_t raw; +}; + +union dwnstream_port_caps_byte3_hdmi { + struct { + uint8_t FRAME_SEQ_TO_FRAME_PACK:1; + uint8_t RESERVED:7; + } bits; + uint8_t raw; +}; + +/*4-byte structure for detailed capabilities of a down-stream port +(DP-to-TMDS converter).*/ +union dwnstream_portx_caps { + struct { + union dwnstream_port_caps_byte0 byte0; + uint8_t max_tmds_clk;/* byte1 */ + union dwnstream_port_caps_byte2 byte2; + + union { + union dwnstream_port_caps_byte3_dvi byte_dvi; + union dwnstream_port_caps_byte3_hdmi byte_hdmi; + } byte3; + } bytes; + uint8_t raw[4]; +}; + +union sink_status { + struct { + uint8_t RX_PORT0_STATUS:1; + uint8_t RX_PORT1_STATUS:1; + uint8_t RESERVED:6; + } bits; + uint8_t raw; +}; + +/*6-byte structure corresponding to 6 registers (200h-205h) +read during handling of HPD-IRQ*/ +union hpd_irq_data { + struct { + union sink_count sink_cnt;/* 200h */ + union device_service_irq device_service_irq;/* 201h */ + union lane_status lane01_status;/* 202h */ + union lane_status lane23_status;/* 203h */ + union lane_align_status_updated lane_status_updated;/* 204h */ + union sink_status sink_status; + } bytes; + uint8_t raw[6]; +}; + +union down_stream_port_count { + struct { + uint8_t DOWN_STR_PORT_COUNT:4; + uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ + /*Bit 6 = MSA_TIMING_PAR_IGNORED + 0 = Sink device requires the MSA timing parameters + 1 = Sink device is capable of rendering incoming video + stream without MSA timing parameters*/ + uint8_t IGNORE_MSA_TIMING_PARAM:1; + /*Bit 7 = OUI Support + 0 = OUI not supported + 1 = OUI supported + (OUI and Device Identification mandatory for DP 1.2)*/ + uint8_t OUI_SUPPORT:1; + } bits; + uint8_t raw; +}; + +union down_spread_ctrl { + struct { + uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ + /* Bits 4 = SPREAD_AMP. Spreading amplitude + 0 = Main link signal is not downspread + 1 = Main link signal is downspread <= 0.5% + with frequency in the range of 30kHz ~ 33kHz*/ + uint8_t SPREAD_AMP:1; + uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ + /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN + 0 = Source device will send valid data for the MSA Timing Params + 1 = Source device may send invalid data for these MSA Timing Params*/ + uint8_t IGNORE_MSA_TIMING_PARAM:1; + } bits; + uint8_t raw; +}; + +union dpcd_edp_config { + struct { + uint8_t PANEL_MODE_EDP:1; + uint8_t FRAMING_CHANGE_ENABLE:1; + uint8_t RESERVED:5; + uint8_t PANEL_SELF_TEST_ENABLE:1; + } bits; + uint8_t raw; +}; + +struct dp_device_vendor_id { + uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ + uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ +}; + +struct dp_sink_hw_fw_revision { + uint8_t ieee_hw_rev; + uint8_t ieee_fw_rev[2]; +}; + +/*DPCD register of DP receiver capability field bits-*/ +union edp_configuration_cap { + struct { + uint8_t ALT_SCRAMBLER_RESET:1; + uint8_t FRAMING_CHANGE:1; + uint8_t RESERVED:1; + uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; + uint8_t RESERVED2:4; + } bits; + uint8_t raw; +}; + +union psr_capabilities { + struct { + uint8_t EXIT_LT_NOT_REQ:1; + uint8_t RFB_SETUP_TIME:3; + uint8_t RESERVED:4; + } bits; + uint8_t raw; +}; + +#endif /* __DAL_DPCD_DEFS_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/encoder_interface.h b/drivers/gpu/drm/amd/dal/include/encoder_interface.h new file mode 100644 index 000000000000..5fbf816cf96e --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/encoder_interface.h @@ -0,0 +1,278 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of enc software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and enc permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_ENCODER_INTERFACE_H__ +#define __DAL_ENCODER_INTERFACE_H__ + +#include "encoder_types.h" +#include "adapter_service_interface.h" +#include "fixed31_32.h" + +enum encoder_result { + ENCODER_RESULT_OK, + ENCODER_RESULT_ERROR, + ENCODER_RESULT_NOBANDWIDTH, + ENCODER_RESULT_SINKCONNECTIVITYCHANGED, +}; + +struct encoder_init_data { + struct adapter_service *adapter_service; + enum channel_id channel; + struct graphics_object_id connector; + enum hpd_source_id hpd_source; + /* TODO: in DAL2, here was pointer to EventManagerInterface */ + struct graphics_object_id encoder; + struct dc_context *ctx; +}; + +/* forward declaration */ +struct encoder; + +struct encoder *dal_encoder_create( + const struct encoder_init_data *init_data); + +/* access graphics object base */ +const struct graphics_object_id dal_encoder_get_graphics_object_id( + const struct encoder *enc); + +/* + * Signal types support + */ +uint32_t dal_encoder_enumerate_input_signals( + const struct encoder *enc); +uint32_t dal_encoder_enumerate_output_signals( + const struct encoder *enc); +bool dal_encoder_is_input_signal_supported( + const struct encoder *enc, + enum signal_type signal); +bool dal_encoder_is_output_signal_supported( + const struct encoder *enc, + enum signal_type signal); +void dal_encoder_set_input_signals( + struct encoder *enc, + uint32_t signals); +void dal_encoder_set_output_signals( + struct encoder *enc, + uint32_t signals); + +/* + * Programming interface + */ +/* perform power-up sequence (boot up, resume, recovery) */ +enum encoder_result dal_encoder_power_up( + struct encoder *enc, + const struct encoder_context *ctx); +/* perform power-down (shut down, stand-by */ +enum encoder_result dal_encoder_power_down( + struct encoder *enc, + const struct encoder_output *output); +/* setup encoder block (DIG, DVO, DAC), does not enables encoder */ +enum encoder_result dal_encoder_setup( + struct encoder *enc, + const struct encoder_output *output); +/* activate transmitter, + * do preparation before enables the actual stream output */ +enum encoder_result dal_encoder_pre_enable_output( + struct encoder *enc, + const struct encoder_pre_enable_output_param *param); +/* activate transmitter, enables actual stream output */ +enum encoder_result dal_encoder_enable_output( + struct encoder *enc, + const struct encoder_output *output); +/* deactivate transmitter, disables stream output */ +enum encoder_result dal_encoder_disable_output( + struct encoder *enc, + const struct encoder_output *output); +/* output blank data, + *prevents output of the actual surface data on active transmitter */ +enum encoder_result dal_encoder_blank( + struct encoder *enc, + const struct encoder_context *ctx); +/* stop sending blank data, + * output the actual surface data on active transmitter */ +enum encoder_result dal_encoder_unblank( + struct encoder *enc, + const struct encoder_unblank_param *param); +/* setup stereo signal from given controller */ +enum encoder_result dal_encoder_setup_stereo( + struct encoder *enc, + const struct encoder_3d_setup *setup); +/* enable HSync/VSync output from given controller */ +enum encoder_result dal_encoder_enable_sync_output( + struct encoder *enc, + enum sync_source src); +/* disable HSync/VSync output */ +enum encoder_result dal_encoder_disable_sync_output( + struct encoder *enc); +/* action of encoder before DDC transaction */ +enum encoder_result dal_encoder_pre_ddc( + struct encoder *enc, + const struct encoder_context *ctx); +/* action of encoder after DDC transaction */ +enum encoder_result dal_encoder_post_ddc( + struct encoder *enc, + const struct encoder_context *ctx); +/* CRT DDC EDID polling interrupt interface */ +enum encoder_result dal_encoder_update_implementation( + struct encoder *enc, + const struct encoder_context *ctx); +/* set test pattern signal */ +enum encoder_result dal_encoder_set_dp_phy_pattern( + struct encoder *enc, + const struct encoder_set_dp_phy_pattern_param *param); + +void dal_encoder_release_hw(struct encoder *enc); +/* + * Information interface + */ +/* check whether sink is present based on SENSE detection, + * analog encoders will return true */ +bool dal_encoder_is_sink_present( + struct encoder *enc, + struct graphics_object_id downstream); +/* detect load on the sink, + * for analog signal, + * load detection will be called for the specified signal */ +enum signal_type dal_encoder_detect_load( + struct encoder *enc, + const struct encoder_context *ctx); +/* detect output sink type, + * for digital perform sense detection, + * for analog return encoder's signal type */ +enum signal_type dal_encoder_detect_sink( + struct encoder *enc, + struct graphics_object_id downstream); +/* get transmitter id */ +enum transmitter dal_encoder_get_transmitter( + const struct encoder *enc); +/* */ +enum transmitter dal_encoder_get_paired_transmitter( + const struct encoder *enc); +/* */ +enum physical_phy_id dal_encoder_get_phy( + const struct encoder *enc); +/* */ +enum physical_phy_id dal_encoder_get_paired_phy( + const struct encoder *enc); +/* reports if the encoder supports given link settings */ +bool dal_encoder_is_link_settings_supported( + struct encoder *enc, + const struct link_settings *link_settings); +/* options and features supported by encoder */ +struct encoder_feature_support dal_encoder_get_supported_features( + const struct encoder *enc); +/* reports list of supported stream engines */ +union supported_stream_engines dal_encoder_get_supported_stream_engines( + const struct encoder *enc); +/* reports preferred stream engine */ +enum engine_id dal_encoder_get_preferred_stream_engine( + const struct encoder *enc); +/* reports whether clock source can be used with enc encoder */ +bool dal_encoder_is_clock_source_supported( + const struct encoder *enc, + enum clock_source_id clock_source); +/* check encoder capabilities to confirm + * specified timing is in the encoder limits + * when outputting certain signal */ +enum encoder_result dal_encoder_validate_output( + struct encoder *enc, + const struct encoder_output *output); +/* retrieves sync source which outputs VSync signal from encoder */ +enum sync_source dal_encoder_get_vsync_output_source( + const struct encoder *enc); +/* + * Adjustments + */ +/* update AVI info frame */ +void dal_encoder_update_info_frame( + struct encoder *enc, + const struct encoder_info_frame_param *param); +/* */ +void dal_encoder_stop_info_frame( + struct encoder *enc, + const struct encoder_context *ctx); +/* */ +enum encoder_result dal_encoder_set_lcd_backlight_level( + struct encoder *enc, + uint32_t level); +/* backlight control interface */ +enum encoder_result dal_encoder_backlight_control( + struct encoder *enc, + bool enable); +/* + * DP MST programming + */ +/* update payload slot allocation for each DP MST stream */ +enum encoder_result dal_encoder_update_mst_alloc_table( + struct encoder *enc, + const struct dp_mst_stream_allocation_table *table, + bool is_removal); +/* enable virtual channel stream with throttled value X.Y */ +enum encoder_result dal_encoder_enable_stream( + struct encoder *enc, + enum engine_id engine, + struct fixed31_32 throttled_vcp_size); +/* disable virtual channel stream */ +enum encoder_result dal_encoder_disable_stream( + struct encoder *enc, + enum engine_id engine); +void dal_encoder_set_multi_path(struct encoder *enc, bool is_multi_path); +/* + * Test harness + */ +/* check whether Test Pattern enabled */ +bool dal_encoder_is_test_pattern_enabled( + struct encoder *enc, + enum engine_id engine); +/* set lane parameters */ +enum encoder_result dal_encoder_set_lane_settings( + struct encoder *enc, + const struct encoder_context *ctx, + const struct link_training_settings *link_settings); +/* get lane parameters */ +enum encoder_result dal_encoder_get_lane_settings( + struct encoder *enc, + const struct encoder_context *ctx, + struct link_training_settings *link_settings); +/* enable master clock of HPD interrupt */ +void dal_encoder_enable_hpd( + struct encoder *enc, + const struct encoder_context *ctx); +/* disable all HPD interrupts */ +void dal_encoder_disable_hpd( + struct encoder *enc, + const struct encoder_context *ctx); + +/* get current HW state - used for optimization code path only */ +enum clock_source_id dal_encoder_get_active_clock_source( + const struct encoder *enc); +enum engine_id dal_encoder_get_active_engine( + const struct encoder *enc); + +/* destroy encoder instance */ +void dal_encoder_destroy( + struct encoder **ptr); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h new file mode 100644 index 000000000000..507f9f639099 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h @@ -0,0 +1,389 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_FIXED31_32_H__ +#define __DAL_FIXED31_32_H__ + +/* + * @brief + * Arithmetic operations on real numbers + * represented as fixed-point numbers. + * There are: 1 bit for sign, + * 31 bit for integer part, + * 32 bits for fractional part. + * + * @note + * Currently, overflows and underflows are asserted; + * no special result returned. + */ + +struct fixed31_32 { + int64_t value; +}; + +/* + * @brief + * Useful constants + */ + +static const struct fixed31_32 dal_fixed31_32_zero = { 0 }; +static const struct fixed31_32 dal_fixed31_32_epsilon = { 1LL }; +static const struct fixed31_32 dal_fixed31_32_half = { 0x80000000LL }; +static const struct fixed31_32 dal_fixed31_32_one = { 0x100000000LL }; + +static const struct fixed31_32 dal_fixed31_32_pi = { 13493037705LL }; +static const struct fixed31_32 dal_fixed31_32_two_pi = { 26986075409LL }; +static const struct fixed31_32 dal_fixed31_32_e = { 11674931555LL }; +static const struct fixed31_32 dal_fixed31_32_ln2 = { 2977044471LL }; +static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL }; + +/* + * @brief + * Initialization routines + */ + +/* + * @brief + * result = numerator / denominator + */ +struct fixed31_32 dal_fixed31_32_from_fraction( + int64_t numerator, + int64_t denominator); + +/* + * @brief + * result = arg + */ +struct fixed31_32 dal_fixed31_32_from_int( + int64_t arg); + +/* + * @brief + * Unary operators + */ + +/* + * @brief + * result = -arg + */ +struct fixed31_32 dal_fixed31_32_neg( + struct fixed31_32 arg); + +/* + * @brief + * result = abs(arg) := (arg >= 0) ? arg : -arg + */ +struct fixed31_32 dal_fixed31_32_abs( + struct fixed31_32 arg); + +/* + * @brief + * Binary relational operators + */ + +/* + * @brief + * result = arg1 < arg2 + */ +bool dal_fixed31_32_lt( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = arg1 <= arg2 + */ +bool dal_fixed31_32_le( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = arg1 == arg2 + */ +bool dal_fixed31_32_eq( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2 + */ +struct fixed31_32 dal_fixed31_32_min( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1 + */ +struct fixed31_32 dal_fixed31_32_max( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * | min_value, when arg <= min_value + * result = | arg, when min_value < arg < max_value + * | max_value, when arg >= max_value + */ +struct fixed31_32 dal_fixed31_32_clamp( + struct fixed31_32 arg, + struct fixed31_32 min_value, + struct fixed31_32 max_value); + +/* + * @brief + * Binary shift operators + */ + +/* + * @brief + * result = arg << shift + */ +struct fixed31_32 dal_fixed31_32_shl( + struct fixed31_32 arg, + uint8_t shift); + +/* + * @brief + * result = arg >> shift + */ +struct fixed31_32 dal_fixed31_32_shr( + struct fixed31_32 arg, + uint8_t shift); + +/* + * @brief + * Binary additive operators + */ + +/* + * @brief + * result = arg1 + arg2 + */ +struct fixed31_32 dal_fixed31_32_add( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = arg1 - arg2 + */ +struct fixed31_32 dal_fixed31_32_sub_int( + struct fixed31_32 arg1, + int32_t arg2); + +/* + * @brief + * result = arg1 - arg2 + */ +struct fixed31_32 dal_fixed31_32_sub( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * Binary multiplicative operators + */ + +/* + * @brief + * result = arg1 * arg2 + */ +struct fixed31_32 dal_fixed31_32_mul_int( + struct fixed31_32 arg1, + int32_t arg2); + +/* + * @brief + * result = arg1 * arg2 + */ +struct fixed31_32 dal_fixed31_32_mul( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * result = square(arg) := arg * arg + */ +struct fixed31_32 dal_fixed31_32_sqr( + struct fixed31_32 arg); + +/* + * @brief + * result = arg1 / arg2 + */ +struct fixed31_32 dal_fixed31_32_div_int( + struct fixed31_32 arg1, + int64_t arg2); + +/* + * @brief + * result = arg1 / arg2 + */ +struct fixed31_32 dal_fixed31_32_div( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * Reciprocal function + */ + +/* + * @brief + * result = reciprocal(arg) := 1 / arg + * + * @note + * No special actions taken in case argument is zero. + */ +struct fixed31_32 dal_fixed31_32_recip( + struct fixed31_32 arg); + +/* + * @brief + * Trigonometric functions + */ + +/* + * @brief + * result = sinc(arg) := sin(arg) / arg + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct fixed31_32 dal_fixed31_32_sinc( + struct fixed31_32 arg); + +/* + * @brief + * result = sin(arg) + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct fixed31_32 dal_fixed31_32_sin( + struct fixed31_32 arg); + +/* + * @brief + * result = cos(arg) + * + * @note + * Argument specified in radians + * and should be in [-2pi...2pi] range - + * passing arguments outside that range + * will cause incorrect result! + */ +struct fixed31_32 dal_fixed31_32_cos( + struct fixed31_32 arg); + +/* + * @brief + * Transcendent functions + */ + +/* + * @brief + * result = exp(arg) + * + * @note + * Currently, function is verified for abs(arg) <= 1. + */ +struct fixed31_32 dal_fixed31_32_exp( + struct fixed31_32 arg); + +/* + * @brief + * result = log(arg) + * + * @note + * Currently, abs(arg) should be less than 1. + * No normalization is done. + * Currently, no special actions taken + * in case of invalid argument(s). Take care! + */ +struct fixed31_32 dal_fixed31_32_log( + struct fixed31_32 arg); + +/* + * @brief + * Power function + */ + +/* + * @brief + * result = pow(arg1, arg2) + * + * @note + * Currently, abs(arg1) should be less than 1. Take care! + */ +struct fixed31_32 dal_fixed31_32_pow( + struct fixed31_32 arg1, + struct fixed31_32 arg2); + +/* + * @brief + * Rounding functions + */ + +/* + * @brief + * result = floor(arg) := greatest integer lower than or equal to arg + */ +int32_t dal_fixed31_32_floor( + struct fixed31_32 arg); + +/* + * @brief + * result = round(arg) := integer nearest to arg + */ +int32_t dal_fixed31_32_round( + struct fixed31_32 arg); + +/* + * @brief + * result = ceil(arg) := lowest integer greater than or equal to arg + */ +int32_t dal_fixed31_32_ceil( + struct fixed31_32 arg); + +/* the following two function are used in scaler hw programming to convert fixed + * point value to format 2 bits from integer part and 19 bits from fractional + * part. The same applies for u0d19, 0 bits from integer part and 19 bits from + * fractional + */ + +uint32_t dal_fixed31_32_u2d19( + struct fixed31_32 arg); + +uint32_t dal_fixed31_32_u0d19( + struct fixed31_32 arg); + + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h new file mode 100644 index 000000000000..f393e953e91a --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h @@ -0,0 +1,82 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_FIXED32_32_H__ +#define __DAL_FIXED32_32_H__ + +#include "dm_services_types.h" + +struct fixed32_32 { + uint64_t value; +}; + +static const struct fixed32_32 dal_fixed32_32_zero = { 0 }; +static const struct fixed32_32 dal_fixed32_32_one = { 0x100000000LL }; +static const struct fixed32_32 dal_fixed32_32_half = { 0x80000000LL }; + +struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d); +struct fixed32_32 dal_fixed32_32_from_int(uint32_t value); +struct fixed32_32 dal_fixed32_32_add( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +struct fixed32_32 dal_fixed32_32_add_int( + struct fixed32_32 lhs, + uint32_t rhs); +struct fixed32_32 dal_fixed32_32_sub( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +struct fixed32_32 dal_fixed32_32_sub_int( + struct fixed32_32 lhs, + uint32_t rhs); +struct fixed32_32 dal_fixed32_32_mul( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +struct fixed32_32 dal_fixed32_32_mul_int( + struct fixed32_32 lhs, + uint32_t rhs); +struct fixed32_32 dal_fixed32_32_div( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +struct fixed32_32 dal_fixed32_32_div_int( + struct fixed32_32 lhs, + uint32_t rhs); +struct fixed32_32 dal_fixed32_32_min( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +struct fixed32_32 dal_fixed32_32_max( + struct fixed32_32 lhs, + struct fixed32_32 rhs); +bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs); +bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs); +bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs); +bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs); +bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs); +bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs); +bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs); +uint32_t dal_fixed32_32_ceil(struct fixed32_32 value); +uint32_t dal_fixed32_32_floor(struct fixed32_32 value); +uint32_t dal_fixed32_32_round(struct fixed32_32 value); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/gpio_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_interface.h new file mode 100644 index 000000000000..a084d7923e2f --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/gpio_interface.h @@ -0,0 +1,93 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GPIO_INTERFACE_H__ +#define __DAL_GPIO_INTERFACE_H__ + +#include "gpio_types.h" +#include "grph_object_defs.h" + +struct gpio; + +/* Open the handle for future use */ +enum gpio_result dal_gpio_open( + struct gpio *gpio, + enum gpio_mode mode); + +enum gpio_result dal_gpio_open_ex( + struct gpio *gpio, + enum gpio_mode mode, + void *options); + +/* Get high or low from the pin */ +enum gpio_result dal_gpio_get_value( + const struct gpio *gpio, + uint32_t *value); + +/* Set pin high or low */ +enum gpio_result dal_gpio_set_value( + const struct gpio *gpio, + uint32_t value); + +/* Get current mode */ +enum gpio_mode dal_gpio_get_mode( + const struct gpio *gpio); + +/* Change mode of the handle */ +enum gpio_result dal_gpio_change_mode( + struct gpio *gpio, + enum gpio_mode mode); + +/* Get the GPIO id */ +enum gpio_id dal_gpio_get_id( + const struct gpio *gpio); + +/* Get the GPIO enum */ +uint32_t dal_gpio_get_enum( + const struct gpio *gpio); + +/* Set the GPIO pin configuration */ +enum gpio_result dal_gpio_set_config( + struct gpio *gpio, + const struct gpio_config_data *config_data); + +/* Obtain GPIO pin info */ +enum gpio_result dal_gpio_get_pin_info( + const struct gpio *gpio, + struct gpio_pin_info *pin_info); + +/* Obtain GPIO sync source */ +enum sync_source dal_gpio_get_sync_source( + const struct gpio *gpio); + +/* Obtain GPIO pin output state (active low or active high) */ +enum gpio_pin_output_state dal_gpio_get_output_state( + const struct gpio *gpio); + +/* Close the handle */ +void dal_gpio_close( + struct gpio *gpio); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h new file mode 100644 index 000000000000..3f1b923c1885 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/gpio_service_interface.h @@ -0,0 +1,81 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GPIO_SERVICE_INTERFACE_H__ +#define __DAL_GPIO_SERVICE_INTERFACE_H__ + +#include "gpio_types.h" +#include "gpio_interface.h" +#include "ddc_interface.h" +#include "irq_interface.h" + +struct gpio_service; + +struct gpio_service *dal_gpio_service_create( + enum dce_version dce_version_major, + enum dce_version dce_version_minor, + struct dc_context *ctx); + +struct gpio *dal_gpio_service_create_gpio( + struct gpio_service *service, + uint32_t offset, + uint32_t mask, + enum gpio_pin_output_state output_state); + +struct gpio *dal_gpio_service_create_gpio_ex( + struct gpio_service *service, + enum gpio_id id, + uint32_t en, + enum gpio_pin_output_state output_state); + +void dal_gpio_service_destroy_gpio( + struct gpio **gpio); + +struct ddc *dal_gpio_service_create_ddc( + struct gpio_service *service, + uint32_t offset, + uint32_t mask, + struct gpio_ddc_hw_info *info); + +void dal_gpio_service_destroy_ddc( + struct ddc **ddc); + +struct irq *dal_gpio_service_create_irq( + struct gpio_service *service, + uint32_t offset, + uint32_t mask); + +struct irq *dal_gpio_service_create_irq_ex( + struct gpio_service *service, + enum gpio_id id, + uint32_t en); + +void dal_gpio_service_destroy_irq( + struct irq **ptr); + +void dal_gpio_service_destroy( + struct gpio_service **ptr); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/gpio_types.h b/drivers/gpu/drm/amd/dal/include/gpio_types.h new file mode 100644 index 000000000000..6d3214b36cf4 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/gpio_types.h @@ -0,0 +1,341 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GPIO_TYPES_H__ +#define __DAL_GPIO_TYPES_H__ + +#define BUNDLE_A_MASK 0x00FFF000L +#define BUNDLE_B_MASK 0x00000FFFL + +/* + * gpio_result + * + * @brief + * The possible return codes that the GPIO object can return. + * These return codes can be generated + * directly by the GPIO object or from the GPIOPin object. + */ +enum gpio_result { + GPIO_RESULT_OK, + GPIO_RESULT_NULL_HANDLE, + GPIO_RESULT_INVALID_DATA, + GPIO_RESULT_DEVICE_BUSY, + GPIO_RESULT_OPEN_FAILED, + GPIO_RESULT_ALREADY_OPENED, + GPIO_RESULT_NON_SPECIFIC_ERROR +}; + +/* + * @brief + * Used to identify the specific GPIO device + * + * @notes + * These constants are used as indices in a vector. + * Thus they should start from zero and be contiguous. + */ +enum gpio_id { + GPIO_ID_UNKNOWN = (-1), + GPIO_ID_DDC_DATA, + GPIO_ID_DDC_CLOCK, + GPIO_ID_GENERIC, + GPIO_ID_HPD, + GPIO_ID_GPIO_PAD, + GPIO_ID_VIP_PAD, + GPIO_ID_SYNC, + GPIO_ID_GSL, /* global swap lock */ + GPIO_ID_COUNT, + GPIO_ID_MIN = GPIO_ID_DDC_DATA, + GPIO_ID_MAX = GPIO_ID_GSL +}; + +#define GPIO_ENUM_UNKNOWN \ + 32 + +struct gpio_pin_info { + uint32_t offset; + uint32_t offset_y; + uint32_t offset_en; + uint32_t offset_mask; + + uint32_t mask; + uint32_t mask_y; + uint32_t mask_en; + uint32_t mask_mask; +}; + +enum gpio_pin_output_state { + GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW, + GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH, + GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW +}; + +enum gpio_generic { + GPIO_GENERIC_UNKNOWN = (-1), + GPIO_GENERIC_A, + GPIO_GENERIC_B, + GPIO_GENERIC_C, + GPIO_GENERIC_D, + GPIO_GENERIC_E, + GPIO_GENERIC_F, + GPIO_GENERIC_G, + GPIO_GENERIC_COUNT, + GPIO_GENERIC_MIN = GPIO_GENERIC_A, + GPIO_GENERIC_MAX = GPIO_GENERIC_B +}; + +enum gpio_hpd { + GPIO_HPD_UNKNOWN = (-1), + GPIO_HPD_1, + GPIO_HPD_2, + GPIO_HPD_3, + GPIO_HPD_4, + GPIO_HPD_5, + GPIO_HPD_6, + GPIO_HPD_COUNT, + GPIO_HPD_MIN = GPIO_HPD_1, + GPIO_HPD_MAX = GPIO_HPD_6 +}; + +enum gpio_gpio_pad { + GPIO_GPIO_PAD_UNKNOWN = (-1), + GPIO_GPIO_PAD_0, + GPIO_GPIO_PAD_1, + GPIO_GPIO_PAD_2, + GPIO_GPIO_PAD_3, + GPIO_GPIO_PAD_4, + GPIO_GPIO_PAD_5, + GPIO_GPIO_PAD_6, + GPIO_GPIO_PAD_7, + GPIO_GPIO_PAD_8, + GPIO_GPIO_PAD_9, + GPIO_GPIO_PAD_10, + GPIO_GPIO_PAD_11, + GPIO_GPIO_PAD_12, + GPIO_GPIO_PAD_13, + GPIO_GPIO_PAD_14, + GPIO_GPIO_PAD_15, + GPIO_GPIO_PAD_16, + GPIO_GPIO_PAD_17, + GPIO_GPIO_PAD_18, + GPIO_GPIO_PAD_19, + GPIO_GPIO_PAD_20, + GPIO_GPIO_PAD_21, + GPIO_GPIO_PAD_22, + GPIO_GPIO_PAD_23, + GPIO_GPIO_PAD_24, + GPIO_GPIO_PAD_25, + GPIO_GPIO_PAD_26, + GPIO_GPIO_PAD_27, + GPIO_GPIO_PAD_28, + GPIO_GPIO_PAD_29, + GPIO_GPIO_PAD_30, + GPIO_GPIO_PAD_COUNT, + GPIO_GPIO_PAD_MIN = GPIO_GPIO_PAD_0, + GPIO_GPIO_PAD_MAX = GPIO_GPIO_PAD_30 +}; + +enum gpio_vip_pad { + GPIO_VIP_PAD_UNKNOWN = (-1), + /* following never used - + * GPIO_ID_DDC_CLOCK::GPIO_DDC_LINE_VIP_PAD defined instead */ + GPIO_VIP_PAD_SCL, + /* following never used - + * GPIO_ID_DDC_DATA::GPIO_DDC_LINE_VIP_PAD defined instead */ + GPIO_VIP_PAD_SDA, + GPIO_VIP_PAD_VHAD, + GPIO_VIP_PAD_VPHCTL, + GPIO_VIP_PAD_VIPCLK, + GPIO_VIP_PAD_VID, + GPIO_VIP_PAD_VPCLK0, + GPIO_VIP_PAD_DVALID, + GPIO_VIP_PAD_PSYNC, + GPIO_VIP_PAD_COUNT, + GPIO_VIP_PAD_MIN = GPIO_VIP_PAD_SCL, + GPIO_VIP_PAD_MAX = GPIO_VIP_PAD_PSYNC +}; + +enum gpio_sync { + GPIO_SYNC_UNKNOWN = (-1), + GPIO_SYNC_HSYNC_A, + GPIO_SYNC_VSYNC_A, + GPIO_SYNC_HSYNC_B, + GPIO_SYNC_VSYNC_B, + GPIO_SYNC_COUNT, + GPIO_SYNC_MIN = GPIO_SYNC_HSYNC_A, + GPIO_SYNC_MAX = GPIO_SYNC_VSYNC_B +}; + +enum gpio_gsl { + GPIO_GSL_UNKNOWN = (-1), + GPIO_GSL_GENLOCK_CLOCK, + GPIO_GSL_GENLOCK_VSYNC, + GPIO_GSL_SWAPLOCK_A, + GPIO_GSL_SWAPLOCK_B, + GPIO_GSL_COUNT, + GPIO_GSL_MIN = GPIO_GSL_GENLOCK_CLOCK, + GPIO_GSL_MAX = GPIO_GSL_SWAPLOCK_B +}; + +/* + * @brief + * Unique Id for DDC handle. + * Values are meaningful (used as indexes to array) + */ +enum gpio_ddc_line { + GPIO_DDC_LINE_UNKNOWN = (-1), + GPIO_DDC_LINE_DDC1, + GPIO_DDC_LINE_DDC2, + GPIO_DDC_LINE_DDC3, + GPIO_DDC_LINE_DDC4, + GPIO_DDC_LINE_DDC5, + GPIO_DDC_LINE_DDC6, + GPIO_DDC_LINE_DDC_VGA, + GPIO_DDC_LINE_VIP_PAD, + GPIO_DDC_LINE_I2C_PAD = GPIO_DDC_LINE_VIP_PAD, + GPIO_DDC_LINE_COUNT, + GPIO_DDC_LINE_MIN = GPIO_DDC_LINE_DDC1, + GPIO_DDC_LINE_MAX = GPIO_DDC_LINE_I2C_PAD +}; + +/* + * @brief + * Identifies the mode of operation to open a GPIO device. + * A GPIO device (pin) can be programmed in only one of these modes at a time. + */ +enum gpio_mode { + GPIO_MODE_UNKNOWN = (-1), + GPIO_MODE_INPUT, + GPIO_MODE_OUTPUT, + GPIO_MODE_FAST_OUTPUT, + GPIO_MODE_HARDWARE, + GPIO_MODE_INTERRUPT +}; + +/* + * @brief + * Identifies the source of the signal when GPIO is in HW mode. + * get_signal_source() will return GPIO_SYGNAL_SOURCE__UNKNOWN + * when one of the following holds: + * 1. GPIO is input GPIO + * 2. GPIO is not opened in HW mode + * 3. GPIO does not have fixed signal source + * (like DC_GenericA have mux instead fixed) + */ +enum gpio_signal_source { + GPIO_SIGNAL_SOURCE_UNKNOWN = (-1), + GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC, + GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC, + GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC, + GPIO_SIGNAL_SOURCE_DACA_HSYNC, + GPIO_SIGNAL_SOURCE_DACB_HSYNC, + GPIO_SIGNAL_SOURCE_DACA_VSYNC, + GPIO_SIGNAL_SOURCE_DACB_VSYNC, +}; + +enum gpio_stereo_source { + GPIO_STEREO_SOURCE_UNKNOWN = (-1), + GPIO_STEREO_SOURCE_D1, + GPIO_STEREO_SOURCE_D2, + GPIO_STEREO_SOURCE_D3, + GPIO_STEREO_SOURCE_D4, + GPIO_STEREO_SOURCE_D5, + GPIO_STEREO_SOURCE_D6 +}; + +/* + * GPIO config + */ + +enum gpio_config_type { + GPIO_CONFIG_TYPE_NONE, + GPIO_CONFIG_TYPE_DDC, + GPIO_CONFIG_TYPE_HPD, + GPIO_CONFIG_TYPE_GENERIC_MUX, + GPIO_CONFIG_TYPE_GSL_MUX, + GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE +}; + +/* DDC configuration */ + +enum gpio_ddc_config_type { + GPIO_DDC_CONFIG_TYPE_MODE_AUX, + GPIO_DDC_CONFIG_TYPE_MODE_I2C, + GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT, + GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT, + GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING +}; + +struct gpio_ddc_config { + enum gpio_ddc_config_type type; + bool data_en_bit_present; + bool clock_en_bit_present; +}; + +/* HPD configuration */ + +struct gpio_hpd_config { + uint32_t delay_on_connect; /* milliseconds */ + uint32_t delay_on_disconnect; /* milliseconds */ +}; + +struct gpio_generic_mux_config { + bool enable_output_from_mux; + enum gpio_signal_source mux_select; + enum gpio_stereo_source stereo_select; +}; + +enum gpio_gsl_mux_config_type { + GPIO_GSL_MUX_CONFIG_TYPE_DISABLE, + GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC, + GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC +}; + +struct gpio_gsl_mux_config { + enum gpio_gsl_mux_config_type type; + /* Actually sync_source type, + * however we want to avoid inter-component includes here */ + uint32_t gsl_group; +}; + +struct gpio_config_data { + enum gpio_config_type type; + union { + struct gpio_ddc_config ddc; + struct gpio_hpd_config hpd; + struct gpio_generic_mux_config generic_mux; + struct gpio_gsl_mux_config gsl_mux; + } config; +}; + +struct gpio_ddc_hw_info { + bool hw_supported; + uint32_t ddc_channel; +}; + +struct gpio_ddc_open_options { + bool en_bit_present; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/grph_csc_types.h b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h new file mode 100644 index 000000000000..711b458ff564 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/grph_csc_types.h @@ -0,0 +1,98 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GRPH_CSC_TYPES_H__ +#define __DAL_GRPH_CSC_TYPES_H__ + +#include "set_mode_types.h" + +enum color_space { + COLOR_SPACE_UNKNOWN, + COLOR_SPACE_SRGB_FULL_RANGE, + COLOR_SPACE_SRGB_LIMITED_RANGE, + COLOR_SPACE_YPBPR601, + COLOR_SPACE_YPBPR709, + COLOR_SPACE_YCBCR601, + COLOR_SPACE_YCBCR709, + COLOR_SPACE_YCBCR601_YONLY, + COLOR_SPACE_YCBCR709_YONLY, + COLOR_SPACE_N_MVPU_SUPER_AA, +}; + +enum grph_color_adjust_option { + GRPH_COLOR_MATRIX_HW_DEFAULT = 1, + GRPH_COLOR_MATRIX_SW +}; + +enum grph_csc_adjust_item { + GRPH_ADJUSTMENT_CONTRAST = 1, + GRPH_ADJUSTMENT_SATURATION, + GRPH_ADJUSTMENT_BRIGHTNESS, + GRPH_ADJUSTMENT_HUE, + GRPH_ADJUSTMENT_COLOR_TEMPERATURE +}; + +#define CSC_TEMPERATURE_MATRIX_SIZE 9 + +enum graphics_csc_adjust_type { + GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ +}; + +enum graphics_gamut_adjust_type { + GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */ +}; + +struct grph_csc_adjustment { + enum grph_color_adjust_option color_adjust_option; + enum color_space c_space; + int32_t grph_cont; + int32_t grph_sat; + int32_t grph_bright; + int32_t grph_hue; + int32_t adjust_divider; + int32_t temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; + int32_t temperature_divider; + uint32_t lb_color_depth; + uint8_t gamma; /* gamma from Edid */ + enum dc_color_depth color_depth; /* clean up to uint32_t */ + enum pixel_format surface_pixel_format; + enum graphics_csc_adjust_type csc_adjust_type; + enum graphics_gamut_adjust_type gamut_adjust_type; +}; + +struct default_adjustment { + uint32_t lb_color_depth; + enum color_space color_space; + enum dc_color_depth color_depth; + enum pixel_format surface_pixel_format; + enum graphics_csc_adjust_type csc_adjust_type; + bool force_hw_default; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h new file mode 100644 index 000000000000..2ed01bd43c37 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h @@ -0,0 +1,593 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__ +#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__ + +#include "grph_object_defs.h" + +/* + * ##################################################### + * ##################################################### + * + * These defines shared between asic_control/bios_parser and other + * DAL components + * + * ##################################################### + * ##################################################### + */ + +enum tv_standard { + TV_STANDARD_UNKNOWN = 0, /* direct HW (mmBIOS_SCRATCH_2) translation! */ + TV_STANDARD_NTSC, + TV_STANDARD_NTSCJ, + TV_STANDARD_PAL, + TV_STANDARD_PALM, + TV_STANDARD_PALCN, + TV_STANDARD_PALN, + TV_STANDARD_PAL60, + TV_STANDARD_SECAM +}; + +enum cv_standard { + CV_STANDARD_UNKNOWN = 0x0000, + CV_STANDARD_HD_MASK = 0x0800, /* Flag mask HDTV output */ + CV_STANDARD_SD_NTSC_MASK = 0x1000, /* Flag mask NTSC output */ + CV_STANDARD_SD_NTSC_M, /* NTSC (North America) output 1001 */ + CV_STANDARD_SD_NTSC_J, /* NTSC (Japan) output 1002 */ + CV_STANDARD_SD_480I, /* SDTV 480i output 1003 */ + CV_STANDARD_SD_480P, /* SDTV 480p output 1004 */ + CV_STANDARD_HD_720_60P = 0x1800,/* HDTV 720/60p output 1800 */ + CV_STANDARD_HD_1080_60I, /* HDTV 1080/60i output 1801 */ + CV_STANDARD_SD_PAL_MASK = 0x2000,/* Flag mask PAL output */ + CV_STANDARD_SD_PAL_B, /* PAL B output 2001 */ + CV_STANDARD_SD_PAL_D, /* PAL D output 2002 */ + CV_STANDARD_SD_PAL_G, /* PAL G output 2003 */ + CV_STANDARD_SD_PAL_H, /* PAL H output 2004 */ + CV_STANDARD_SD_PAL_I, /* PAL I output 2005 */ + CV_STANDARD_SD_PAL_M, /* PAL M output 2006 */ + CV_STANDARD_SD_PAL_N, /* PAL N output 2007 */ + CV_STANDARD_SD_PAL_N_COMB, /* PAL Combination N output 2008 */ + CV_STANDARD_SD_PAL_60, /* PAL 60 output (test mode) 2009 */ + CV_STANDARD_SD_576I, /* SDTV 576i output 2010 */ + CV_STANDARD_SD_576P, /* SDTV 576p output 2011 */ + CV_STANDARD_HD_720_50P = 0x2800,/* HDTV 720/50p output 2800 */ + CV_STANDARD_HD_1080_50I, /* HDTV 1080/50i output 2801 */ + CV_STANDARD_SD_SECAM_MASK = 0x4000, /* Flag mask SECAM output */ + CV_STANDARD_SD_SECAM_B, /* SECAM B output 4001 */ + CV_STANDARD_SD_SECAM_D, /* SECAM D output 4002 */ + CV_STANDARD_SD_SECAM_G, /* SECAM G output 4003 */ + CV_STANDARD_SD_SECAM_H, /* SECAM H output 4004 */ + CV_STANDARD_SD_SECAM_K, /* SECAM K output 4005 */ + CV_STANDARD_SD_SECAM_K1, /* SECAM K1 output 4006 */ + CV_STANDARD_SD_SECAM_L, /* SECAM L output 4007 */ + CV_STANDARD_SD_SECAM_L1 /* SECAM L1 output 4009 */ +}; + +enum display_output_bit_depth { + PANEL_UNDEFINE = 0, + PANEL_6BIT_COLOR = 1, + PANEL_8BIT_COLOR = 2, + PANEL_10BIT_COLOR = 3, + PANEL_12BIT_COLOR = 4, + PANEL_16BIT_COLOR = 5, +}; + +enum lcd_scale { + /* No request to turn on LCD SCALER (Centering or Replication) */ + LCD_SCALE_NONE = 0, + /* Request LCD SCALER in full panel mode */ + LCD_SCALE_FULLPANEL, + /* Request LCD SCALER in aspect-ratio mode */ + LCD_SCALE_ASPECTRATIO, + + LCD_SCALE_UNKNOWN = (-1L), +}; + +/* Device type as abstracted by ATOM BIOS */ +enum dal_device_type { + DEVICE_TYPE_UNKNOWN = 0, + DEVICE_TYPE_LCD, + DEVICE_TYPE_CRT, + DEVICE_TYPE_DFP, + DEVICE_TYPE_CV, + DEVICE_TYPE_TV, + DEVICE_TYPE_CF, + DEVICE_TYPE_WIRELESS +}; + +/* Device ID as abstracted by ATOM BIOS */ +struct device_id { + enum dal_device_type device_type:16; + uint32_t enum_id:16; /* 1 based enum */ +}; + +struct graphics_object_i2c_info { + struct gpio_info { + uint32_t clk_mask_register_index; + uint32_t clk_en_register_index; + uint32_t clk_y_register_index; + uint32_t clk_a_register_index; + uint32_t data_mask_register_index; + uint32_t data_en_register_index; + uint32_t data_y_register_index; + uint32_t data_a_register_index; + + uint32_t clk_mask_shift; + uint32_t clk_en_shift; + uint32_t clk_y_shift; + uint32_t clk_a_shift; + uint32_t data_mask_shift; + uint32_t data_en_shift; + uint32_t data_y_shift; + uint32_t data_a_shift; + } gpio_info; + + bool i2c_hw_assist; + uint32_t i2c_line; + uint32_t i2c_engine_id; + uint32_t i2c_slave_address; +}; + + +struct graphics_object_hpd_info { + uint8_t hpd_int_gpio_uid; + uint8_t hpd_active; +}; + +struct connector_device_tag_info { + uint32_t acpi_device; + struct device_id dev_id; +}; + +struct device_timing { + struct misc_info { + uint32_t HORIZONTAL_CUT_OFF:1; + /* 0=Active High, 1=Active Low */ + uint32_t H_SYNC_POLARITY:1; + /* 0=Active High, 1=Active Low */ + uint32_t V_SYNC_POLARITY:1; + uint32_t VERTICAL_CUT_OFF:1; + uint32_t H_REPLICATION_BY2:1; + uint32_t V_REPLICATION_BY2:1; + uint32_t COMPOSITE_SYNC:1; + uint32_t INTERLACE:1; + uint32_t DOUBLE_CLOCK:1; + uint32_t RGB888:1; + uint32_t GREY_LEVEL:2; + uint32_t SPATIAL:1; + uint32_t TEMPORAL:1; + uint32_t API_ENABLED:1; + } misc_info; + + uint32_t pixel_clk; /* in KHz */ + uint32_t horizontal_addressable; + uint32_t horizontal_blanking_time; + uint32_t vertical_addressable; + uint32_t vertical_blanking_time; + uint32_t horizontal_sync_offset; + uint32_t horizontal_sync_width; + uint32_t vertical_sync_offset; + uint32_t vertical_sync_width; + uint32_t horizontal_border; + uint32_t vertical_border; +}; + +struct supported_refresh_rate { + uint32_t REFRESH_RATE_30HZ:1; + uint32_t REFRESH_RATE_40HZ:1; + uint32_t REFRESH_RATE_48HZ:1; + uint32_t REFRESH_RATE_50HZ:1; + uint32_t REFRESH_RATE_60HZ:1; +}; + +struct embedded_panel_info { + struct device_timing lcd_timing; + uint32_t ss_id; + struct supported_refresh_rate supported_rr; + uint32_t drr_enabled; + uint32_t min_drr_refresh_rate; +}; + +struct embedded_panel_patch_mode { + uint32_t width; + uint32_t height; +}; + +struct firmware_info { + struct pll_info { + uint32_t crystal_frequency; /* in KHz */ + uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */ + uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */ + uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */ + uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */ + } pll_info; + + struct firmware_feature { + uint32_t memory_clk_ss_percentage; + uint32_t engine_clk_ss_percentage; + } feature; + + uint32_t default_display_engine_pll_frequency; /* in KHz */ + uint32_t external_clock_source_frequency_for_dp; /* in KHz */ + uint32_t smu_gpu_pll_output_freq; /* in KHz */ + uint8_t min_allowed_bl_level; + uint8_t remote_display_config; +}; + +/* direct HW (mmBIOS_SCRATCH_2) translation! */ +union tv_standard_support { + uint8_t u_all; + struct { + bool TV_SUPPORT_NTSC:1; + bool TV_SUPPORT_NTSCJ:1; + + bool TV_SUPPORT_PAL:1; + bool TV_SUPPORT_PALM:1; + bool TV_SUPPORT_PALCN:1; + bool TV_SUPPORT_PALN:1; + bool TV_SUPPORT_PAL60:1; + + bool TV_SUPPORT_SECAM:1; + } bits; +}; + +struct analog_tv_info { + union tv_standard_support tv_suppported; + union tv_standard_support tv_boot_up_default; +}; + +struct step_and_delay_info { + uint32_t step; + uint32_t delay; + uint32_t recommended_ref_div; +}; + +struct spread_spectrum_info { + struct spread_spectrum_type { + bool CENTER_MODE:1; + bool EXTERNAL:1; + bool STEP_AND_DELAY_INFO:1; + } type; + + /* in unit of 0.01% (spreadPercentageDivider = 100), + otherwise in 0.001% units (spreadPercentageDivider = 1000); */ + uint32_t spread_spectrum_percentage; + uint32_t spread_percentage_divider; /* 100 or 1000 */ + uint32_t spread_spectrum_range; /* modulation freq (HZ)*/ + + union { + struct step_and_delay_info step_and_delay_info; + /* For mem/engine/uvd, Clock Out frequence (VCO ), + in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock, + for DP, it is link clock ( 270000 or 162000 ) */ + uint32_t target_clock_range; /* in KHz */ + }; + +}; + +struct graphics_object_encoder_cap_info { + uint32_t dp_hbr2_cap:1; + uint32_t dp_hbr2_validated:1; + uint32_t reserved:15; +}; + +struct din_connector_info { + uint32_t gpio_id; + bool gpio_tv_active_state; +}; + +/* Invalid channel mapping */ +enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 }; + +/** + * DDI PHY channel mapping reflecting XBAR setting + */ +union ddi_channel_mapping { + struct mapping { + uint8_t lane0:2; /* Mapping for lane 0 */ + uint8_t lane1:2; /* Mapping for lane 1 */ + uint8_t lane2:2; /* Mapping for lane 2 */ + uint8_t lane3:2; /* Mapping for lane 3 */ + } mapping; + uint8_t raw; +}; + +/** +* Transmitter output configuration description +*/ +struct transmitter_configuration_info { + /* DDI PHY ID for the transmitter */ + enum transmitter transmitter_phy_id; + /* DDI PHY channel mapping reflecting crossbar setting */ + union ddi_channel_mapping output_channel_mapping; +}; + +struct transmitter_configuration { + /* Configuration for the primary transmitter */ + struct transmitter_configuration_info primary_transmitter_config; + /* Secondary transmitter configuration for Dual-link DVI */ + struct transmitter_configuration_info secondary_transmitter_config; +}; + + +/* These size should be sufficient to store info coming from BIOS */ +#define NUMBER_OF_UCHAR_FOR_GUID 16 +#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 +#define NUMBER_OF_CSR_M3_ARB 10 +#define NUMBER_OF_DISP_CLK_VOLTAGE 4 +#define NUMBER_OF_AVAILABLE_SCLK 5 + +/* V6 */ +struct integrated_info { + struct clock_voltage_caps { + /* The Voltage Index indicated by FUSE, same voltage index + shared with SCLK DPM fuse table */ + uint32_t voltage_index; + /* Maximum clock supported with specified voltage index */ + uint32_t max_supported_clk; /* in KHz */ + } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE]; + + struct display_connection_info { + struct external_display_path { + /* A bit vector to show what devices are supported */ + uint32_t device_tag; + /* 16bit device ACPI id. */ + uint32_t device_acpi_enum; + /* A physical connector for displays to plug in, + using object connector definitions */ + struct graphics_object_id device_connector_id; + /* An index into external AUX/DDC channel LUT */ + uint8_t ext_aux_ddc_lut_index; + /* An index into external HPD pin LUT */ + uint8_t ext_hpd_pin_lut_index; + /* external encoder object id */ + struct graphics_object_id ext_encoder_obj_id; + /* XBAR mapping of the PHY channels */ + union ddi_channel_mapping channel_mapping; + } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; + + uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID]; + uint8_t checksum; + } ext_disp_conn_info; /* exiting long long time */ + + struct available_s_clk_list { + /* Maximum clock supported with specified voltage index */ + uint32_t supported_s_clk; /* in KHz */ + /* The Voltage Index indicated by FUSE for specified SCLK */ + uint32_t voltage_index; + /* The Voltage ID indicated by FUSE for specified SCLK */ + uint32_t voltage_id; + } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK]; + + uint8_t memory_type; + uint8_t ma_channel_number; + uint32_t boot_up_engine_clock; /* in KHz */ + uint32_t dentist_vco_freq; /* in KHz */ + uint32_t boot_up_uma_clock; /* in KHz */ + uint32_t boot_up_req_display_vector; + uint32_t other_display_misc; + uint32_t gpu_cap_info; + uint32_t sb_mmio_base_addr; + uint32_t system_config; + uint32_t cpu_cap_info; + uint32_t max_nb_voltage; + uint32_t min_nb_voltage; + uint32_t boot_up_nb_voltage; + uint32_t ext_disp_conn_info_offset; + uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB]; + uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB]; + uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB]; + uint32_t gmc_restore_reset_time; + uint32_t minimum_n_clk; + uint32_t idle_n_clk; + uint32_t ddr_dll_power_up_time; + uint32_t ddr_pll_power_up_time; + /* start for V6 */ + uint32_t pcie_clk_ss_type; + uint32_t lvds_ss_percentage; + uint32_t lvds_sspread_rate_in_10hz; + uint32_t hdmi_ss_percentage; + uint32_t hdmi_sspread_rate_in_10hz; + uint32_t dvi_ss_percentage; + uint32_t dvi_sspread_rate_in_10_hz; + uint32_t sclk_dpm_boost_margin; + uint32_t sclk_dpm_throttle_margin; + uint32_t sclk_dpm_tdp_limit_pg; + uint32_t sclk_dpm_tdp_limit_boost; + uint32_t boost_engine_clock; + uint32_t boost_vid_2bit; + uint32_t enable_boost; + uint32_t gnb_tdp_limit; + /* Start from V7 */ + uint32_t max_lvds_pclk_freq_in_single_link; + uint32_t lvds_misc; + uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms; + uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms; + uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms; + uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms; + uint32_t lvds_off_to_on_delay_in_4ms; + uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms; + uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms; + uint32_t lvds_reserved1; + uint32_t lvds_bit_depth_control_val; +}; + +/** +* Power source ids. +*/ +enum power_source { + POWER_SOURCE_AC = 0, + POWER_SOURCE_DC, + POWER_SOURCE_LIMITED_POWER, + POWER_SOURCE_LIMITED_POWER_2, + POWER_SOURCE_MAX +}; + +struct bios_event_info { + uint32_t thermal_state; + uint32_t backlight_level; + enum power_source powerSource; + bool has_thermal_state_changed; + bool has_power_source_changed; + bool has_forced_mode_changed; + bool forced_mode; + bool backlight_changed; +}; + +union stereo_3d_support { + struct { + /* HW can alter left and right image sequentially */ + uint32_t FRAME_ALTERNATE:1; + /* Frame Alternate + HW can integrate stereosync + signal into TMDS stream */ + uint32_t DVI_FRAME_ALT:1; + /* Frame Alternate + HW can integrate stereosync + signal into DP stream */ + uint32_t DISPLAY_PORT_FRAME_ALT:1; + /* Frame Alternate + HW can drive stereosync signal + on separate line */ + uint32_t SIDEBAND_FRAME_ALT:1; + /* SW allowed to pack left and right image into single frame. + Used for HDMI only, DP has it's own flags. */ + uint32_t SW_FRAME_PACK:1; + /* HW can pack left and right image into single HDMI frame */ + uint32_t PROGRESSIVE_FRAME_PACK:1; + /* HW can pack left and right interlaced images into + single HDMI frame */ + uint32_t INTERLACE_FRAME_PACK:1; + /* HW can pack left and right images into single DP frame */ + uint32_t DISPLAY_PORT_FRAME_PACK:1; + /* SW can pack left and right images into single DP frame */ + uint32_t DISPLAY_PORT_SW_FRAME_PACK:1; + /* HW can mix left and right images into single image */ + uint32_t INTERLEAVE:1; + /* HW can mix left and right interlaced images + into single image */ + uint32_t INTERLACE_INTERLEAVE:1; + /* Allow display-based formats (whatever supported) + in WS stereo mode */ + uint32_t DISPLAY_3DIN_WS_MODE:1; + /* Side-by-side, packed by application/driver into 2D frame */ + uint32_t SIDE_BY_SIDE_SW_PACKED:1; + /* Top-and-bottom, packed by application/driver into 2D frame */ + uint32_t TOP_AND_BOTTOM_SW_PACKED:1; + } bits; + uint32_t u_all; +}; + +/* Bitvector and bitfields of possible optimizations + #IMPORTANT# Keep bitfields match bitvector! */ +enum optimization_feature { + /* Don't do HW programming on panels that were enabled by VBIOS */ + OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY = 0x1, + OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME = 0x2, + OF_SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME = 0x4, + OF_SKIP_POWER_UP_VBIOS_ENABLED_ENCODER = 0x8, + /* Do not turn off VCC while powering down on boot or resume */ + OF_KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME = 0x10, + /* Do not turn off VCC while performing SetMode */ + OF_KEEP_VCC_DURING_SET_MODE = 0x20, + OF_DO_NOT_WAIT_FOR_HPD_LOW = 0x40, + OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80 +}; + +union optimization_flags { + struct { + /* Don't do HW programming if panels were enabled by VBIOS */ + uint32_t SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:1; + uint32_t SKIP_RESET_OF_ALL_HW_ON_S3RESUME:1; + uint32_t SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME:1; + uint32_t SKIP_POWER_UP_VBIOS_ENABLED_ENCODER:1; + /* Do not turn off VCC while powering down on boot or resume */ + uint32_t KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME:1; + /* Do not turn off VCC while performing SetMode */ + uint32_t KEEP_VCC_DURING_SET_MODE:1; + uint32_t DO_NOT_WAIT_FOR_HPD_LOW:1; + } bits; + uint32_t u_all; +}; + +/* Bitvector and bitfields of performance measurements + #IMPORTANT# Keep bitfields match bitvector! */ +enum perf_measure { + PERF_MEASURE_ADAPTER_POWER_STATE = 0x1, + PERF_MEASURE_DISPLAY_POWER_STATE = 0x2, + PERF_MEASURE_SET_MODE_SEQ = 0x4, + PERF_MEASURE_DETECT_AT_RESUME = 0x8, + PERF_MEASURE_MEMORY_READ_CONTROL = 0x10, +}; + +union perf_measure_flags { + struct { + uint32_t ADAPTER_POWER_STATE:1; + uint32_t DISPLAY_POWER_STATE:1; + uint32_t SET_MODE_SEQ:1; + uint32_t DETECT_AT_RESUME:1; + uint32_t MEMORY_READ_CONTROL:1; + + } bits; + uint32_t u_all; +}; + +enum { + PERF_MEASURE_POWERCODE_OFFSET = 0x0, + PERF_MEASURE_POWER_CODE_MASK = 0xFF, + PERF_MEASURE_POWER_STATE_OFFSET = 8, + PERF_MEASURE_POWER_STATE_MASK = 0x000FF00, + PERF_MEASURE_PREV_POWER_STATE_OFFSET = 16, + PERF_MEASURE_PREV_POWER_STATE_MASK = 0x00FF0000, + PERF_MEASURE_DISPLAY_INDEX_OFFSET = 24, + PERF_MEASURE_DISPLAY_INDEX_MASK = 0xFF000000 +}; + +enum { + HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000, + TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000 +}; + +/* + * DFS-bypass flag + */ +/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */ +enum { + DFS_BYPASS_ENABLE = 0x10 +}; + +enum { + INVALID_BACKLIGHT = -1 +}; + +struct panel_backlight_boundaries { + uint32_t min_signal_level; + uint32_t max_signal_level; +}; + +struct panel_backlight_default_levels { + uint32_t ac_level_percentage; + uint32_t dc_level_percentage; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h new file mode 100644 index 000000000000..a1e468fbbb2b --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h @@ -0,0 +1,328 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GRPH_OBJECT_DEFS_H__ +#define __DAL_GRPH_OBJECT_DEFS_H__ + +#include "grph_object_id.h" + +/* ******************************************************************** + * ******************************************************************** + * + * These defines shared between All Graphics Objects + * + * ******************************************************************** + * ******************************************************************** + */ + +/* HPD unit id - HW direct translation */ +enum hpd_source_id { + HPD_SOURCEID1 = 0, + HPD_SOURCEID2, + HPD_SOURCEID3, + HPD_SOURCEID4, + HPD_SOURCEID5, + HPD_SOURCEID6, + + HPD_SOURCEID_COUNT, + HPD_SOURCEID_UNKNOWN +}; + +/* DDC unit id - HW direct translation */ +enum channel_id { + CHANNEL_ID_UNKNOWN = 0, + CHANNEL_ID_DDC1, + CHANNEL_ID_DDC2, + CHANNEL_ID_DDC3, + CHANNEL_ID_DDC4, + CHANNEL_ID_DDC5, + CHANNEL_ID_DDC6, + CHANNEL_ID_DDC_VGA, + CHANNEL_ID_I2C_PAD, + CHANNEL_ID_COUNT +}; + +#define DECODE_CHANNEL_ID(ch_id) \ + (ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \ + (ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \ + (ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \ + (ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \ + (ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \ + (ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \ + (ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \ + (ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid" + +enum transmitter { + TRANSMITTER_UNKNOWN = (-1L), + TRANSMITTER_UNIPHY_A, + TRANSMITTER_UNIPHY_B, + TRANSMITTER_UNIPHY_C, + TRANSMITTER_UNIPHY_D, + TRANSMITTER_UNIPHY_E, + TRANSMITTER_UNIPHY_F, + TRANSMITTER_NUTMEG_CRT, + TRANSMITTER_TRAVIS_CRT, + TRANSMITTER_TRAVIS_LCD, + TRANSMITTER_UNIPHY_G, + TRANSMITTER_COUNT +}; + +enum physical_phy_id { + PHY_ID_UNKNOWN = (-1L), + PHY_ID_0, + PHY_ID_1, + PHY_ID_2, + PHY_ID_3, + PHY_ID_4, + PHY_ID_5, + PHY_ID_6, + PHY_ID_7, + PHY_ID_8, + PHY_ID_9, + PHY_ID_COUNT +}; + +/* Generic source of the synchronisation input/output signal */ +/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */ +enum sync_source { + SYNC_SOURCE_NONE = 0, + + /* Source based on controllers */ + SYNC_SOURCE_CONTROLLER0, + SYNC_SOURCE_CONTROLLER1, + SYNC_SOURCE_CONTROLLER2, + SYNC_SOURCE_CONTROLLER3, + SYNC_SOURCE_CONTROLLER4, + SYNC_SOURCE_CONTROLLER5, + + /* Source based on GSL group */ + SYNC_SOURCE_GSL_GROUP0, + SYNC_SOURCE_GSL_GROUP1, + SYNC_SOURCE_GSL_GROUP2, + + /* Source based on GSL IOs */ + /* These IOs normally used as GSL input/output */ + SYNC_SOURCE_GSL_IO_FIRST, + SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST, + SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC, + SYNC_SOURCE_GSL_IO_SWAPLOCK_A, + SYNC_SOURCE_GSL_IO_SWAPLOCK_B, + SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B, + + /* Source based on regular IOs */ + SYNC_SOURCE_IO_FIRST, + SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST, + SYNC_SOURCE_IO_GENERIC_B, + SYNC_SOURCE_IO_GENERIC_C, + SYNC_SOURCE_IO_GENERIC_D, + SYNC_SOURCE_IO_GENERIC_E, + SYNC_SOURCE_IO_GENERIC_F, + SYNC_SOURCE_IO_HPD1, + SYNC_SOURCE_IO_HPD2, + SYNC_SOURCE_IO_HSYNC_A, + SYNC_SOURCE_IO_VSYNC_A, + SYNC_SOURCE_IO_HSYNC_B, + SYNC_SOURCE_IO_VSYNC_B, + SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B, + + /* Misc. flow control sources */ + SYNC_SOURCE_DUAL_GPU_PIN +}; + +enum trigger_edge { + TRIGGER_EDGE_RISING = 0, + TRIGGER_EDGE_FALLING, + TRIGGER_EDGE_BOTH, + TRIGGER_EDGE_DEFAULT +}; + +/* Parameters to enable CRTC trigger */ +struct trigger_params { + enum sync_source source; + enum trigger_edge edge; +}; + +/* CRTC Static Screen event triggers */ +struct static_screen_events { + union { + /* event mask to enable/disable various + trigger sources for static screen detection */ + struct { + /* Force event high */ + uint32_t FRAME_START:1; + /* Cursor register change */ + uint32_t CURSOR_MOVE:1; + /* Memory write to any client other than MCIF */ + uint32_t MEM_WRITE:1; + /* Memory write to hit memory region 0 */ + uint32_t MEM_REGION0_WRITE:1; + /* Memory write to hit memory region 1 */ + uint32_t MEM_REGION1_WRITE:1; + /* Memory write to hit memory region 2 */ + uint32_t MEM_REGION2_WRITE:1; + /* Memory write to hit memory region 3 */ + uint32_t MEM_REGION3_WRITE:1; + /* Graphics Surface Update Pending */ + uint32_t GFX_UPDATE:1; + /* Overlay Surface Update Pending */ + uint32_t OVL_UPDATE:1; + /* Compressed surface invalidated in FBC */ + uint32_t INVALIDATE_FBC_SURFACE:1; + /* Register pending update in any double buffered + register group in the display pipe + (i.e. Blender, DCP, or SCL) */ + uint32_t REG_PENDING_UPDATE:1; + /* Crtc_trig_a: Based on signal from any other CRTC */ + uint32_t CRTC_TRIG_A:1; + /* Crtc_trig_b: Based on signal from any other CRTC */ + uint32_t CRTC_TRIG_B:1; + /* Readback of CRTC nominal vertical count register + by driver indicates that OS may be trying to change + mode or contents of the display therefore need to + switch to higher refresh rate */ + uint32_t READBACK_NOMINAL_VERTICAL:1; + /* Readback of CRTC dynamic vertical count register + by driver indicates that OS may be trying to change + mode or contents of the display therefore need to + switch to higher refresh rate */ + uint32_t READBACK_DYNAMIC_VERTICAL:1; + /* Reserved */ + uint32_t RESERVED:1; + } bits; + uint32_t u_all; + }; +}; + + +/* + * *************************************************************** + * ********************* Register programming sequences ******** + * *************************************************************** + */ + +/* GPIO/Register access sequences */ +enum io_register_sequence { + /* GLSync sequences to access SwapReady & SwapRequest + GPIOs - GLSync Connector parameter */ + IO_REG_SEQUENCE_SWAPREADY_SET = 0, + IO_REG_SEQUENCE_SWAPREADY_RESET, + IO_REG_SEQUENCE_SWAPREADY_READ, + IO_REG_SEQUENCE_SWAPREQUEST_SET, + IO_REG_SEQUENCE_SWAPREQUEST_RESET, + IO_REG_SEQUENCE_SWAPREQUEST_READ, + + /* Frame synchronization start/stop - display index parameter */ + IO_REG_SEQUENCE_FRAMELOCK_STOP, + IO_REG_SEQUENCE_FRAMELOCK_START, + + /* Flip lock/unlock - GLSync Connector parameter */ + IO_REG_SEQUENCE_GLOBALSWAP_LOCK, + IO_REG_SEQUENCE_GLOBALSWAP_UNLOCK, + + IO_REG_SEQUENCEENUM_MAX +}; + +#define IO_REGISTER_SEQUENCE_MAX_LENGTH 5 + +/* + ***************************************************************************** + * struct io_register + ***************************************************************************** + * Generic struct for read/write register or GPIO. + * It allows controlling only some bit section of register, rather then the + * whole one. + * For write operation should be used as following: + * 1. data = READ(Base + RegisterOffset) + * 2. data &= ANDMask + * 3. data |= ORMask + * 4. WRITE(Base + RegisterOffset, data) + * + * Note: In case of regular register, ANDMask will be typically 0. + * In case of GPIO, ANDMask will have typically all bits set + * except the specific GPIO bit. + * + * For read operation should be used as following: + * 1. data = READ(Base + RegisterOffset) + * 2. data &= ANDMask + * 3. data >>= BitShift + * + * Note: In case of regular register, ANDMask will be typically 0xFFFFFFFF. + * In case of GPIO, ANDMask will have typically only specific GPIO bit set + * + * Note: Base Address is not exposed in this structure due to + * security consideration. + */ + +/* + * The generic sequence to program/access registers or GPIOs. + * There could be 2 types of sequences - read and write. + * Read sequence may have 0 or more writes and in the end one read + * Write sequence may have 1 or more writes. + */ +struct io_reg_sequence { + /* Ordered array of register to program */ + struct { + /* Offset of memory mapped register or GPIO */ + uint32_t register_offset; + /* Mask to use at AND operation (Mandatory, comes + before OR operation) */ + uint32_t and_mask; + union { + /* Mask to use at OR operation (For write + sequence only, comes after AND operation) */ + uint32_t or_mask; + /* Number of bits to shift to get the actual value + (For read sequence only, comes after AND operation) */ + uint32_t bit_shift; + }; + } io_registers[IO_REGISTER_SEQUENCE_MAX_LENGTH]; + + uint32_t steps_num; /* Total number of r/w steps in the sequence */ +}; + +/* Sequence ID - uniqly defines sequence on single adapter */ +struct io_reg_sequence_id { + enum io_register_sequence sequence; /* Sequence enumeration Index/ID */ + union { + /* Refers to object to which the sequence applies.*/ + uint32_t index; + uint32_t display_index; + uint32_t controller_index; + uint32_t glsync_connector_index; + }; +}; + +struct fbc_info { + bool fbc_enable; + bool lpt_enable; +}; + +/* Event to request TM change IRQ registration state */ +struct hotplug_irq_data { + bool disable; + struct graphics_object_id connector; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h new file mode 100644 index 000000000000..372e46c9f0dd --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h @@ -0,0 +1,277 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GRPH_OBJECT_ID_H__ +#define __DAL_GRPH_OBJECT_ID_H__ + +/* Types of graphics objects */ +enum object_type { + OBJECT_TYPE_UNKNOWN = 0, + + /* Direct ATOM BIOS translation */ + OBJECT_TYPE_GPU, + OBJECT_TYPE_ENCODER, + OBJECT_TYPE_CONNECTOR, + OBJECT_TYPE_ROUTER, + OBJECT_TYPE_GENERIC, + + /* Driver specific */ + OBJECT_TYPE_AUDIO, + OBJECT_TYPE_CONTROLLER, + OBJECT_TYPE_CLOCK_SOURCE, + OBJECT_TYPE_ENGINE, + + OBJECT_TYPE_COUNT +}; + +/* Enumeration inside one type of graphics objects */ +enum object_enum_id { + ENUM_ID_UNKNOWN = 0, + ENUM_ID_1, + ENUM_ID_2, + ENUM_ID_3, + ENUM_ID_4, + ENUM_ID_5, + ENUM_ID_6, + ENUM_ID_7, + + ENUM_ID_COUNT +}; + +/* Generic object ids */ +enum generic_id { + GENERIC_ID_UNKNOWN = 0, + GENERIC_ID_MXM_OPM, + GENERIC_ID_GLSYNC, + GENERIC_ID_STEREO, + + GENERIC_ID_COUNT +}; + +/* Controller object ids */ +enum controller_id { + CONTROLLER_ID_UNDEFINED = 0, + CONTROLLER_ID_D0, + CONTROLLER_ID_D1, + CONTROLLER_ID_D2, + CONTROLLER_ID_D3, + CONTROLLER_ID_D4, + CONTROLLER_ID_D5, + CONTROLLER_ID_UNDERLAY0, + CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0 +}; + +#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0) + +/* + * ClockSource object ids. + * We maintain the order matching (more or less) ATOM BIOS + * to improve optimized acquire + */ +enum clock_source_id { + CLOCK_SOURCE_ID_UNDEFINED = 0, + CLOCK_SOURCE_ID_PLL0, + CLOCK_SOURCE_ID_PLL1, + CLOCK_SOURCE_ID_PLL2, + CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */ + CLOCK_SOURCE_ID_DCPLL, + CLOCK_SOURCE_ID_DFS, /* DENTIST */ + CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */ + /* Used to distinguish between programming pixel clock and ID (Phy) clock */ + CLOCK_SOURCE_ID_DP_DTO, + + CLOCK_SOURCE_COMBO_PHY_PLL0, + CLOCK_SOURCE_COMBO_PHY_PLL1, + CLOCK_SOURCE_COMBO_PHY_PLL2, + CLOCK_SOURCE_COMBO_PHY_PLL3, + CLOCK_SOURCE_COMBO_PHY_PLL4, + CLOCK_SOURCE_COMBO_PHY_PLL5, + CLOCK_SOURCE_COMBO_DISPLAY_PLL0 +}; + + +/* Encoder object ids */ +enum encoder_id { + ENCODER_ID_UNKNOWN = 0, + + /* Radeon Class Display Hardware */ + ENCODER_ID_INTERNAL_LVDS, + ENCODER_ID_INTERNAL_TMDS1, + ENCODER_ID_INTERNAL_TMDS2, + ENCODER_ID_INTERNAL_DAC1, + ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */ + + /* External Third Party Encoders */ + ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */ + ENCODER_ID_INTERNAL_HDMI, + + /* Kaledisope (KLDSCP) Class Display Hardware */ + ENCODER_ID_INTERNAL_KLDSCP_TMDS1, + ENCODER_ID_INTERNAL_KLDSCP_DAC1, + ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */ + /* External TMDS (dual link) */ + ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */ + ENCODER_ID_INTERNAL_DDI, + ENCODER_ID_INTERNAL_UNIPHY, + ENCODER_ID_INTERNAL_KLDSCP_LVTMA, + ENCODER_ID_INTERNAL_UNIPHY1, + ENCODER_ID_INTERNAL_UNIPHY2, + ENCODER_ID_EXTERNAL_NUTMEG, + ENCODER_ID_EXTERNAL_TRAVIS, + + ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */ + ENCODER_ID_INTERNAL_UNIPHY3, + ENCODER_ID_INTERNAL_VIRTUAL, +}; + + +/* Connector object ids */ +enum connector_id { + CONNECTOR_ID_UNKNOWN = 0, + CONNECTOR_ID_SINGLE_LINK_DVII = 1, + CONNECTOR_ID_DUAL_LINK_DVII = 2, + CONNECTOR_ID_SINGLE_LINK_DVID = 3, + CONNECTOR_ID_DUAL_LINK_DVID = 4, + CONNECTOR_ID_VGA = 5, + CONNECTOR_ID_HDMI_TYPE_A = 12, + CONNECTOR_ID_LVDS = 14, + CONNECTOR_ID_PCIE = 16, + CONNECTOR_ID_HARDCODE_DVI = 18, + CONNECTOR_ID_DISPLAY_PORT = 19, + CONNECTOR_ID_EDP = 20, + CONNECTOR_ID_MXM = 21, + CONNECTOR_ID_WIRELESS = 22, + CONNECTOR_ID_MIRACAST = 23, + + CONNECTOR_ID_VIRTUAL = 100 +}; + + +/* Audio object ids */ +enum audio_id { + AUDIO_ID_UNKNOWN = 0, + AUDIO_ID_INTERNAL_AZALIA +}; + + +/* Engine object ids */ +enum engine_id { + ENGINE_ID_DIGA, + ENGINE_ID_DIGB, + ENGINE_ID_DIGC, + ENGINE_ID_DIGD, + ENGINE_ID_DIGE, + ENGINE_ID_DIGF, + ENGINE_ID_DIGG, + ENGINE_ID_DACA, + ENGINE_ID_DACB, + ENGINE_ID_VCE, /* wireless display pseudo-encoder */ + ENGINE_ID_VIRTUAL, + + ENGINE_ID_COUNT, + ENGINE_ID_UNKNOWN = (-1L) +}; + +union supported_stream_engines { + struct { + uint32_t ENGINE_ID_DIGA:1; + uint32_t ENGINE_ID_DIGB:1; + uint32_t ENGINE_ID_DIGC:1; + uint32_t ENGINE_ID_DIGD:1; + uint32_t ENGINE_ID_DIGE:1; + uint32_t ENGINE_ID_DIGF:1; + uint32_t ENGINE_ID_DIGG:1; + uint32_t ENGINE_ID_DACA:1; + uint32_t ENGINE_ID_DACB:1; + uint32_t ENGINE_ID_VCE:1; + } engine; + uint32_t u_all; +}; + +enum transmitter_color_depth { + TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */ + TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */ + TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */ + TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */ +}; + +/* + ***************************************************************************** + * graphics_object_id struct + * + * graphics_object_id is a very simple struct wrapping 32bit Graphics + * Object identication + * + * This struct should stay very simple + * No dependencies at all (no includes) + * No debug messages or asserts + * No #ifndef and preprocessor directives + * No grow in space (no more data member) + ***************************************************************************** + */ + +struct graphics_object_id { + uint32_t id:8; + uint32_t enum_id:4; + uint32_t type:4; + uint32_t reserved:16; /* for padding. total size should be u32 */ +}; + +/* some simple functions for convenient graphics_object_id handle */ + +static inline struct graphics_object_id dal_graphics_object_id_init( + uint32_t id, + enum object_enum_id enum_id, + enum object_type type) +{ + struct graphics_object_id result = { + id, enum_id, type, 0 + }; + + return result; +} + +bool dal_graphics_object_id_is_valid( + struct graphics_object_id id); +bool dal_graphics_object_id_is_equal( + struct graphics_object_id id1, + struct graphics_object_id id2); +uint32_t dal_graphics_object_id_to_uint( + struct graphics_object_id id); + + +enum controller_id dal_graphics_object_id_get_controller_id( + struct graphics_object_id id); +enum clock_source_id dal_graphics_object_id_get_clock_source_id( + struct graphics_object_id id); +enum encoder_id dal_graphics_object_id_get_encoder_id( + struct graphics_object_id id); +enum connector_id dal_graphics_object_id_get_connector_id( + struct graphics_object_id id); +enum audio_id dal_graphics_object_id_get_audio_id( + struct graphics_object_id id); +enum engine_id dal_graphics_object_id_get_engine_id( + struct graphics_object_id id); +#endif diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h new file mode 100644 index 000000000000..ddd78d6c97e3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h @@ -0,0 +1,388 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HW_SEQUENCER_INTERFACE_H__ +#define __DAL_HW_SEQUENCER_INTERFACE_H__ + +#include "hw_sequencer_types.h" +#include "hw_adjustment_types.h" +#include "include/display_clock_interface.h" +#include "include/scaler_types.h" +#include "include/grph_csc_types.h" +#include "plane_types.h" + +#include "adapter_service_interface.h" + +enum hwss_result { + HWSS_RESULT_OK, + HWSS_RESULT_ERROR, + HWSS_RESULT_NO_BANDWIDTH, + HWSS_RESULT_OUT_OF_RANGE, + HWSS_RESULT_NOT_SUPPORTED, + HWSS_RESULT_UNKNOWN +}; + +struct hws_init_data { + struct adapter_service *as; + struct dal_context *dal_context; +}; + +/* TODO: below is three almost equal structures. + * We should decide what to do with them */ +struct blank_stream_param { + struct display_path *display_path; + uint32_t link_idx; + struct hw_crtc_timing timing; + struct link_settings link_settings; +}; + +struct enable_stream_param { + struct display_path *display_path; + uint32_t link_idx; + struct hw_crtc_timing timing; + struct link_settings link_settings; + + const struct hw_path_mode *path_mode; +}; + +struct enable_link_param { + struct display_path *display_path; + uint32_t link_idx; + struct hw_crtc_timing timing; + struct link_settings link_settings; + + bool optimized_programming; + const struct hw_path_mode *path_mode; +}; + +struct validate_link_param { + const struct display_path *display_path; + uint32_t link_idx; + struct link_settings link_settings; +}; + +struct set_dp_phy_pattern_param { + struct display_path *display_path; + uint32_t link_idx; + enum dp_test_pattern test_pattern; + const uint8_t *custom_pattern; + uint32_t cust_pattern_size; +}; + +struct hw_global_objects; +struct hw_sequencer; +struct hw_adjustment; +struct hw_path_mode_set; +struct hw_path_mode; +struct hwss_build_params; +struct controller; + +void dal_hw_sequencer_mute_audio_endpoint( + struct hw_sequencer *hws, + struct display_path *display_path, + bool mute); + +void dal_hw_sequencer_enable_audio_endpoint( + struct hw_sequencer *hws, + struct link_settings *ls, + struct display_path *display_path, + bool enable); + +enum hwss_result dal_hw_sequencer_reset_audio_device( + struct hw_sequencer *hws, + struct display_path *display_path); + +enum hwss_result dal_hw_sequencer_validate_link( + struct hw_sequencer *hws, + const struct validate_link_param *param); + +bool dal_hw_sequencer_is_supported_dp_training_pattern3( + struct hw_sequencer *hws, + struct display_path *display_path, + uint32_t link_idx); + +enum hwss_result dal_hw_sequencer_set_dp_phy_pattern( + struct hw_sequencer *hws, + const struct set_dp_phy_pattern_param *param); + +enum hwss_result dal_hw_sequencer_set_lane_settings( + struct hw_sequencer *hws, + struct display_path *display_path, + const struct link_training_settings *link_settings); + +void dal_hw_sequencer_set_test_pattern( + struct hw_sequencer *hws, + struct hw_path_mode *path_mode, + enum dp_test_pattern test_pattern, + const struct link_training_settings *link_settings, + const uint8_t *custom_pattern, + uint8_t cust_pattern_size); + +bool dal_hw_sequencer_has_audio_bandwidth_changed( + struct hw_sequencer *hws, + const struct hw_path_mode *old, + const struct hw_path_mode *new); + +void dal_hw_sequencer_enable_azalia_audio_jack_presence( + struct hw_sequencer *hws, + struct display_path *display_path); + +void dal_hw_sequencer_disable_azalia_audio_jack_presence( + struct hw_sequencer *hws, + struct display_path *display_path); + +void dal_hw_sequencer_enable_memory_requests( + struct hw_sequencer *hws, + struct hw_path_mode *path_mode); + +void dal_hw_sequencer_update_info_packets( + struct hw_sequencer *hws, + struct hw_path_mode *path_mode); + +/* Static validation for a SINGLE path mode. + * Already "active" paths (if any) are NOT taken into account. */ +enum hwss_result dal_hw_sequencer_validate_display_path_mode( + struct hw_sequencer *hws, + const struct hw_path_mode *path_mode); + +/* Validation for a SET of path modes, including Video Memory Bandwidth + * validation. */ +enum hwss_result dal_hw_sequencer_validate_display_hwpms( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set); + +struct hw_adjustment_gamma_ramp; + +enum hwss_result dal_hw_sequencer_set_gamma_ramp_adjustment( + struct hw_sequencer *hws, + const struct display_path *display_path, + struct hw_adjustment_gamma_ramp *adjusment); + +enum hwss_result dal_hw_sequencer_set_color_control_adjustment( + struct hw_sequencer *hws, + struct controller *crtc, + struct hw_adjustment_color_control *adjustment); + +enum hwss_result dal_hw_sequencer_set_vertical_sync_adjustment( + struct hw_sequencer *hws, + struct display_path *display_path, + struct hw_adjustment_value *adjustment); + +enum hwss_result dal_hw_sequencer_set_horizontal_sync_adjustment( + struct hw_sequencer *hws, + struct display_path *display_path, + struct hw_adjustment_value *adjustment); + +enum hwss_result dal_hw_sequencer_set_composite_sync_adjustment( + struct hw_sequencer *hws, + struct display_path *display_path, + struct hw_adjustment_value *adjustment); + +enum hwss_result dal_hw_sequencer_enable_sync_output( + struct hw_sequencer *hws, + struct display_path *display_path); + +enum hwss_result dal_hw_sequencer_disable_sync_output( + struct hw_sequencer *hws, + struct display_path *display_path); + +enum hwss_result dal_hw_sequencer_set_backlight_adjustment( + struct hw_sequencer *hws, + struct display_path *display_path, + struct hw_adjustment_value *adjustment); + +void dal_hw_sequencer_disable_memory_requests( + struct hw_sequencer *hws, + const struct hw_path_mode *path_mode); + +enum hwss_result dal_hw_sequencer_enable_link( + struct hw_sequencer *hws, + const struct enable_link_param *in); + +void dal_hw_sequencer_disable_link( + struct hw_sequencer *hws, + const struct enable_link_param *in); + +void dal_hw_sequencer_enable_stream( + struct hw_sequencer *hws, + const struct enable_stream_param *in); + +void dal_hw_sequencer_disable_stream( + struct hw_sequencer *hws, + const struct enable_stream_param *in); + +void dal_hw_sequencer_blank_stream( + struct hw_sequencer *hws, + const struct blank_stream_param *in); + +void dal_hw_sequencer_unblank_stream( + struct hw_sequencer *hws, + const struct blank_stream_param *in); + +enum hwss_result dal_hw_sequencer_set_clocks_and_clock_state( + struct hw_sequencer *hws, + struct hw_global_objects *g_obj, + const struct minimum_clocks_calculation_result *min_clk_in, + enum clocks_state required_clocks_state); + +enum hwss_result dal_hw_sequencer_set_mode( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set); + +enum signal_type dal_hw_sequencer_detect_sink( + struct hw_sequencer *hws, + struct display_path *display_path); + +enum signal_type dal_hw_sequencer_detect_load( + struct hw_sequencer *hws, + struct display_path *display_path); + +bool dal_hw_sequencer_is_sink_present( + struct hw_sequencer *hws, + struct display_path *display_path); + +void dal_hw_sequencer_psr_setup( + struct hw_sequencer *hws, + const struct hw_path_mode *path_mode, + const struct psr_caps *psr_caps); + +void dal_hw_sequencer_psr_enable( + struct hw_sequencer *hws, + struct display_path *display_path); + +void dal_hw_sequencer_psr_disable( + struct hw_sequencer *hws, + struct display_path *display_path); + +void dal_hw_sequencer_program_drr( + struct hw_sequencer *hws, + const struct hw_path_mode *path_mode); + +enum hwss_result dal_hw_sequencer_set_safe_displaymark( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set); + +enum hwss_result dal_hw_sequencer_set_displaymark( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set); + +void dal_hw_sequencer_destroy(struct hw_sequencer **hws); + +struct hw_sequencer *dal_hw_sequencer_create( + struct hws_init_data *hws_init_data); + +enum hwss_result dal_hw_sequencer_set_overscan_adj( + struct hw_sequencer *hws, + struct hw_path_mode_set *set, + struct hw_underscan_adjustment_data *hw_underscan); + +bool dal_hw_sequencer_enable_line_buffer_power_gating( + struct line_buffer *lb, + enum controller_id id, + enum pixel_type pixel_type, + uint32_t src_pixel_width, + uint32_t dst_pixel_width, + struct scaling_taps *taps, + enum lb_pixel_depth lb_depth, + uint32_t src_height, + uint32_t dst_height, + bool interlaced); + +void dal_hw_sequencer_build_scaler_parameter( + const struct hw_path_mode *path_mode, + const struct scaling_taps *taps, + bool build_timing_required, + struct scaler_data *scaler_data); + +void dal_hw_sequencer_update_info_frame( + const struct hw_path_mode *hw_path_mode); + +enum hwss_result dal_hw_sequencer_set_bit_depth_reduction_adj( + struct hw_sequencer *hws, + struct display_path *disp_path, + union hw_adjustment_bit_depth_reduction *bit_depth); + +bool dal_hw_sequencer_is_support_custom_gamut_adj( + struct hw_sequencer *hws, + struct display_path *disp_path, + enum hw_surface_type surface_type); + +enum hwss_result dal_hw_sequencer_get_hw_color_adj_range( + struct hw_sequencer *hws, + struct display_path *disp_path, + struct hw_color_control_range *hw_color_range); + +bool dal_hw_sequencer_is_support_custom_gamma_coefficients( + struct hw_sequencer *hws, + struct display_path *disp_path, + enum hw_surface_type surface_type); + +enum hwss_result dal_hw_sequencer_build_csc_adjust( + struct hw_sequencer *hws, + struct hw_adjustment_color_control *color_control, + struct grph_csc_adjustment *adjust); + +void dal_hw_sequencer_build_gamma_ramp_adj_params( + const struct hw_adjustment_gamma_ramp *adjusment, + struct gamma_parameters *gamma_param, + struct gamma_ramp *ramp); + +void translate_from_hw_to_controller_regamma( + const struct hw_regamma_lut *hw_regamma, + struct regamma_lut *regamma); + +void dal_hw_sequencer_enable_wireless_idle_detection( + struct hw_sequencer *hws, + bool enable); + +/* Cursor interface */ +enum hwss_result dal_hw_sequencer_set_cursor_position( + struct hw_sequencer *hws, + struct display_path *dp, + const struct dc_cursor_position *position); + +enum hwss_result dal_hw_sequencer_set_cursor_attributes( + struct hw_sequencer *hws, + struct display_path *dp, + const struct dc_cursor_attributes *attributes); + +/* Underlay/MPO interface */ +enum hwss_result dal_hw_sequencer_set_plane_config( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set, + uint32_t display_index); + +bool dal_hw_sequencer_update_plane_address( + struct hw_sequencer *hws, + struct display_path *dp, + uint32_t num_planes, + struct plane_addr_flip_info *info); + +void dal_hw_sequencer_prepare_to_release_planes( + struct hw_sequencer *hws, + struct hw_path_mode_set *path_set, + uint32_t display_index); + +#endif /* __DAL_HW_SEQUENCER_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h new file mode 100644 index 000000000000..ad7b90605d75 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h @@ -0,0 +1,304 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HW_SEQUENCER_TYPES_H__ +#define __DAL_HW_SEQUENCER_TYPES_H__ + +#include "signal_types.h" +#include "grph_object_defs.h" +#include "link_service_types.h" + +struct color_quality { + uint32_t bpp_graphics; + uint32_t bpp_backend_video; +}; + +enum { + HW_MAX_NUM_VIEWPORTS = 2, + HW_CURRENT_PIPE_INDEX = 0, + HW_OTHER_PIPE_INDEX = 1 +}; + +struct hw_view_port_adjustment { + int32_t start_adjustment; + int32_t width; + + enum controller_id controller_id; +}; + +struct hw_view_port_adjustments { + uint32_t view_ports_num; + struct hw_view_port_adjustment adjustments[HW_MAX_NUM_VIEWPORTS]; +}; + +/* Timing standard */ +enum hw_timing_standard { + HW_TIMING_STANDARD_UNDEFINED, + HW_TIMING_STANDARD_DMT, + HW_TIMING_STANDARD_GTF, + HW_TIMING_STANDARD_CVT, + HW_TIMING_STANDARD_CVT_RB, + HW_TIMING_STANDARD_CEA770, + HW_TIMING_STANDARD_CEA861, + HW_TIMING_STANDARD_HDMI, + HW_TIMING_STANDARD_TV_NTSC, + HW_TIMING_STANDARD_TV_NTSC_J, + HW_TIMING_STANDARD_TV_PAL, + HW_TIMING_STANDARD_TV_PAL_M, + HW_TIMING_STANDARD_TV_PAL_CN, + HW_TIMING_STANDARD_TV_SECAM, + /* for explicit timings from VBIOS, EDID etc. */ + HW_TIMING_STANDARD_EXPLICIT +}; + +/* TODO: identical to struct crtc_ranged_timing_control + * defined in inc\timing_generator_types.h */ +struct hw_ranged_timing_control { + /* set to 1 to force dynamic counter V_COUNT + * to lock to constant rate counter V_COUNT_NOM + * on page flip event in dynamic refresh mode + * when switching from a low refresh rate to nominal refresh rate */ + bool force_lock_on_event; + /* set to 1 to force CRTC2 (slave) to lock to CRTC1 (master) VSync + * in order to overlap their blank regions for MC clock changes */ + bool lock_to_master_vsync; + + /* set to 1 to program Static Screen Detection Masks + * without enabling dynamic refresh rate */ + bool program_static_screen_mask; + /* set to 1 to program Dynamic Refresh Rate */ + bool program_dynamic_refresh_rate; + /* set to 1 to force disable Dynamic Refresh Rate */ + bool force_disable_drr; + + /* event mask to enable/disable various trigger sources + * for static screen detection */ + struct static_screen_events event_mask; + + /* Number of consecutive static screen frames before static state is + * asserted. */ + uint32_t static_frame_count; +}; + +/* define the structure of Dynamic Refresh Mode */ +struct hw_ranged_timing { + /* defines the minimum possible vertical dimension of display timing + * for CRTC as supported by the panel */ + uint32_t vertical_total_min; + /* defines the maximum possible vertical dimension of display timing + * for CRTC as supported by the panel */ + uint32_t vertical_total_max; + + struct hw_ranged_timing_control control; +}; + +/* CRTC timing structure */ +struct hw_crtc_timing { + uint32_t h_total; + uint32_t h_addressable; + uint32_t h_overscan_left; + uint32_t h_overscan_right; + uint32_t h_sync_start; + uint32_t h_sync_width; + + uint32_t v_total; + uint32_t v_addressable; + uint32_t v_overscan_top; + uint32_t v_overscan_bottom; + uint32_t v_sync_start; + uint32_t v_sync_width; + + struct hw_ranged_timing ranged_timing; + + /* in KHz */ + uint32_t pixel_clock; + + enum hw_timing_standard timing_standard; + enum dc_color_depth color_depth; + enum dc_pixel_encoding pixel_encoding; + + struct { + uint32_t INTERLACED:1; + uint32_t DOUBLESCAN:1; + uint32_t PIXEL_REPETITION:4; /* 1...10 */ + uint32_t HSYNC_POSITIVE_POLARITY:1; + uint32_t VSYNC_POSITIVE_POLARITY:1; + /* frame should be packed for 3D + * (currently this refers to HDMI 1.4a FramePacking format */ + uint32_t HORZ_COUNT_BY_TWO:1; + uint32_t PACK_3D_FRAME:1; + /* 0 - left eye polarity, 1 - right eye polarity */ + uint32_t RIGHT_EYE_3D_POLARITY:1; + /* DVI-DL High-Color mode */ + uint32_t HIGH_COLOR_DL_MODE:1; + uint32_t Y_ONLY:1; + /* HDMI 2.0 - Support scrambling for TMDS character + * rates less than or equal to 340Mcsc */ + uint32_t LTE_340MCSC_SCRAMBLE:1; + } flags; +}; + +struct hw_scaling_info { + struct view src; + struct view dst; + enum signal_type signal; +}; + +enum hw_color_space { + HW_COLOR_SPACE_UNKNOWN = 0, + HW_COLOR_SPACE_SRGB_FULL_RANGE, + HW_COLOR_SPACE_SRGB_LIMITED_RANGE, + HW_COLOR_SPACE_YPBPR601, + HW_COLOR_SPACE_YPBPR709, + HW_COLOR_SPACE_YCBCR601, + HW_COLOR_SPACE_YCBCR709, + HW_COLOR_SPACE_YCBCR601_YONLY, + HW_COLOR_SPACE_YCBCR709_YONLY, + HW_COLOR_SPACE_NMVPU_SUPERAA, +}; + +enum hw_overlay_color_space { + HW_OVERLAY_COLOR_SPACE_UNKNOWN, + HW_OVERLAY_COLOR_SPACE_BT709, + HW_OVERLAY_COLOR_SPACE_BT601, + HW_OVERLAY_COLOR_SPACE_SMPTE240, + HW_OVERLAY_COLOR_SPACE_RGB +}; + +enum hw_overlay_backend_bpp { + HW_OVERLAY_BACKEND_BPP_UNKNOWN, + HW_OVERLAY_BACKEND_BPP32_FULL_BANDWIDTH, + HW_OVERLAY_BACKEND_BPP16_FULL_BANDWIDTH, + HW_OVERLAY_BACKEND_BPP32_HALF_BANDWIDTH, +}; +enum hw_overlay_format { + HW_OVERLAY_FORMAT_UNKNOWN, + HW_OVERLAY_FORMAT_YUY2, + HW_OVERLAY_FORMAT_UYVY, + HW_OVERLAY_FORMAT_RGB565, + HW_OVERLAY_FORMAT_RGB555, + HW_OVERLAY_FORMAT_RGB32, + HW_OVERLAY_FORMAT_YUV444, + HW_OVERLAY_FORMAT_RGB32_2101010 +}; + +enum hw_scale_options { + HW_SCALE_OPTION_UNKNOWN, + HW_SCALE_OPTION_OVERSCAN, /* multimedia pass through mode */ + HW_SCALE_OPTION_UNDERSCAN +}; + +enum hw_stereo_format { + HW_STEREO_FORMAT_NONE = 0, + HW_STEREO_FORMAT_SIDE_BY_SIDE = 1, + HW_STEREO_FORMAT_TOP_AND_BOTTOM = 2, + HW_STEREO_FORMAT_FRAME_ALTERNATE = 3, + HW_STEREO_FORMAT_ROW_INTERLEAVED = 5, + HW_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, + HW_STEREO_FORMAT_CHECKER_BOARD = 7 /* the same as pixel interleave */ +}; + +enum hw_dithering_options { + HW_DITHERING_OPTION_UNKNOWN, + HW_DITHERING_OPTION_SKIP_PROGRAMMING, + HW_DITHERING_OPTION_ENABLE, + HW_DITHERING_OPTION_DISABLE +}; + +struct hw_stereo_mixer_params { + bool sub_sampling; + bool single_pipe; +}; + + + +struct hw_action_flags { + uint32_t RESYNC_PATH:1; + uint32_t TIMING_CHANGED:1; + uint32_t PIXEL_ENCODING_CHANGED:1; + uint32_t GAMUT_CHANGED:1; + uint32_t TURN_OFF_VCC:1; +}; + +enum hw_sync_request { + HW_SYNC_REQUEST_NONE = 0, + HW_SYNC_REQUEST_SET_INTERPATH, + HW_SYNC_REQUEST_SET_GL_SYNC_GENLOCK, + HW_SYNC_REQUEST_SET_GL_SYNC_FREE_RUN, + HW_SYNC_REQUEST_SET_GL_SYNC_SHADOW, + HW_SYNC_REQUEST_RESET_GLSYNC, + HW_SYNC_REQUEST_RESYNC_GLSYNC, + HW_SYNC_REQUEST_SET_STEREO3D +}; + +struct hw_sync_info { + enum hw_sync_request sync_request; + uint32_t target_pixel_clock; /* in KHz */ + enum sync_source sync_source; +}; + +/* TODO hw_info_frame and hw_info_packet structures are same as in encoder + * merge it*/ +struct hw_info_packet { + bool valid; + uint8_t hb0; + uint8_t hb1; + uint8_t hb2; + uint8_t hb3; + uint8_t sb[28]; +}; + +struct hw_info_frame { + /* Auxiliary Video Information */ + struct hw_info_packet avi_info_packet; + struct hw_info_packet gamut_packet; + struct hw_info_packet vendor_info_packet; + /* Source Product Description */ + struct hw_info_packet spd_packet; + /* Video Stream Configuration */ + struct hw_info_packet vsc_packet; +}; + + +enum channel_command_type { + CHANNEL_COMMAND_I2C, + CHANNEL_COMMAND_I2C_OVER_AUX, + CHANNEL_COMMAND_AUX +}; + + +/* maximum TMDS transmitter pixel clock is 165 MHz. So it is KHz */ +#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 +#define NATIVE_HDMI_MAX_PIXEL_CLOCK_IN_KHZ 297000 + +struct hw_adjustment_range { + int32_t hw_default; + int32_t min; + int32_t max; + int32_t step; + uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h new file mode 100644 index 000000000000..b961d24d0e70 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h @@ -0,0 +1,127 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_I2CAUX_INTERFACE_H__ +#define __DAL_I2CAUX_INTERFACE_H__ + +#include "ddc_interface.h" +#include "adapter_service_interface.h" + +struct i2c_payload { + bool write; + uint8_t address; + uint8_t length; + uint8_t *data; +}; + +enum i2c_command_engine { + I2C_COMMAND_ENGINE_DEFAULT, + I2C_COMMAND_ENGINE_SW, + I2C_COMMAND_ENGINE_HW +}; + +struct i2c_command { + struct i2c_payload *payloads; + uint8_t number_of_payloads; + + enum i2c_command_engine engine; + + /* expressed in KHz + * zero means "use default value" */ + uint32_t speed; +}; + +#define DEFAULT_AUX_MAX_DATA_SIZE 16 +#define AUX_MAX_DEFER_WRITE_RETRY 20 + +struct aux_payload { + /* set following flag to read/write I2C data, + * reset it to read/write DPCD data */ + bool i2c_over_aux; + /* set following flag to write data, + * reset it to read data */ + bool write; + uint32_t address; + uint8_t length; + uint8_t *data; +}; + +struct aux_command { + struct aux_payload *payloads; + uint8_t number_of_payloads; + + /* expressed in milliseconds + * zero means "use default value" */ + uint32_t defer_delay; + + /* zero means "use default value" */ + uint32_t max_defer_write_retry; +}; + +union aux_config { + struct { + uint32_t ALLOW_AUX_WHEN_HPD_LOW:1; + } bits; + uint32_t raw; +}; + +struct i2caux; + +struct i2caux *dal_i2caux_create( + struct adapter_service *as, + struct dc_context *ctx); + +bool dal_i2caux_submit_i2c_command( + struct i2caux *i2caux, + struct ddc *ddc, + struct i2c_command *cmd); + +bool dal_i2caux_submit_aux_command( + struct i2caux *i2caux, + struct ddc *ddc, + struct aux_command *cmd); + +void dal_i2caux_keep_engine_power_up( + struct i2caux *i2caux, + struct ddc *ddc, + bool keep_power_up); + +bool dal_i2caux_start_gtc_sync( + struct i2caux *i2caux, + struct ddc *ddc); + +bool dal_i2caux_stop_gtc_sync( + struct i2caux *i2caux, + struct ddc *ddc); + +void dal_i2caux_configure_aux( + struct i2caux *i2caux, + struct ddc *ddc, + union aux_config cfg); + +void dal_i2caux_destroy( + struct i2caux **ptr); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/irq_interface.h b/drivers/gpu/drm/amd/dal/include/irq_interface.h new file mode 100644 index 000000000000..0faa48fabf95 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/irq_interface.h @@ -0,0 +1,53 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IRQ_INTERFACE_H__ +#define __DAL_IRQ_INTERFACE_H__ + +#include "gpio_types.h" + +struct irq; + +enum gpio_result dal_irq_open( + struct irq *irq); + +enum gpio_result dal_irq_get_value( + const struct irq *irq, + uint32_t *value); + +enum dc_irq_source dal_irq_get_source( + const struct irq *irq); + +enum dc_irq_source dal_irq_get_rx_source( + const struct irq *irq); + +enum gpio_result dal_irq_setup_hpd_filter( + struct irq *irq, + struct gpio_hpd_config *config); + +void dal_irq_close( + struct irq *irq); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/irq_service_interface.h b/drivers/gpu/drm/amd/dal/include/irq_service_interface.h new file mode 100644 index 000000000000..7ae4aebb738d --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/irq_service_interface.h @@ -0,0 +1,55 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IRQ_SERVICE_INTERFACE_H__ +#define __DAL_IRQ_SERVICE_INTERFACE_H__ + +#include "include/adapter_service_types.h" + +struct irq_service_init_data { + struct dc_context *ctx; +}; + +struct irq_service *dal_irq_service_create( + enum dce_version version, + struct irq_service_init_data *init_data); + +void dal_irq_service_destroy(struct irq_service **irq_service); + +bool dal_irq_service_set( + struct irq_service *irq_service, + enum dc_irq_source source, + bool enable); + +bool dal_irq_service_ack( + struct irq_service *irq_service, + enum dc_irq_source source); + +enum dc_irq_source dal_irq_service_to_irq_source( + struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/link_service_interface.h b/drivers/gpu/drm/amd/dal/include/link_service_interface.h new file mode 100644 index 000000000000..2ac93119cc02 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/link_service_interface.h @@ -0,0 +1,202 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_LINK_SERVICE_INTERFACE_H__ +#define __DAL_LINK_SERVICE_INTERFACE_H__ + +#include "include/link_service_types.h" + +/* forward declaration */ +struct link_service; +struct hw_crtc_timing; +struct hw_path_mode; +struct display_path; +struct hw_path_mode_set; +struct link_training_preference; +enum ddc_result; + +struct link_service *dal_link_service_create( + struct link_service_init_data *init_data); + +void dal_link_service_destroy( + struct link_service **ls); + +enum link_service_type dal_ls_get_link_service_type( + struct link_service *link_service); + +bool dal_ls_validate_mode_timing( + struct link_service *ls, + uint32_t display_index, + const struct hw_crtc_timing *timing, + struct link_validation_flags flags); + +bool dal_ls_get_mst_sink_info( + struct link_service *ls, + uint32_t display_index, + struct mst_sink_info *sink_info); + +bool dal_ls_get_gtc_sync_status( + struct link_service *ls); + +bool dal_ls_enable_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_disable_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *poath_mode); + +bool dal_ls_optimized_enable_stream( + struct link_service *ls, + uint32_t display_index, + struct display_path *display_path); + +void dal_ls_update_stream_features( + struct link_service *ls, + const struct hw_path_mode *path_mode); + +bool dal_ls_blank_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_unblank_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_pre_mode_change( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_post_mode_change( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_power_on_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +bool dal_ls_power_off_stream( + struct link_service *ls, + uint32_t display_index, + struct hw_path_mode *path_mode); + +void dal_ls_retrain_link( + struct link_service *ls, + struct hw_path_mode_set *path_set); + +bool dal_ls_get_current_link_setting( + struct link_service *ls, + struct link_settings *link_settings); + +void dal_ls_connect_link( + struct link_service *ls, + const struct display_path *display_path, + bool initial_detection); + +void dal_ls_disconnect_link( + struct link_service *ls); + +bool dal_ls_is_mst_network_present( + struct link_service *ls); + +void dal_ls_invalidate_down_stream_devices( + struct link_service *ls); + +bool dal_ls_are_mst_displays_cofunctional( + struct link_service *ls, + const uint32_t *array_display_index, + uint32_t len); + +bool dal_ls_is_sink_present_at_display_index( + struct link_service *ls, + uint32_t display_index); + +struct ddc_service *dal_ls_obtain_mst_ddc_service( + struct link_service *ls, + uint32_t display_index); + +void dal_ls_release_mst_ddc_service( + struct link_service *ls, + struct ddc_service *ddc_service); + +void dal_ls_release_hw( + struct link_service *ls); + +bool dal_ls_associate_link( + struct link_service *ls, + uint32_t display_index, + uint32_t link_index, + bool is_internal_link); + +bool dal_dpsst_ls_set_overridden_trained_link_settings( + struct link_service *ls, + const struct link_settings *link_settings); + +void dal_dpsst_ls_set_link_training_preference( + struct link_service *ls, + const struct link_training_preference *ltp); + +struct link_training_preference + dal_dpsst_ls_get_link_training_preference( + struct link_service *ls); + +bool dal_ls_should_send_notification( + struct link_service *ls); + +uint32_t dal_ls_get_notification_display_index( + struct link_service *ls); + +enum ddc_result dal_dpsst_ls_read_dpcd_data( + struct link_service *ls, + uint32_t address, + uint8_t *data, + uint32_t size); + +enum ddc_result dal_dpsst_ls_write_dpcd_data( + struct link_service *ls, + uint32_t address, + const uint8_t *data, + uint32_t size); + +bool dal_ls_is_link_psr_supported(struct link_service *ls); + +bool dal_ls_is_stream_drr_supported(struct link_service *ls); + +void dal_ls_set_link_psr_capabilities( + struct link_service *ls, + struct psr_caps *psr_caps); + +void dal_ls_get_link_psr_capabilities( + struct link_service *ls, + struct psr_caps *psr_caps); + +#endif /* __DAL_LINK_SERVICE_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h new file mode 100644 index 000000000000..d2e6256695fb --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h @@ -0,0 +1,427 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_LINK_SERVICE_TYPES_H__ +#define __DAL_LINK_SERVICE_TYPES_H__ + +#include "grph_object_id.h" +#include "dpcd_defs.h" +#include "dal_types.h" +#include "irq_types.h" + +/*struct mst_mgr_callback_object;*/ +struct ddc; +struct irq_manager; + +enum { + MAX_CONTROLLER_NUM = 6 +}; + +enum link_service_type { + LINK_SERVICE_TYPE_LEGACY = 0, + LINK_SERVICE_TYPE_DP_SST, + LINK_SERVICE_TYPE_DP_MST, + LINK_SERVICE_TYPE_MAX +}; + +struct link_validation_flags { + uint32_t DYNAMIC_VALIDATION:1; + uint32_t CANDIDATE_TIMING:1; + uint32_t START_OF_VALIDATION:1; +}; + +/* Post Cursor 2 is optional for transmitter + * and it applies only to the main link operating at HBR2 + */ +enum post_cursor2 { + POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ + POST_CURSOR2_LEVEL1, + POST_CURSOR2_LEVEL2, + POST_CURSOR2_LEVEL3, + POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, +}; + +enum voltage_swing { + VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ + VOLTAGE_SWING_LEVEL1, + VOLTAGE_SWING_LEVEL2, + VOLTAGE_SWING_LEVEL3, + VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 +}; + +enum pre_emphasis { + PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ + PRE_EMPHASIS_LEVEL1, + PRE_EMPHASIS_LEVEL2, + PRE_EMPHASIS_LEVEL3, + PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 +}; + +enum dpcd_value_mask { + DPCD_VALUE_MASK_MAX_LANE_COUNT_LANE_COUNT = 0x1F, + DPCD_VALUE_MASK_MAX_LANE_COUNT_TPS3_SUPPORTED = 0x40, + DPCD_VALUE_MASK_MAX_LANE_COUNT_ENHANCED_FRAME_EN = 0x80, + DPCD_VALUE_MASK_MAX_DOWNSPREAD = 0x01, + DPCD_VALUE_MASK_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE = 0x01 +}; + +enum dp_power_state { + DP_POWER_STATE_D0 = 1, + DP_POWER_STATE_D3 +}; + +enum dpcd_downstream_port_types { + DPCD_DOWNSTREAM_DP, + DPCD_DOWNSTREAM_VGA, + DPCD_DOWNSTREAM_DVI_HDMI, + /* has no EDID (TV, CV) */ + DPCD_DOWNSTREAM_NON_DDC +}; + +enum edp_revision { + /* eDP version 1.1 or lower */ + EDP_REVISION_11 = 0x00, + /* eDP version 1.2 */ + EDP_REVISION_12 = 0x01, + /* eDP version 1.3 */ + EDP_REVISION_13 = 0x02 +}; + +enum lane_count { + LANE_COUNT_UNKNOWN = 0, + LANE_COUNT_ONE = 1, + LANE_COUNT_TWO = 2, + LANE_COUNT_FOUR = 4, + LANE_COUNT_EIGHT = 8, + LANE_COUNT_DP_MAX = LANE_COUNT_FOUR +}; + +/* This is actually a reference clock (27MHz) multiplier + * 162MBps bandwidth for 1.62GHz like rate, + * 270MBps for 2.70GHz, + * 324MBps for 3.24Ghz, + * 540MBps for 5.40GHz + */ +enum link_rate { + LINK_RATE_UNKNOWN = 0, + LINK_RATE_LOW = 0x06, + LINK_RATE_HIGH = 0x0A, + LINK_RATE_RBR2 = 0x0C, + LINK_RATE_HIGH2 = 0x14 +}; + +enum { + LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/ +}; + +enum link_spread { + LINK_SPREAD_DISABLED = 0x00, + /* 0.5 % downspread 30 kHz */ + LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, + /* 0.5 % downspread 33 kHz */ + LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 +}; + +/* DPCD_ADDR_DOWNSTREAM_PORT_PRESENT register value */ +union dpcd_downstream_port { + struct { +#if defined(LITTLEENDIAN_CPU) + uint8_t PRESENT:1; + uint8_t TYPE:2; + uint8_t FORMAT_CONV:1; + uint8_t RESERVED:4; +#elif defined(BIGENDIAN_CPU) + uint8_t RESERVED:4; + uint8_t FORMAT_CONV:1; + uint8_t TYPE:2; + uint8_t PRESENT:1; +#else + #error ARCH not defined! +#endif + } bits; + + uint8_t raw; +}; + +/* DPCD_ADDR_SINK_COUNT register value */ +union dpcd_sink_count { + struct { +#if defined(LITTLEENDIAN_CPU) + uint8_t SINK_COUNT:6; + uint8_t CP_READY:1; + uint8_t RESERVED:1; +#elif defined(BIGENDIAN_CPU) + uint8_t RESERVED:1; + uint8_t CP_READY:1; + uint8_t SINK_COUNT:6; +#else + #error ARCH not defined! +#endif + } bits; + + uint8_t raw; +}; + +struct link_settings { + enum lane_count lane_count; + enum link_rate link_rate; + enum link_spread link_spread; +}; + +struct lane_settings { + enum voltage_swing VOLTAGE_SWING; + enum pre_emphasis PRE_EMPHASIS; + enum post_cursor2 POST_CURSOR2; +}; + +struct link_training_settings { + struct link_settings link_settings; + struct lane_settings lane_settings[LANE_COUNT_DP_MAX]; + bool allow_invalid_msa_timing_param; +}; + +enum hw_dp_training_pattern { + HW_DP_TRAINING_PATTERN_1 = 0, + HW_DP_TRAINING_PATTERN_2, + HW_DP_TRAINING_PATTERN_3 +}; + +/*TODO: Move this enum test harness*/ +/* Test patterns*/ +enum dp_test_pattern { + /* Input data is pass through Scrambler + * and 8b10b Encoder straight to output*/ + DP_TEST_PATTERN_VIDEO_MODE = 0, + /* phy test patterns*/ + DP_TEST_PATTERN_D102, + DP_TEST_PATTERN_SYMBOL_ERROR, + DP_TEST_PATTERN_PRBS7, + + DP_TEST_PATTERN_80BIT_CUSTOM, + DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE, + + /* Link Training Patterns */ + DP_TEST_PATTERN_TRAINING_PATTERN1, + DP_TEST_PATTERN_TRAINING_PATTERN2, + DP_TEST_PATTERN_TRAINING_PATTERN3, + + /* link test patterns*/ + DP_TEST_PATTERN_COLOR_SQUARES, + DP_TEST_PATTERN_COLOR_SQUARES_CEA, + DP_TEST_PATTERN_VERTICAL_BARS, + DP_TEST_PATTERN_HORIZONTAL_BARS, + DP_TEST_PATTERN_COLOR_RAMP, + + /* audio test patterns*/ + DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED, + DP_TEST_PATTERN_AUDIO_SAWTOOTH, + + DP_TEST_PATTERN_UNSUPPORTED +}; + +enum dp_panel_mode { + /* not required */ + DP_PANEL_MODE_DEFAULT, + /* standard mode for eDP */ + DP_PANEL_MODE_EDP, + /* external chips specific settings */ + DP_PANEL_MODE_SPECIAL +}; + +/** + * @brief LinkServiceInitOptions to set certain bits + */ +struct link_service_init_options { + uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1; +}; + +/** + * @brief data required to initialize LinkService + */ +struct link_service_init_data { + /* number of displays indices which the MST Mgr would manange*/ + uint32_t num_of_displays; + enum link_service_type link_type; + /*struct mst_mgr_callback_object*topology_change_callback;*/ + /* native aux access */ + struct ddc_service *dpcd_access_srv; + /* for calling HWSS to program HW */ + struct hw_sequencer *hwss; + /* the source which to register IRQ on */ + enum dc_irq_source irq_src_hpd_rx; + enum dc_irq_source irq_src_dp_sink; + /* other init options such as SW Workarounds */ + struct link_service_init_options init_options; + uint32_t connector_enum_id; + struct graphics_object_id connector_id; + struct adapter_service *adapter_service; + struct dc_context *ctx; + struct topology_mgr *tm; +}; + +/** + * @brief LinkServiceInitOptions to set certain bits + */ +struct LinkServiceInitOptions { + uint32_t APPLY_MISALIGNMENT_BUG_WORKAROUND:1; +}; + +/* DPCD_ADDR_TRAINING_LANEx_SET registers value */ +union dpcd_training_lane_set { + struct { +#if defined(LITTLEENDIAN_CPU) + uint8_t VOLTAGE_SWING_SET:2; + uint8_t MAX_SWING_REACHED:1; + uint8_t PRE_EMPHASIS_SET:2; + uint8_t MAX_PRE_EMPHASIS_REACHED:1; + /* following is reserved in DP 1.1 */ + uint8_t POST_CURSOR2_SET:2; +#elif defined(BIGENDIAN_CPU) + uint8_t POST_CURSOR2_SET:2; + uint8_t MAX_PRE_EMPHASIS_REACHED:1; + uint8_t PRE_EMPHASIS_SET:2; + uint8_t MAX_SWING_REACHED:1; + uint8_t VOLTAGE_SWING_SET:2; +#else + #error ARCH not defined! +#endif + } bits; + + uint8_t raw; +}; + +/* DPCD_ADDR_TRAINING_LANEx_SET2 registers value - since DP 1.2 */ +union dpcd_training_lanes_set2 { + struct { +#if defined(LITTLEENDIAN_CPU) + uint8_t LANE0_POST_CURSOR2_SET:2; + uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1; + uint8_t LANE0_RESERVED:1; + uint8_t LANE1_POST_CURSOR2_SET:2; + uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1; + uint8_t LANE1_RESERVED:1; +#elif defined(BIGENDIAN_CPU) + uint8_t LANE1_RESERVED:1; + uint8_t LANE1_MAX_POST_CURSOR2_REACHED:1; + uint8_t LANE1_POST_CURSOR2_SET:2; + uint8_t LANE0_RESERVED:1; + uint8_t LANE0_MAX_POST_CURSOR2_REACHED:1; + uint8_t LANE0_POST_CURSOR2_SET:2; +#else + #error ARCH not defined! +#endif + } bits; + + uint8_t raw; +}; + +/** + * @brief represent the 16 byte + * global unique identifier + */ +struct mst_guid { + uint8_t ids[16]; +}; + +/** + * @brief represents the relative address used + * to identify a node in MST topology network + */ +struct mst_rad { + /* number of links. rad[0] up to + * rad [linkCount - 1] are valid. */ + uint32_t rad_link_count; + /* relative address. rad[0] is the + * first device connected to the source. */ + uint8_t rad[15]; + /* extra 10 bytes for underscores; for e.g.:2_1_8*/ + int8_t rad_str[25]; +}; + +/** + * @brief this structure is used to report + * properties associated to a sink device + */ +struct mst_sink_info { + /* global unique identifier */ + struct mst_guid guid; + /* relative address */ + struct mst_rad rad; + /* total bandwidth available on the DP connector */ + uint32_t total_available_bandwidth_in_mbps; + /* bandwidth allocated to the sink device. */ + uint32_t allocated_bandwidth_in_mbps; + /* bandwidth consumed to support for the current mode. */ + uint32_t consumed_bandwidth_in_mbps; +}; + +/** + * @brief represent device information in MST topology + */ +struct mst_device_info { + /* global unique identifier*/ + struct mst_guid guid; + /* relative address*/ + struct mst_rad rad; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct dp_mst_stream_allocation { + uint8_t vcp_id; + /* number of slots required for the DP stream in + * transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct dp_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; +}; + +struct dp_test_event_data { + /*size of parameters (starting from params) in bytes*/ + uint32_t size; + /*parameters block*/ + uint32_t params[1]; +}; + +struct psr_caps { + /* These parameters are from PSR capabilities reported by Sink DPCD. */ + uint8_t psr_version; + uint32_t psr_rfb_setup_time; + bool psr_exit_link_training_req; + + /* These parameters are calculated in Driver, based on display timing + * and Sink capabilities. + * If VBLANK region is too small and Sink takes a long time to power up + * Remote Frame Buffer, it may take an extra frame to enter PSR */ + bool psr_frame_capture_indication_req; + uint32_t psr_sdp_transmit_line_num_deadline; +}; + +#endif /*__DAL_LINK_SERVICE_TYPES_H__*/ diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h new file mode 100644 index 000000000000..4d945eabb07f --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h @@ -0,0 +1,153 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_LOGGER_INTERFACE_H__ +#define __DAL_LOGGER_INTERFACE_H__ + +#include "logger_types.h" + +struct dal_logger; +struct dc_context; +union logger_flags; + +/* + * TODO: This logger functionality needs to be implemented and reworked. + */ + + +/* + * + * DAL logger functionality + * + */ + +struct dal_logger *dal_logger_create(struct dc_context *ctx); + +uint32_t dal_logger_destroy(struct dal_logger **logger); + +uint32_t dal_logger_get_mask( + struct dal_logger *logger, + enum log_major lvl_major, enum log_minor lvl_minor); + +uint32_t dal_logger_set_mask( + struct dal_logger *logger, + enum log_major lvl_major, enum log_minor lvl_minor); + +uint32_t dal_logger_get_masks( + struct dal_logger *logger, + enum log_major lvl_major); + +void dal_logger_set_masks( + struct dal_logger *logger, + enum log_major lvl_major, uint32_t log_mask); + +uint32_t dal_logger_unset_mask( + struct dal_logger *logger, + enum log_major lvl_major, enum log_minor lvl_minor); + +bool dal_logger_should_log( + struct dal_logger *logger, + enum log_major major, + enum log_minor minor); + +uint32_t dal_logger_get_flags( + struct dal_logger *logger); + +void dal_logger_set_flags( + struct dal_logger *logger, + union logger_flags flags); + +void dal_logger_write( + struct dal_logger *logger, + enum log_major major, + enum log_minor minor, + const char *msg, + ...); + +void dal_logger_append( + struct log_entry *entry, + const char *msg, + ...); + +uint32_t dal_logger_read( + struct dal_logger *logger, + uint32_t output_buffer_size, + char *output_buffer, + uint32_t *bytes_read, + bool single_line); + +void dal_logger_open( + struct dal_logger *logger, + struct log_entry *entry, + enum log_major major, + enum log_minor minor); + +void dal_logger_close(struct log_entry *entry); + +uint32_t dal_logger_get_buffer_size(struct dal_logger *logger); + +uint32_t dal_logger_set_buffer_size( + struct dal_logger *logger, + uint32_t new_size); + +const struct log_major_info *dal_logger_enum_log_major_info( + struct dal_logger *logger, + unsigned int enum_index); + +const struct log_minor_info *dal_logger_enum_log_minor_info( + struct dal_logger *logger, + enum log_major major, + unsigned int enum_index); + +/* Any function which is empty or have incomplete implementation should be + * marked by this macro. + * Note that the message will be printed exactly once for every function + * it is used in order to avoid repeating of the same message. */ +#define DAL_LOGGER_NOT_IMPL(log_minor, fmt, ...) \ +{ \ + static bool print_not_impl = true; \ +\ + if (print_not_impl == true) { \ + print_not_impl = false; \ + dal_logger_write(ctx->logger, LOG_MAJOR_WARNING, \ + log_minor, "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \ + } \ +} + +/****************************************************************************** + * Convenience macros to save on typing. + *****************************************************************************/ + +#define DC_ERROR(...) \ + dal_logger_write(dc_ctx->logger, \ + LOG_MAJOR_ERROR, LOG_MINOR_COMPONENT_DC, \ + __VA_ARGS__); + +#define DC_SYNC_INFO(...) \ + dal_logger_write(dc_ctx->logger, \ + LOG_MAJOR_SYNC, LOG_MINOR_SYNC_TIMING, \ + __VA_ARGS__); + +#endif /* __DAL_LOGGER_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h new file mode 100644 index 000000000000..614799907e19 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/logger_types.h @@ -0,0 +1,356 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_LOGGER_TYPES_H__ +#define __DAL_LOGGER_TYPES_H__ + + +/* + * TODO: This logger functionality needs to be implemented and reworked. + */ + + +struct dal_logger; + +enum log_major { +/*00*/ + LOG_MAJOR_ERROR = 0, /*< DAL subcomponent error MSG*/ +/*01*/ LOG_MAJOR_WARNING, /*< DAL subcomponent warning MSG*/ +/*02*/ LOG_MAJOR_INTERFACE_TRACE,/*< DAL subcomponent interface tracing*/ +/*03*/ LOG_MAJOR_HW_TRACE, /*< Log ASIC register read/write, + * ATOMBIOS exec table call and delays*/ + +/*04*/ LOG_MAJOR_MST, /*< related to multi-stream*/ +/*05*/ LOG_MAJOR_DCS, /*< related to Dcs*/ +/*06*/ LOG_MAJOR_DCP, /*< related to Dcp grph and ovl,gamam and csc*/ +/*07*/ LOG_MAJOR_BIOS, /*< related to BiosParser*/ +/*08*/ LOG_MAJOR_REGISTER, /*< register access*/ +/*09*/ LOG_MAJOR_INFO_PACKETS, /*< info packets*/ +/*10*/ LOG_MAJOR_DSAT, /*< related + * to Display System Analysis Tool*/ +/*11*/ LOG_MAJOR_EC, /*< External Components - MCIL Events/queries, + * PPLib notifications/queries*/ +/*12*/ LOG_MAJOR_BWM, /*< related to Bandwidth Manager*/ +/*13*/ LOG_MAJOR_MODE_ENUM, /*< related to mode enumeration*/ +/*14*/ LOG_MAJOR_I2C_AUX, /*< i2c and aux channel log*/ +/*15*/ LOG_MAJOR_LINE_BUFFER, /*< Line Buffer object logging activity*/ +/*16*/ LOG_MAJOR_HWSS, /*< HWSS object logging activity*/ +/*17*/ LOG_MAJOR_OPTIMIZATION, /*< Optimization code path*/ +/*18*/ LOG_MAJOR_PERF_MEASURE, /*< Performance measurement dumps*/ +/*19*/ LOG_MAJOR_SYNC, /*< related to HW and SW Synchronization*/ +/*20*/ LOG_MAJOR_BACKLIGHT, /*< related to backlight */ +/*21*/ LOG_MAJOR_INTERRUPTS, /*< logging for all interrupts */ + +/*22*/ LOG_MAJOR_TM, /*< related to Topology Manager*/ +/*23*/ LOG_MAJOR_DISPLAY_SERVICE, /*< related to Display Service*/ +/*24*/ LOG_MAJOR_FEATURE_OVERRIDE, /*< related to features*/ +/*25*/ LOG_MAJOR_DETECTION, /*< related to detection*/ + LOG_MAJOR_COUNT, /*< count of the Major categories*/ +}; + +/** +* @brief defines minor switch for logging. each of these define sub category +* of log message per LogMajor +*/ + + +enum log_minor { + + /* Special case for 'all' checkbox */ + LOG_MINOR_MASK_ALL = (uint32_t)-1, /* 0xFFFFFFFF */ +/** +* @brief defines minor category for +* LOG_MAJOR_ERROR, +* LOG_MAJOR_WARNING, +* LOG_MAJOR_INTERFACE_TRACE +* +* @note each DAL subcomponent should have a corresponding enum +*/ + LOG_MINOR_COMPONENT_LINK_SERVICE = 0, + LOG_MINOR_COMPONENT_DAL_INTERFACE, + LOG_MINOR_COMPONENT_HWSS, + LOG_MINOR_COMPONENT_ADAPTER_SERVICE, + LOG_MINOR_COMPONENT_DISPLAY_SERVICE, + LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER, + LOG_MINOR_COMPONENT_ENCODER, + LOG_MINOR_COMPONENT_I2C_AUX, + LOG_MINOR_COMPONENT_AUDIO, + LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE, + LOG_MINOR_COMPONENT_DMCU, + LOG_MINOR_COMPONENT_GPU, + LOG_MINOR_COMPONENT_CONTROLLER, + LOG_MINOR_COMPONENT_ISR, + LOG_MINOR_COMPONENT_BIOS, + LOG_MINOR_COMPONENT_DC, + LOG_MINOR_COMPONENT_IRQ_SERVICE, + +/** +* @brief define minor category for LogMajor_HardwareTrace +* +* @note defines functionality based HW programming trace +*/ + LOG_MINOR_HW_TRACE_MST = 0, + LOG_MINOR_HW_TRACE_TRAVIS, + LOG_MINOR_HW_TRACE_HOTPLUG, + LOG_MINOR_HW_TRACE_LINK_TRAINING, + LOG_MINOR_HW_TRACE_SET_MODE, + LOG_MINOR_HW_TRACE_RESUME_S3, + LOG_MINOR_HW_TRACE_RESUME_S4, + LOG_MINOR_HW_TRACE_BOOTUP, + LOG_MINOR_HW_TRACE_AUDIO, + LOG_MINOR_HW_TRACE_HPD_IRQ, + LOG_MINOR_HW_TRACE_INTERRUPT, + LOG_MINOR_HW_TRACE_MPO, + +/** +* @brief defines minor category for LogMajor_Mst +* +* @note define sub functionality related to MST +*/ + LOG_MINOR_MST_IRQ_HPD_RX = 0, + LOG_MINOR_MST_IRQ_TIMER, + LOG_MINOR_MST_NATIVE_AUX, + LOG_MINOR_MST_SIDEBAND_MSG, + LOG_MINOR_MST_MSG_TRANSACTION, + LOG_MINOR_MST_SIDEBAND_MSG_PARSED, + LOG_MINOR_MST_MSG_TRANSACTION_PARSED, + LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS, + LOG_MINOR_MST_PROGRAMMING, + LOG_MINOR_MST_TOPOLOGY_DISCOVERY, + LOG_MINOR_MST_CONVERTER_CAPS, + +/** +* @brief defines minor category for LogMajor_DCS +* +* @note should define sub functionality related to Dcs +*/ + LOG_MINOR_DCS_EDID_EMULATOR = 0, + LOG_MINOR_DCS_DONGLE_DETECTION, + +/** +* @brief defines minor category for DCP +* +* @note should define sub functionality related to Dcp +*/ + LOG_MINOR_DCP_GAMMA_GRPH = 0, + LOG_MINOR_DCP_GAMMA_OVL, + LOG_MINOR_DCP_CSC_GRPH, + LOG_MINOR_DCP_CSC_OVL, + LOG_MINOR_DCP_SCALER, + LOG_MINOR_DCP_SCALER_TABLES, +/** +* @brief defines minor category for LogMajor_Bios +* +* @note define sub functionality related to BiosParser +*/ + LOG_MINOR_BIOS_CMD_TABLE = 0, +/** +* @brief defines minor category for LogMajor_Bios +* +* @note define sub functionality related to BiosParser +*/ + LOG_MINOR_REGISTER_INDEX = 0, +/** +* @brief defines minor category for info packets +* +*/ + LOG_MINOR_INFO_PACKETS_HDMI = 0, + +/** +* @brief defines minor category for LOG_MAJOR_DSAT +* +* @note define sub functionality related to Display System Analysis Tool +*/ + LOG_MINOR_DSAT_LOGGER = 0, + LOG_MINOR_DSAT_GET_EDID, + LOG_MINOR_DSAT_EDID_OVERRIDE, + LOG_MINOR_DSAT_SET_ADJUSTMENTS, + LOG_MINOR_DSAT_GET_ADJUSTMENTS, + +/** +* @brief defines minor category for LOG_MAJOR_EC +* +* @note define sub functionality related to External components notifications +*/ + LOG_MINOR_EC_PPLIB_NOTIFY = 0, + LOG_MINOR_EC_PPLIB_QUERY, + +/** +* @brief defines minor category for LOG_MAJOR_BWM +* +* @note define sub functionality related to Bandwidth Manager +*/ + LOG_MINOR_BWM_MODE_VALIDATION = 0, + LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS, + +/** +* @brief define minor category for LogMajor_ModeEnum +* +* @note defines functionality mode enumeration trace +*/ + LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES = 0, + LOG_MINOR_MODE_ENUM_VIEW_SOLUTION, + LOG_MINOR_MODE_ENUM_TS_LIST_BUILD, + LOG_MINOR_MODE_ENUM_TS_LIST, + LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST, + LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE, + +/** +* @brief defines minor category for LogMajor_I2C_AUX +* +* @note define sub functionality related to I2c and Aux Channel Log +*/ + LOG_MINOR_I2C_AUX_LOG = 0, + LOG_MINOR_I2C_AUX_AUX_TIMESTAMP, + LOG_MINOR_I2C_AUX_CFG, + +/** +* @brief defines minor category for LogMajor_LineBuffer +* +* @note define sub functionality related to LineBuffer +*/ + LOG_MINOR_LINE_BUFFER_POWERGATING = 0, + +/** +* @brief defines minor category for LogMajor_HWSS +* +* @note define sub functionality related to HWSS +*/ + LOG_MINOR_HWSS_TAPS_VALIDATION = 0, + +/** +* @brief defines minor category for LogMajor_Optimization +* +* @note define sub functionality related to Optimization +*/ + LOG_MINOR_OPTMZ_GENERAL = 0, + LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE, + +/** +* @brief defines minor category for LogMajor_PerfMeasure +* +* @note define sub functionality related to Performance measurement dumps +*/ + LOG_MINOR_PERF_MEASURE_GENERAL = 0, + LOG_MINOR_PERF_MEASURE_HEAP_MEMORY, + +/** +* @brief defines minor category for LogMajor_Sync +* +* @note define sub functionality related to HW and SW Synchronization +*/ + LOG_MINOR_SYNC_HW_CLOCK_ADJUST = 0, + LOG_MINOR_SYNC_TIMING, + +/** +* @brief defines minor category for LogMajor_Backlight +* +* @note define sub functionality related to backlight (including VariBright) +*/ + LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS = 0, + LOG_MINOR_BACKLIGHT_DMCU_DELTALUT, + LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT, + LOG_MINOR_BACKLIGHT_INTERFACE, + LOG_MINOR_BACKLIGHT_LID, + +/** +* @brief defines minor category for LOG_MAJOR_TM +* +* @note define sub functionality related to Topology Manager +*/ + LOG_MINOR_TM_INFO = 0, + LOG_MINOR_TM_IFACE_TRACE, + LOG_MINOR_TM_RESOURCES, + LOG_MINOR_TM_ENCODER_CTL, + LOG_MINOR_TM_ENG_ASN, + LOG_MINOR_TM_CONTROLLER_ASN, + LOG_MINOR_TM_PWR_GATING, + LOG_MINOR_TM_BUILD_DSP_PATH, + LOG_MINOR_TM_DISPLAY_DETECT, + LOG_MINOR_TM_LINK_SRV, + LOG_MINOR_TM_NOT_IMPLEMENTED, + LOG_MINOR_TM_COFUNC_PATH, + +/** +* @brief defines minor category for LOG_MAJOR_DISPLAY_SERVICE +* +* @note define sub functionality related to Display Service +*/ + LOG_MINOR_DS_MODE_SETTING = 0, + +/** +* @brief defines minor category for LOG_MAJOR_FEATURE_OVERRIDE +* +* @note define sub functionality related to features in adapter service +*/ + LOG_MINOR_FEATURE_OVERRIDE = 0, + +/** +* @brief defines minor category for LOG_MAJOR_DETECTION +* +* @note define sub functionality related to detection +*/ + LOG_MINOR_DETECTION_EDID_PARSER = 0, + LOG_MINOR_DETECTION_DP_CAPS, +}; + +union logger_flags { + struct { + uint32_t ENABLE_CONSOLE:1; /* Print to console */ + uint32_t ENABLE_BUFFER:1; /* Print to buffer */ + uint32_t RESERVED:30; + } bits; + uint32_t value; +}; + +struct log_entry { + + struct dal_logger *logger; + enum log_major major; + enum log_minor minor; + + char *buf; + uint32_t buf_offset; + uint32_t max_buf_bytes; +}; + +/** +* Structure for enumerating LogMajors and LogMinors +*/ + +#define MAX_MAJOR_NAME_LEN 32 +#define MAX_MINOR_NAME_LEN 32 + +struct log_major_info { + enum log_major major; + char major_name[MAX_MAJOR_NAME_LEN]; +}; + +struct log_minor_info { + enum log_minor minor; + char minor_name[MAX_MINOR_NAME_LEN]; +}; + +#endif /* __DAL_LOGGER_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/scaler_types.h b/drivers/gpu/drm/amd/dal/include/scaler_types.h new file mode 100644 index 000000000000..db52dbc72383 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/scaler_types.h @@ -0,0 +1,196 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_SCALER_TYPES_H__ +#define __DAL_SCALER_TYPES_H__ + +#include "signal_types.h" +#include "fixed31_32.h" +#include "dc_types.h" + +enum pixel_type { + PIXEL_TYPE_30BPP = 1, + PIXEL_TYPE_20BPP +}; + +/*overscan or window*/ +struct overscan_info { + uint32_t left; + uint32_t right; + uint32_t top; + uint32_t bottom; +}; + +struct mp_scaling_data { + struct rect viewport; + struct view dst_res; + struct overscan_info overscan; + struct scaling_taps taps; + struct scaling_ratios ratios; +}; + +struct scaler_validation_params { + uint32_t INTERLACED:1; + uint32_t CHROMA_SUB_SAMPLING:1; + + uint32_t line_buffer_size; + uint32_t display_clock; /* in KHz */ + uint32_t actual_pixel_clock; /* in KHz */ + struct view source_view; + struct view dest_view; + enum signal_type signal_type; + + struct scaling_taps taps_requested; + enum pixel_format pixel_format; + enum dc_rotation_angle rotation; +}; + +struct adjustment_factor { + int32_t adjust; /* Actual adjustment value * lDivider */ + uint32_t divider; +}; + +struct sharpness_adjustment { + int32_t sharpness; + bool enable_sharpening; +}; + +enum scaling_options { + SCALING_BYPASS = 0, + SCALING_ENABLE +}; + +/* same as Hw register */ +enum filter_type { + FILTER_TYPE_V_LOW_PASS = 0x0, + FILTER_TYPE_V_HIGH_PASS = 0x1, + FILTER_TYPE_H_LUMA = 0x2, + FILTER_TYPE_H_CHROMA = 0x3 +}; + +/* Validation Result enumeration */ +enum scaler_validation_code { + SCALER_VALIDATION_OK = 0, + SCALER_VALIDATION_INVALID_INPUT_PARAMETERS, + SCALER_VALIDATION_SCALING_RATIO_NOT_SUPPORTED, + SCALER_VALIDATION_SOURCE_VIEW_WIDTH_EXCEEDING_LIMIT, + SCALER_VALIDATION_DISPLAY_CLOCK_BELOW_PIXEL_CLOCK, + SCALER_VALIDATION_FAILURE_PREDEFINED_TAPS_NUMBER +}; + + +#define FILTER_TYPE_MASK 0x0000000FL +#define TWO_TAPS 2 + +struct init_int_and_frac { + uint32_t integer; + uint32_t fraction; +}; + +struct scl_ratios_inits { + uint32_t bottom_enable; + uint32_t h_int_scale_ratio; + uint32_t v_int_scale_ratio; + struct init_int_and_frac h_init; + struct init_int_and_frac v_init; + struct init_int_and_frac v_init_bottom; +}; + +union scaler_flags { + uint32_t raw; + struct { + uint32_t INTERLACED:1; + uint32_t DOUBLE_SCAN_MODE:1; + /* this one is legacy flag only used in DCE80 */ + uint32_t RGB_COLOR_SPACE:1; + uint32_t PIPE_LOCK_REQ:1; + /* 4 */ + uint32_t WIDE_DISPLAY:1; + uint32_t OTHER_PIPE:1; + uint32_t SHOULD_PROGRAM_VIEWPORT:1; + uint32_t SHOULD_UNLOCK:1; + /* 8 */ + uint32_t SHOULD_PROGRAM_ALPHA:1; + uint32_t SHOW_COLOURED_BORDER:1; + + uint32_t RESERVED:22; + } bits; +}; + +struct scaler_data { + struct view src_res; + struct view dst_res; + struct overscan_info overscan; + struct scaling_taps taps; + struct adjustment_factor scale_ratio_hp_factor; + struct adjustment_factor scale_ratio_lp_factor; + enum pixel_type pixel_type; /*legacy*/ + struct sharpness_adjustment sharp_gain; + + union scaler_flags flags; + int32_t h_sharpness; + int32_t v_sharpness; + + struct view src_res_wide_display; + struct view dst_res_wide_display; + + /* it is here because of the HW bug in NI (UBTS #269539) + causes glitches in this VBI signal. It shouldn't change after + initialization, kind of a const */ + const struct hw_crtc_timing *hw_crtc_timing; + + struct rect viewport; + + enum pixel_format dal_pixel_format;/*plane concept*/ + /*stereoformat TODO*/ + /*hwtotation TODO*/ + + const struct scaling_ratios *ratios; +}; + +enum bypass_type { + /* 00 - 00 - Manual Centering, Manual Replication */ + BYPASS_TYPE_MANUAL = 0, + /* 01 - 01 - Auto-Centering, No Replication */ + BYPASS_TYPE_AUTO_CENTER = 1, + /* 02 - 10 - Auto-Centering, Auto-Replication */ + BYPASS_TYPE_AUTO_REPLICATION = 3 +}; + +struct replication_factor { + uint32_t h_manual; + uint32_t v_manual; +}; + +enum ram_filter_type { + FILTER_TYPE_RGB_Y_VERTICAL = 0, /* 0 - RGB/Y Vertical filter */ + FILTER_TYPE_CBCR_VERTICAL = 1, /* 1 - CbCr Vertical filter */ + FILTER_TYPE_RGB_Y_HORIZONTAL = 2, /* 1 - RGB/Y Horizontal filter */ + FILTER_TYPE_CBCR_HORIZONTAL = 3, /* 3 - CbCr Horizontal filter */ + FILTER_TYPE_ALPHA_VERTICAL = 4, /* 4 - Alpha Vertical filter. */ + FILTER_TYPE_ALPHA_HORIZONTAL = 5, /* 5 - Alpha Horizontal filter. */ +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/set_mode_types.h b/drivers/gpu/drm/amd/dal/include/set_mode_types.h new file mode 100644 index 000000000000..97160fe7484c --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/set_mode_types.h @@ -0,0 +1,142 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_SET_MODE_TYPES_H__ +#define __DAL_SET_MODE_TYPES_H__ + +#include "dc_types.h" + + +/* GTC group number */ +enum gtc_group { + GTC_GROUP_DISABLED, + GTC_GROUP_1, + GTC_GROUP_2, + GTC_GROUP_3, + GTC_GROUP_4, + GTC_GROUP_5, + GTC_GROUP_6, + GTC_GROUP_MAX +}; + +/* Info frame packet status */ +enum info_frame_flag { + INFO_PACKET_PACKET_INVALID = 0, + INFO_PACKET_PACKET_VALID = 1, + INFO_PACKET_PACKET_RESET = 2, + INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8 +}; + +/* Info frame types */ +enum info_frame_type { + INFO_FRAME_GAMUT = 0x0A, + INFO_FRAME_VENDOR_INFO = 0x81, + INFO_FRAME_AVI = 0x82 +}; + +/* Info frame versions */ +enum info_frame_version { + INFO_FRAME_VERSION_1 = 1, + INFO_FRAME_VERSION_2 = 2, + INFO_FRAME_VERSION_3 = 3 +}; + +/* Info frame size */ +enum info_frame_size { + INFO_FRAME_SIZE_AVI = 13, + INFO_FRAME_SIZE_VENDOR = 25, + INFO_FRAME_SIZE_AUDIO = 10 +}; + +struct hdmi_info_frame_header { + uint8_t info_frame_type; + uint8_t version; + uint8_t length; +}; + +#pragma pack(push) +#pragma pack(1) + +struct info_packet_raw_data { + uint8_t hb0; + uint8_t hb1; + uint8_t hb2; + uint8_t sb[28]; /* sb0~sb27 */ +}; + +union hdmi_info_packet { + struct avi_info_frame { + struct hdmi_info_frame_header header; + + uint8_t CHECK_SUM:8; + + uint8_t S0_S1:2; + uint8_t B0_B1:2; + uint8_t A0:1; + uint8_t Y0_Y1_Y2:3; + + uint8_t R0_R3:4; + uint8_t M0_M1:2; + uint8_t C0_C1:2; + + uint8_t SC0_SC1:2; + uint8_t Q0_Q1:2; + uint8_t EC0_EC2:3; + uint8_t ITC:1; + + uint8_t VIC0_VIC7:8; + + uint8_t PR0_PR3:4; + uint8_t CN0_CN1:2; + uint8_t YQ0_YQ1:2; + + uint16_t bar_top; + uint16_t bar_bottom; + uint16_t bar_left; + uint16_t bar_right; + + uint8_t reserved[14]; + } bits; + + struct info_packet_raw_data packet_raw_data; +}; + +struct info_packet { + enum info_frame_flag flags; + union hdmi_info_packet info_packet_hdmi; +}; + +struct info_frame { + struct info_packet avi_info_packet; + struct info_packet gamut_packet; + struct info_packet vendor_info_packet; + struct info_packet spd_info_packet; +}; + + + +#pragma pack(pop) + +#endif /* __DAL_SET_MODE_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h new file mode 100644 index 000000000000..a50f7ed74a33 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/signal_types.h @@ -0,0 +1,59 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_SIGNAL_TYPES_H__ +#define __DC_SIGNAL_TYPES_H__ + +enum signal_type { + SIGNAL_TYPE_NONE = 0L, /* no signal */ + SIGNAL_TYPE_DVI_SINGLE_LINK = (1 << 0), + SIGNAL_TYPE_DVI_DUAL_LINK = (1 << 1), + SIGNAL_TYPE_HDMI_TYPE_A = (1 << 2), + SIGNAL_TYPE_LVDS = (1 << 3), + SIGNAL_TYPE_RGB = (1 << 4), + SIGNAL_TYPE_DISPLAY_PORT = (1 << 5), + SIGNAL_TYPE_DISPLAY_PORT_MST = (1 << 6), + SIGNAL_TYPE_EDP = (1 << 7), + SIGNAL_TYPE_WIRELESS = (1 << 8), /* Wireless Display */ + SIGNAL_TYPE_VIRTUAL = (1 << 9), /* Virtual Display */ + + SIGNAL_TYPE_COUNT = 10, + SIGNAL_TYPE_ALL = (1 << SIGNAL_TYPE_COUNT) - 1 +}; + +/* help functions for signal types manipulation */ +bool dc_is_hdmi_signal(enum signal_type signal); +bool dc_is_dp_sst_signal(enum signal_type signal); +bool dc_is_dp_signal(enum signal_type signal); +bool dc_is_dp_external_signal(enum signal_type signal); +bool dc_is_analog_signal(enum signal_type signal); +bool dc_is_embedded_signal(enum signal_type signal); +bool dc_is_dvi_signal(enum signal_type signal); +bool dc_is_dvi_single_link_signal(enum signal_type signal); +bool dc_is_dual_link_signal(enum signal_type signal); +bool dc_is_audio_capable_signal(enum signal_type signal); +bool dc_is_digital_encoder_compatible_signal(enum signal_type signal); + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/vector.h b/drivers/gpu/drm/amd/dal/include/vector.h new file mode 100644 index 000000000000..8233b7c22a07 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/vector.h @@ -0,0 +1,150 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_VECTOR_H__ +#define __DAL_VECTOR_H__ + +struct vector { + uint8_t *container; + uint32_t struct_size; + uint32_t count; + uint32_t capacity; + struct dc_context *ctx; +}; + +bool dal_vector_construct( + struct vector *vector, + struct dc_context *ctx, + uint32_t capacity, + uint32_t struct_size); + +struct vector *dal_vector_create( + struct dc_context *ctx, + uint32_t capacity, + uint32_t struct_size); + +/* 'initial_value' is optional. If initial_value not supplied, + * each "structure" in the vector will contain zeros by default. */ +struct vector *dal_vector_presized_create( + struct dc_context *ctx, + uint32_t size, + void *initial_value, + uint32_t struct_size); + +void dal_vector_destruct( + struct vector *vector); + +void dal_vector_destroy( + struct vector **vector); + +uint32_t dal_vector_get_count( + const struct vector *vector); + +/* dal_vector_insert_at + * reallocate container if necessary + * then shell items at right and insert + * return if the container modified + * do not check that index belongs to container + * since the function is private and index is going to be calculated + * either with by function or as get_count+1 */ +bool dal_vector_insert_at( + struct vector *vector, + const void *what, + uint32_t position); + +bool dal_vector_append( + struct vector *vector, + const void *item); + +/* operator[] */ +void *dal_vector_at_index( + const struct vector *vector, + uint32_t index); + +void dal_vector_set_at_index( + const struct vector *vector, + const void *what, + uint32_t index); + +/* create a clone (copy) of a vector */ +struct vector *dal_vector_clone( + const struct vector *vector_other); + +/* dal_vector_remove_at_index + * Shifts elements on the right from remove position to the left, + * removing an element at position by overwrite means*/ +bool dal_vector_remove_at_index( + struct vector *vector, + uint32_t index); + +uint32_t dal_vector_capacity(const struct vector *vector); + +bool dal_vector_reserve(struct vector *vector, uint32_t capacity); + +void dal_vector_clear(struct vector *vector); + +/*************************************************************************** + * Macro definitions of TYPE-SAFE versions of vector set/get functions. + ***************************************************************************/ + +#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \ + static bool vector_type##_vector_insert_at( \ + struct vector *vector, \ + type_t what, \ + uint32_t position) \ +{ \ + return dal_vector_insert_at(vector, what, position); \ +} + +#define DAL_VECTOR_APPEND(vector_type, type_t) \ + static bool vector_type##_vector_append( \ + struct vector *vector, \ + type_t item) \ +{ \ + return dal_vector_append(vector, item); \ +} + +/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by + * "checkcommit" as *return type*. + * For uniformity reasons "type_t" is used for all type-safe macro + * definitions here. */ +#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \ + static type_t vector_type##_vector_at_index( \ + const struct vector *vector, \ + uint32_t index) \ +{ \ + return dal_vector_at_index(vector, index); \ +} + +#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \ + static void vector_type##_vector_set_at_index( \ + const struct vector *vector, \ + type_t what, \ + uint32_t index) \ +{ \ + dal_vector_set_at_index(vector, what, index); \ +} + +#endif /* __DAL_VECTOR_H__ */ diff --git a/drivers/gpu/drm/amd/dal/include/video_csc_types.h b/drivers/gpu/drm/amd/dal/include/video_csc_types.h new file mode 100644 index 000000000000..c229f5a7a325 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/video_csc_types.h @@ -0,0 +1,135 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_VIDEO_CSC_TYPES_H__ +#define __DAL_VIDEO_CSC_TYPES_H__ + +#include "video_gamma_types.h" + +enum ovl_alpha_blending_mode { + OVL_ALPHA_PER_PIXEL_GRPH_ALPHA_MODE = 0, + OVL_ALPHA_PER_PIXEL_OVL_ALPHA_MODE +}; + +enum ovl_color_space { + OVL_COLOR_SPACE_UNKNOWN = 0, + OVL_COLOR_SPACE_RGB, + OVL_COLOR_SPACE_YUV601, + OVL_COLOR_SPACE_YUV709 +}; + +enum ovl_surface_format { + OVL_SURFACE_FORMAT_UNKNOWN = 0, + OVL_SURFACE_FORMAT_YUY2, + OVL_SURFACE_FORMAT_UYVY, + OVL_SURFACE_FORMAT_RGB565, + OVL_SURFACE_FORMAT_RGB555, + OVL_SURFACE_FORMAT_RGB32, + OVL_SURFACE_FORMAT_YUV444, + OVL_SURFACE_FORMAT_RGB32_2101010 +}; + +struct ovl_color_adjust_option { + uint32_t ALLOW_OVL_RGB_ADJUST:1; + uint32_t ALLOW_OVL_TEMPERATURE:1; + uint32_t FULL_RANGE:1; /* 0 for limited range it'is default for YUV */ + uint32_t OVL_MATRIX:1; + uint32_t RESERVED:28; +}; + +struct overlay_adjust_item { + int32_t adjust; /* InInteger */ + int32_t adjust_divider; +}; + +enum overlay_csc_adjust_type { + OVERLAY_CSC_ADJUST_TYPE_BYPASS = 0, + OVERLAY_CSC_ADJUST_TYPE_HW, /* without adjustments */ + OVERLAY_CSC_ADJUST_TYPE_SW /* use adjustments */ +}; + +enum overlay_gamut_adjust_type { + OVERLAY_GAMUT_ADJUST_TYPE_BYPASS = 0, + OVERLAY_GAMUT_ADJUST_TYPE_SW /* use adjustments */ +}; + +#define TEMPERATURE_MATRIX_SIZE 9 +#define MAXTRIX_SIZE TEMPERATURE_MAXTRIX_SIZE +#define MAXTRIX_SIZE_WITH_OFFSET 12 + +/* overlay adjustment input */ +union ovl_csc_flag { + uint32_t u_all; + struct { + uint32_t CONFIG_IS_CHANGED:1; + uint32_t RESERVED:31; + } bits; +}; + +struct ovl_csc_adjustment { + enum ovl_color_space ovl_cs; + struct ovl_color_adjust_option ovl_option; + enum dc_color_depth display_color_depth; + uint32_t lb_color_depth; + enum pixel_format desktop_surface_pixel_format; + enum ovl_surface_format ovl_sf; + /* API adjustment */ + struct overlay_adjust_item overlay_brightness; + struct overlay_adjust_item overlay_gamma; + struct overlay_adjust_item overlay_contrast; + struct overlay_adjust_item overlay_saturation; + struct overlay_adjust_item overlay_hue; /* unit in degree from API. */ + int32_t f_temperature[TEMPERATURE_MATRIX_SIZE]; + uint32_t temperature_divider; + /* OEM/Application matrix related. */ + int32_t matrix[MAXTRIX_SIZE_WITH_OFFSET]; + uint32_t matrix_divider; + + /* DCE50 parameters */ + struct regamma_lut regamma; + enum overlay_gamma_adjust adjust_gamma_type; + enum overlay_csc_adjust_type adjust_csc_type; + enum overlay_gamut_adjust_type adjust_gamut_type; + union ovl_csc_flag flag; + +}; + +enum ovl_csc_adjust_item { + OVERLAY_BRIGHTNESS = 0, + OVERLAY_GAMMA, + OVERLAY_CONTRAST, + OVERLAY_SATURATION, + OVERLAY_HUE, + OVERLAY_ALPHA, + OVERLAY_ALPHA_PER_PIX, + OVERLAY_COLOR_TEMPERATURE +}; + +struct input_csc_matrix { + enum color_space color_space; + uint16_t regval[12]; +}; + +#endif diff --git a/drivers/gpu/drm/amd/dal/include/video_gamma_types.h b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h new file mode 100644 index 000000000000..6f9cd3fda21d --- /dev/null +++ b/drivers/gpu/drm/amd/dal/include/video_gamma_types.h @@ -0,0 +1,57 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_VIDEO_GAMMA_TYPES_H__ +#define __DAL_VIDEO_GAMMA_TYPES_H__ + +#include "set_mode_types.h" +#include "gamma_types.h" + +enum overlay_gamma_adjust { + OVERLAY_GAMMA_ADJUST_BYPASS, + OVERLAY_GAMMA_ADJUST_HW, /* without adjustments */ + OVERLAY_GAMMA_ADJUST_SW /* use adjustments */ + +}; + +union video_gamma_flag { + struct { + uint32_t CONFIG_IS_CHANGED:1; + uint32_t RESERVED:31; + } bits; + uint32_t u_all; +}; + +struct overlay_gamma_parameters { + union video_gamma_flag flag; + int32_t ovl_gamma_cont; + enum overlay_gamma_adjust adjust_type; + enum pixel_format desktop_surface; + struct regamma_lut regamma; + + /* here we grow with parameters if necessary */ +}; + +#endif