On 12:33-20220419, Aradhya Bhatia wrote:
The DSS IP on the ti-am65x soc supports an additional register space, named "common1". Further. the IP services a maximum number of 2 interrupts.
Add the missing register space "common1" and the additional interrupt.
Signed-off-by: Aradhya Bhatia a-bhatia1@ti.com
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..102059e9e0d5 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -26,6 +26,7 @@ properties: Addresses to each DSS memory region described in the SoC's TRM. items: - description: common DSS register area
- description: common1 DSS register area - description: VIDL1 light video plane - description: VID video plane - description: OVR1 overlay manager for vp1@@ -36,6 +37,7 @@ properties: reg-names: items: - const: common
- const: common1 - const: vidl1 - const: vid - const: ovr1@@ -64,7 +66,7 @@ properties: maxItems: 3
interrupts:
- maxItems: 1
- maxItems: 2
What are the interrupts supposed to be?
power-domains: maxItems: 1 @@ -122,13 +124,14 @@ examples: dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x04a00000 0x1000>, /* common */
reg = <0x04a01000 0x1000>, /* common1 */ <0x04a02000 0x1000>, /* vidl1 */ <0x04a06000 0x1000>, /* vid */ <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ <0x04a0b000 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
reg-names = "common", "common1". "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;@@ -136,7 +139,8 @@ examples: <&k3_clks 216 1>, <&k3_clks 67 2>; clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; ports { #address-cells = <1>; #size-cells = <0>;-- 2.35.3