The GPU has an idle state register where each bit represents the idle state of a sub-GPU component like FE or TX. Sample this register every 10ms and calculate a simple moving average over the sub-GPU component idle states with a total observation time frame of 1s.
This provides us with a percentage based load of each sub-GPU component.
Signed-off-by: Christian Gmeiner christian.gmeiner@gmail.com --- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 14 ++++++++++++ drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 32 +++++++++++++++++++++++++++ drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 29 ++++++++++++++++++++++++ 3 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index f9afe11c50f0..b31920241c86 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -46,6 +46,19 @@ static void load_gpu(struct drm_device *dev) } }
+static void unload_gpu(struct drm_device *dev) +{ + struct etnaviv_drm_private *priv = dev->dev_private; + unsigned int i; + + for (i = 0; i < ETNA_MAX_PIPES; i++) { + struct etnaviv_gpu *g = priv->gpu[i]; + + if (g) + etnaviv_gpu_shutdown(g); + } +} + static int etnaviv_open(struct drm_device *dev, struct drm_file *file) { struct etnaviv_drm_private *priv = dev->dev_private; @@ -581,6 +594,7 @@ static void etnaviv_unbind(struct device *dev) struct drm_device *drm = dev_get_drvdata(dev); struct etnaviv_drm_private *priv = drm->dev_private;
+ unload_gpu(drm); drm_dev_unregister(drm);
component_unbind_all(dev, drm); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index a31eeff2b297..1f0eb7e00657 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -714,6 +714,28 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); }
+static void etnaviv_loadavg_function(struct timer_list *t) +{ + struct etnaviv_gpu *gpu = from_timer(gpu, t, loadavg_timer); + const u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); + int i; + + for (i = 0; i < ARRAY_SIZE(etna_idle_module_names); i++) + if ((idle & etna_idle_module_names[i].bit)) + sma_loadavg_add(&gpu->loadavg_value[i], 0); + else + sma_loadavg_add(&gpu->loadavg_value[i], 100); + + spin_lock_bh(&gpu->loadavg_spinlock); + + for (i = 0; i < ARRAY_SIZE(etna_idle_module_names); i++) + gpu->loadavg_percentage[i] = sma_loadavg_read(&gpu->loadavg_value[i]); + + spin_unlock_bh(&gpu->loadavg_spinlock); + + mod_timer(t, jiffies + msecs_to_jiffies(10)); +} + int etnaviv_gpu_init(struct etnaviv_gpu *gpu) { struct etnaviv_drm_private *priv = gpu->drm->dev_private; @@ -804,6 +826,10 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) for (i = 0; i < ARRAY_SIZE(gpu->event); i++) complete(&gpu->event_free);
+ /* Setup loadavg timer */ + timer_setup(&gpu->loadavg_timer, etnaviv_loadavg_function, 0); + mod_timer(&gpu->loadavg_timer, jiffies + msecs_to_jiffies(10)); + /* Now program the hardware */ mutex_lock(&gpu->lock); etnaviv_gpu_hw_init(gpu); @@ -824,6 +850,11 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) return ret; }
+void etnaviv_gpu_shutdown(struct etnaviv_gpu *gpu) +{ + del_timer(&gpu->loadavg_timer); +} + #ifdef CONFIG_DEBUG_FS struct dma_debug { u32 address[2]; @@ -1762,6 +1793,7 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) gpu->dev = &pdev->dev; mutex_init(&gpu->lock); mutex_init(&gpu->fence_lock); + spin_lock_init(&gpu->loadavg_spinlock);
/* Map registers: */ gpu->mmio = devm_platform_ioremap_resource(pdev, 0); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 8ea48697d132..a5b9c89c6744 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -10,6 +10,8 @@ #include "etnaviv_gem.h" #include "etnaviv_mmu.h" #include "etnaviv_drv.h" +#include "etnaviv_sma.h" +#include "state_hi.xml.h"
struct etnaviv_gem_submit; struct etnaviv_vram_mapping; @@ -91,6 +93,26 @@ struct clk;
#define ETNA_NR_EVENTS 30
+DECLARE_SMA(loadavg, 100) + +static const struct { + const char *name; + u32 bit; +} etna_idle_module_names[] = { + { "FE", VIVS_HI_IDLE_STATE_FE }, + { "DE", VIVS_HI_IDLE_STATE_DE }, + { "PE", VIVS_HI_IDLE_STATE_PE }, + { "SH", VIVS_HI_IDLE_STATE_SH }, + { "PA", VIVS_HI_IDLE_STATE_PA }, + { "SE", VIVS_HI_IDLE_STATE_SE }, + { "RA", VIVS_HI_IDLE_STATE_RA }, + { "TX", VIVS_HI_IDLE_STATE_TX }, + { "VG", VIVS_HI_IDLE_STATE_VG }, + { "IM", VIVS_HI_IDLE_STATE_IM }, + { "FP", VIVS_HI_IDLE_STATE_FP }, + { "TS", VIVS_HI_IDLE_STATE_TS }, +}; + struct etnaviv_gpu { struct drm_device *drm; struct thermal_cooling_device *cooling; @@ -145,6 +167,12 @@ struct etnaviv_gpu { unsigned int freq_scale; unsigned long base_rate_core; unsigned long base_rate_shader; + + /* Loadavg: */ + struct timer_list loadavg_timer; + spinlock_t loadavg_spinlock; + struct sma_loadavg loadavg_value[ARRAY_SIZE(etna_idle_module_names)]; + unsigned int loadavg_percentage[ARRAY_SIZE(etna_idle_module_names)]; };
static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) @@ -160,6 +188,7 @@ static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
int etnaviv_gpu_init(struct etnaviv_gpu *gpu); +void etnaviv_gpu_shutdown(struct etnaviv_gpu *gpu); bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
#ifdef CONFIG_DEBUG_FS