RE: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

Hi Rob,

Subject: RE: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

Hi Rob,

Thanks for the feedback.

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Subject: Re: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

On Mon, Mar 14, 2022 at 04:10:02PM +0000, Biju Das wrote:

...

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com

RFC->v1:

• Added a ref to dsi-controller.yaml.

RFC:-

---

.../bindings/display/bridge/renesas,dsi.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml new file mode 100644 index 000000000000..74bc3782d230 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.y +++ am +++ l @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id:

+title: Renesas RZ/G2L MIPI DSI Encoder

+maintainers:

• • Biju Das biju.das.jz@bp.renesas.com

+description: |

• This binding describes the MIPI DSI encoder embedded in the

+Renesas

• RZ/G2L family of SoC's. The encoder can operate in DSI mode with

+up

• to four data lanes.

+allOf:

• • $ref: ../dsi-controller.yaml#

Full path preferred:

/schemas/display/dsi-controller.yaml#

OK. Will fix this.

...

...

+properties:

• compatible:
• enum:

•  - renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L
  

• reg:
• items:

•  - description: Link register
  

•  - description: D-PHY register
  

D-PHY is not a separate block?

Got it. I will model as a single block.

Regards, Biju

Basically D-PHY is integrated inside MIPI-DSI Tx module.

MIPI-DSI Tx module consists of MIPI DSI-2 Host controller (LINK) and MIPI D-PHY Tx(D-PHY).

That is the reason I have modelled like this.

Is this model ok or am I missing something here? Please let me know.

...

...

• clocks:
• items:

•  - description: DSI D-PHY PLL multiplied clock
  

•  - description: DSI D-PHY system clock
  

•  - description: DSI AXI bus clock
  

•  - description: DSI Register access clock
  

•  - description: DSI Video clock
  

•  - description: DSI D_PHY Escape mode Receive clock
  

D-PHY

OK, Will fix this.

Regards, Biju

...

...

• clock-names:
• items:

•  - const: pllclk
  

•  - const: sysclk
  

•  - const: aclk
  

•  - const: pclk
  

•  - const: vclk
  

•  - const: lpclk
  

• power-domains:
• maxItems: 1
• resets:
• items:

•  - description: MIPI_DSI_CMN_RSTB
  

•  - description: MIPI_DSI_ARESET_N
  

•  - description: MIPI_DSI_PRESET_N
  

• reset-names:
• items:

•  - const: rst
  

•  - const: arst
  

•  - const: prst
  

• ports:
• $ref: /schemas/graph.yaml#/properties/ports
• properties:

•  port@0:
  

•    $ref: /schemas/graph.yaml#/properties/port
  

•    description: Parallel input port
  

•  port@1:
  

•    $ref: /schemas/graph.yaml#/$defs/port-base
  

•    unevaluatedProperties: false
  

•    description: DSI output port
  

•    properties:
  

•      endpoint:
  

•        $ref: /schemas/media/video-interfaces.yaml#
  

•        unevaluatedProperties: false
  

•        properties:
  

•          data-lanes:
  

•            minItems: 1
  

•            maxItems: 4
  

•        required:
  

•          - data-lanes
  

• required:

•  - port@0
  

•  - port@1
  

+required:

• • compatible
• • reg
• • clocks
• • clock-names
• • power-domains
• • resets
• • reset-names
• • ports

+additionalProperties: false

+examples:

• • |
• #include <dt-bindings/clock/r9a07g044-cpg.h>
• dsi0: dsi@10860000 {

•    compatible = "renesas,rzg2l-mipi-dsi";
  

•    reg = <0x10860000 0x10000>,
  

•          <0x10850000 0x10000>;
  

•    power-domains = <&cpg>;
  

•    clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
  

•             <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
  

•    clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk",
  

"lpclk";

...

•    resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
  

•             <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
  

•             <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
  

•    reset-names = "rst", "arst", "prst";
  

•    ports {
  

•        #address-cells = <1>;
  

•        #size-cells = <0>;
  

•        port@0 {
  

•            reg = <0>;
  

•            dsi0_in: endpoint {
  

•                remote-endpoint = <&du_out_dsi0>;
  

•            };
  

•        };
  

•        port@1 {
  

•            reg = <1>;
  

•            dsi0_out: endpoint {
  

•                data-lanes = <1 2 3 4>;
  

•                remote-endpoint = <&adv7535_in>;
  

•            };
  

•        };
  

•    };
  

• };

+...

2.17.1