On Sun, Sep 26, 2021 at 10:10:05PM +0200, Michal Wajdeczko wrote:
We assumed that for all modern GENs the PTEs and register space are split in the GTTMMADR BAR, but while it is true, we should rather use fixed offset as it is defined in the specification.
Bspec: 4409, 4457, 4604, 11181, 9027, 13246, 13321, 44980
Signed-off-by: Michal Wajdeczko michal.wajdeczko@intel.com Cc: CQ Tang cq.tang@intel.com Cc: Matt Roper matthew.d.roper@intel.com
Matches the descriptions on all the various bspec pages.
Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_ggtt.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index ba7c7ed89fa8..f17383e76eb7 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -813,6 +813,21 @@ static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) return 0; }
+static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915) +{
- /*
* GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset* GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset*/- GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
- return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
+}
+static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915) +{
- return gen6_gttmmadr_size(i915) / 2;
+}
static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) { struct drm_i915_private *i915 = ggtt->vm.i915; @@ -821,8 +836,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) u32 pte_flags; int ret;
- /* For Modern GENs the PTEs and register space are split in the BAR */
- phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
/*
- On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
-- 2.25.1