On Mi, 2022-04-06 at 18:01 +0200, Lucas Stach wrote:
This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a full timing generator and can switch between different video sources. On the i.MX8MP however the only supported source is the LCDIF. The block just needs to be powered up and told about the polarity of the video sync signals to act in bypass mode.
Signed-off-by: Lucas Stach l.stach@pengutronix.de
[...]
+static void imx_hdmi_pvi_bridge_enable(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state)
+{
- struct drm_atomic_state *state = bridge_state->base.state;
- struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
- struct drm_connector_state *conn_state;
- const struct drm_display_mode *mode;
- struct drm_crtc_state *crtc_state;
- struct drm_connector *connector;
- u32 bus_flags, val;
- connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
- if (WARN_ON(!connector))
return;
- conn_state = drm_atomic_get_new_connector_state(state, connector);
- if (WARN_ON(!conn_state))
return;
- crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- if (WARN_ON(!crtc_state))
return;
Can those happen at all, and if so, should they be caught at atomic_check time?
- if (WARN_ON(pm_runtime_resume_and_get(pvi->dev)))
return;
Should be pm_runtime_get_sync(), since the error is ignored.
Otherwise the pm_runtime_put() in imx_hdmi_pvi_bridge_disable() will double-decrement the usage counter in case this failed.
regards Philipp