Hi Philipp,
On Tue, Jun 9, 2015 at 7:39 PM, Philipp Zabel p.zabel@pengutronix.de wrote:
Hi Gary,
Am Dienstag, den 09.06.2015, 17:59 +0200 schrieb Gary Bisson:
Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver.
The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz.
This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/
Signed-off-by: Gary Bisson gary.bisson@boundarydevices.com
.../bindings/panel/okaya,rs800480t_7x0gp.txt | 7 ++++++ drivers/gpu/drm/panel/panel-simple.c | 27 ++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt
diff --git a/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt new file mode 100644 index 0000000..f7c729d --- /dev/null +++ b/Documentation/devicetree/bindings/panel/okaya,rs800480t_7x0gp.txt @@ -0,0 +1,7 @@ +OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
+Required properties: +- compatible: should be "okaya,rs800480t_7x0gp"
+This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 97b66b8..e511a22 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -942,6 +942,30 @@ static const struct panel_desc lg_lp129qe = { }, };
+static const struct display_timing okaya_rs800480t_7x0gp_timing = {
.pixelclock = { 30000000, 30000000, 40000000 },.hactive = { 800, 800, 800 },.hfront_porch = { 40, 40, 40 },.hback_porch = { 40, 40, 40 },.hsync_len = { 1, 48, 48 },.vactive = { 480, 480, 480 },.vfront_porch = { 13, 13, 13 },.vback_porch = { 29, 29, 29 },.vsync_len = { 3, 3, 3 },.flags = DISPLAY_FLAGS_DE_HIGH,+};
+static const struct panel_desc okaya_rs800480t_7x0gp = {
.timings = &okaya_rs800480t_7x0gp_timing,.num_timings = 1,.bpc = 6,.size = {.width = 154,.height = 87,},Are there any poweron/poweroff sequencing delays in the datasheet that should be met? Parallel displays often specify a few ms delay after the voltage supply is stable and before pixel data should be driven on the bus (.delay.prepare), as well as afterwards, before activating the backlight (.delay.enable).
You are right I forgot to add those delays. I will submit a v3.
That gives prepare = unprepare = 40.5ms (rounded up to 41) and enable = disable = 50ms based on the values provided at page 6/20 of the following doc: http://boundarydevices.com/datasheets/RS800480T-7X0GP-A.pdf
Regards, Gary