Hi GVRao,
On Sun, May 31, 2020 at 05:41:50PM +0000, Venkateshwar Rao Gannavarapu wrote:
On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote:
On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface.
It supports upto 4 lanes, optional register interface for the DPHY,
I don't see the register interface for dphy support.
I think the D-PHY should be supported through a PHY driver, as it seems to be shared between different subsystems.
IP has the provision to read DPHY register for debug purpose only. No programming of DPHY is required in subsystem.
Do you know if this is the same D-PHY as used in the CSI2-RX subsystem ?
multiple RGB color formats, command mode and video mode. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework.
Signed-off-by: Venkateshwar Rao Gannavarapu venkateshwar.rao.gannavarapu@xilinx.com
drivers/gpu/drm/xlnx/Kconfig | 11 + drivers/gpu/drm/xlnx/Makefile | 2 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 ++++++++++++++++++++++++++++++++++++++++
Daniel Vetter has recently expressed his opiion that bridge drivers should go to drivers/gpu/drm/bridge/. It would then be drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself.
3 files changed, 768 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c
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