On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
for 5 or 6 bpc panel, we need enable dither function to improve the display quality
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Hsin-Yi Wang hsinyi@chromium.org
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..e85625704d611 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4)
#define LUT_10BIT_MASK 0x03ff
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
- bool enable = false;
- /* default value for dither reg 5 to 14 */
- const u32 dither_setting[] = {
0x00000000, /* 5 */0x00003002, /* 6 */0x00000000, /* 7 */0x00000000, /* 8 */0x00000000, /* 9 */0x00000000, /* 10 */0x00000000, /* 11 */0x00000011, /* 12 */0x00000000, /* 13 */0x00000000, /* 14 */Could you explain what is this?
this is dither 5 to dither 14 setting this will be useless, we just need set dither 5 and dither 7 like mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); other value is same with hardware default value.
- };
- if (bpc == 5 || bpc == 6) {
enable = true;mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,&priv->cmdq_reg, priv->regs, DITHER_REG(15));mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),This result in 0x50505050, but previous version is 0x50504040, so this version is correct and previous version is incorrect?
the new version set r g b 3 channel same, seams more reasonable
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15, DISP_DITHER_16 is identical to mtk_dither_set(), so call mtk_dither_set() instead of duplication here.
dither enable set in mtk_dither_set is mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
that is different 8183 and mt8192. mt8173 dither enable in gamma is bit2 mt8183 and mt8192 dither engine enable is bit 1
Regards, CK
Regards, CK
&priv->cmdq_reg, priv->regs, DITHER_REG(16));- }
- if (enable) {
u32 idx;for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs,DITHER_REG(idx + 5));- }
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);}
static void mtk_dither_start(struct device *dev)