This patch adds support for controlling power of hdmi phy for exynos5 soc. A special bit is provided in exynos5 for directly switching of PHY while in exynos4, phy power needs to be controlled through i2c settings. I2C configuration may affect the suspend to resume and wake-up time requirements hence not added.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 21 +++++++++++++++++++++ drivers/gpu/drm/exynos/regs-hdmi.h | 5 +++++ 2 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index a85fc58..74e38a5 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1877,6 +1877,24 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) mdelay(10); }
+static void hdmiphy_poweron(struct hdmi_context *hdata) +{ + DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); + + if (hdata->type == HDMI_TYPE14) + hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, + HDMI_PHY_POWER_OFF_EN); +} + +static void hdmiphy_poweroff(struct hdmi_context *hdata) +{ + DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); + + if (hdata->type == HDMI_TYPE14) + hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, + HDMI_PHY_POWER_OFF_EN); +} + static void hdmiphy_conf_apply(struct hdmi_context *hdata) { const u8 *hdmiphy_data; @@ -2068,6 +2086,8 @@ static void hdmi_poweron(struct hdmi_context *hdata) clk_enable(res->hdmiphy); clk_enable(res->hdmi); clk_enable(res->sclk_hdmi); + + hdmiphy_poweron(hdata); }
static void hdmi_poweroff(struct hdmi_context *hdata) @@ -2086,6 +2106,7 @@ static void hdmi_poweroff(struct hdmi_context *hdata) * its reset state seems to meet the condition. */ hdmiphy_conf_reset(hdata); + hdmiphy_poweroff(hdata);
clk_disable(res->sclk_hdmi); clk_disable(res->hdmi); diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h index 9cc7c5e..59ff7fa 100644 --- a/drivers/gpu/drm/exynos/regs-hdmi.h +++ b/drivers/gpu/drm/exynos/regs-hdmi.h @@ -176,6 +176,11 @@ #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)
+/* PHY Control bit definition */ + +/* HDMI_PHY_CON_0 */ +#define HDMI_PHY_POWER_OFF_EN (1 << 0) + /* Video related registers */ #define HDMI_YMAX HDMI_CORE_BASE(0x0060) #define HDMI_YMIN HDMI_CORE_BASE(0x0064)