On Mon, Mar 26, 2012 at 04:47:11PM +0200, Daniel Vetter wrote:
On Mon, Mar 26, 2012 at 10:26:41PM +0800, Daniel Kurtz wrote:
According to i915 documentation [1], "Port D" (DP/HDMI Port D) is actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b). Pin pair 7 is a reserved pair.
[1] Documentation for [DevSNB+] and [DevIBX], as found on http://intellinuxgraphics.org
Note: the "reserved" and "disabled" pairs do not actually map to a physical pair of pins, nor GPIO regs and shouldn't be initialized or used. Fixing this is left for a later patch.
This bug has not been noticed for two reasons:
- "gmbus" mode is currently disabled - all transfers are actually using "bit-bang" mode which uses the GPIO port 5 (the "HDMI/DPD CTLDATA/CLK" pair), at register 0x5024 (defined as GPIOF i915_reg.h). Since this is the correct pair of pins for HDMI1, transfers succeed.
... this is no longer true on drm-intel-next.
- Even if gmbus mode is re-enabled, the first attempted transaction will fail because it tries to use the wrong ("Reserved") pin pair. However, the driver immediately falls back again to the bit-bang method, which correctly uses GPIOF, so again, transfers succeed.
However, if gmbus mode is re-enabled and the GPIO fall-back mode is disabled, then reading an attached monitor's EDID fail.
Signed-off-by: Daniel Kurtz djkurtz@chromium.org
Otherwise this looks ok to me - I've checked with gen3 Bspec and we seem to indeed have a 1:1 mapping, see "Display Registers", 1.5.3 "GPIO Control Registers", the list right below the heading.
well, scrap that, I've confused myself here a bit. Afaict we don't actually use these gmbus ports on earlier chips.
Reviewed-by: Daniel Vetter daniel.vetter@ffwll.ch
When resending, can you please add the Bspec reference above?
Can you you instead add a clear reference (Volume, Full Section plus Heading Title) for the Snb/Ibx public Bspec.
Thanks, Daneil