Re: [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195

Hi, Jason:

jason-jh.lin jason-jh.lin@mediatek.com 於 2021年9月21日 週二 下午11:52寫道：

add MERGE additional properties description for mt8195:

1. async clock
2. fifo setting enable
3. reset controller

Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com

.../display/mediatek/mediatek,merge.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 75beeb207ceb..542dd7137d3b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,6 +38,19 @@ properties: clocks: items: - description: MERGE Clock

•  - description: MERGE Async Clock
  

•      Controlling the synchronous process between MERGE and other display
  

•      function blocks cross clock domain.
  

• mediatek,merge-fifo-en:

• description:

•  The setting of merge fifo is mainly provided for the display latency
  

•  buffer to ensure that the back-end panel display data will not be
  

•  underrun, a little more data is needed in the fifo.
  

•  According to the merge fifo settings, when the water level is detected
  

•  to be insufficient, it will trigger RDMA sending ultra and preulra
  

•  command to SMI to speed up the data rate.
  

• type: boolean

  mediatek,gce-client-reg: description:

@@ -50,6 +63,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1

• resets:
• description: reset controller

•  See Documentation/devicetree/bindings/reset/reset.txt for details.
  

• maxItems: 1

required:

• compatible
• reg

@@ -67,3 +85,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; };

• merge5: disp_vpp_merge5@1c110000 {

•    compatible = "mediatek,mt8195-disp-merge";
  

•    reg = <0 0x1c110000 0 0x1000>;
  

•    interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
  

•    clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
  

•             <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
  

•    clock-names = "merge","merge_async";
  

Define clock-names first.

Regards, Chun-Kuang.

•    power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
  

•    mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
  

•    mediatek,merge-fifo-en = <1>;
  

•    resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
  

• };

-- 2.18.0