Il 18/02/22 11:07, xinlei.lee@mediatek.com ha scritto:
From: Xinlei Lee xinlei.lee@mediatek.com
Convert mediatek,dsi.txt to mediatek,dsi.yaml format
Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
.../display/mediatek/mediatek,dsi.txt | 62 -------------- .../display/mediatek/mediatek,dsi.yaml | 85 +++++++++++++++++++ 2 files changed, 85 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@
-Mediatek DSI Device
-The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output.
-Required properties: -- compatible: "mediatek,<chip>-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
-Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1].
-[1] Documentation/devicetree/bindings/reset/reset.txt
-MIPI TX Configuration Module
-See phy/mediatek,dsi-phy.yaml
-Example:
-mipi_tx0: mipi-dphy@10215000 {
- compatible = "mediatek,mt8173-mipi-tx";
- reg = <0 0x10215000 0 0x1000>;
- clocks = <&clk26m>;
- clock-output-names = "mipi_tx0_pll";
- #clock-cells = <0>;
- #phy-cells = <0>;
- drive-strength-microamp = <4600>;
- nvmem-cells= <&mipi_tx_calibration>;
- nvmem-cell-names = "calibration-data";
-};
-dsi0: dsi@1401b000 {
- compatible = "mediatek,mt8173-dsi";
- reg = <0 0x1401b000 0 0x1000>;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;- clock-names = "engine", "digital", "hs";
- resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
- phys = <&mipi_tx0>;
- phy-names = "dphy";
- port {
dsi0_out: endpoint {remote-endpoint = <&panel_in>;};- };
-}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 000000000000..552a013786fe --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: mediatek DSI Controller Device Tree Bindings
Shouldn't this be "MediaTek"?
+maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao Shi jitao.shi@mediatek.com
- Xinlei Lee xinlei.lee@mediatek.com
+properties:
- compatible:
- enum:
- mediatek,mt2701-dsi- mediatek,mt8173-dsi- mediatek,mt8183-dsi- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- maxItems: 1
- clocks:
- items:
- description: Engine Clock- description: Digital Clock- description: Hs Clock
HS should be all capital letters.
- clock-names:
- items:
- const: engine- const: digital- const: hs- resets:
- maxItems: 1
- phys:
- maxItems: 1
- phy-names:
- items:
- const: dphy
Add #address-cells, #size-cells with const 2
+required:
- compatible
- reg
- interrupts
- power-domains
- clocks
- clock-names
- phys
- phy-names
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/clock/mt8183-clk.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/power/mt8183-power.h>
- #include <dt-bindings/phy/phy.h>
- #include <dt-bindings/reset/mt8183-resets.h>
Since all users are using two address and size cells:
soc { #address-cells = <2>; #size-cells = <2>;
dsi0: dsi@14014000 { compatible = "mediatek,mt8183-dsi"; reg = <0 0x14014000 0 0x1000>; .....etc..... }; };
- dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi";reg = <0x14014000 0x1000>;interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;clocks = <&mmsys CLK_MM_DSI0_MM>,<&mmsys CLK_MM_DSI0_IF>,<&mipi_tx0>;clock-names = "engine", "digital", "hs";resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;phys = <&mipi_tx0>;phy-names = "dphy";- };