Hi Maxime
On Thu, 25 Feb 2021 at 15:59, Maxime Ripard maxime@cerno.tech wrote:
The HDMI controller on the BCM2711 includes a scrambler in order to reach the modes that require it. Let's add the support for it.
Signed-off-by: Maxime Ripard maxime@cerno.tech
drivers/gpu/drm/vc4/vc4_hdmi.c | 58 +++++++++++++++++++++++++++++ drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 ++ 2 files changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index f05f6da286f7..1a6babb53cf4 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -35,6 +35,7 @@ #include <drm/drm_edid.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> +#include <drm/drm_scdc_helper.h> #include <linux/clk.h> #include <linux/component.h> #include <linux/i2c.h> @@ -76,6 +77,8 @@ #define VC5_HDMI_VERTB_VSPO_SHIFT 16 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
+#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
@@ -445,6 +448,58 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) vc4_hdmi_set_audio_infoframe(encoder); }
+#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
Something feels a bit funny here. drm-misc-next already has a commit [1] that adds a define HDMI_14_MAX_TMDS_CLK. Part of it is in the diff for 3/8. So is there a need to redefine it in this patch?
[1] https://cgit.freedesktop.org/drm/drm-misc/commit/drivers/gpu/drm/vc4/vc4_hdm...
+static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
struct drm_display_mode *mode)+{
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);struct drm_display_info *display = &vc4_hdmi->connector.display_info;if (!vc4_encoder->hdmi_monitor)return false;if (!display->hdmi.scdc.supported ||!display->hdmi.scdc.scrambling.supported)return false;if ((mode->clock * 1000) < HDMI_14_MAX_TMDS_CLK)return false;return true;+}
+static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) +{
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);if (!vc4_hdmi_supports_scrambling(encoder, mode))return;drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);drm_scdc_set_scrambling(vc4_hdmi->ddc, true);HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |VC5_HDMI_SCRAMBLER_CTL_ENABLE);+}
+static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) +{
struct drm_display_mode *mode = &encoder->crtc->mode;struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);if (!vc4_hdmi_supports_scrambling(encoder, mode))return;HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &~VC5_HDMI_SCRAMBLER_CTL_ENABLE);drm_scdc_set_scrambling(vc4_hdmi->ddc, false);drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);+}
static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) { @@ -457,6 +512,8 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
vc4_hdmi_disable_scrambling(encoder);}
static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, @@ -901,6 +958,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, }
vc4_hdmi_recenter_fifo(vc4_hdmi);
vc4_hdmi_enable_scrambling(encoder);}
static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h index e1b58eac766f..6897586228ad 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h @@ -100,6 +100,7 @@ enum vc4_hdmi_field { HDMI_RM_FORMAT, HDMI_RM_OFFSET, HDMI_SCHEDULER_CONTROL,
HDMI_SCRAMBLER_CTL, HDMI_SW_RESET_CONTROL, HDMI_TX_PHY_CHANNEL_SWAP, HDMI_TX_PHY_CLK_DIV,@@ -234,6 +235,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = { VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
Nit pick: the rest of these registers are in numerical order, but these new additions aren't.
Dave
VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),@@ -313,6 +315,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = { VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4), VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),-- 2.29.2