https://bugzilla.kernel.org/show_bug.cgi?id=28932
Florian Mickler florian@mickler.org changed:
What |Removed |Added ---------------------------------------------------------------------------- CC| |florian@mickler.org
--- Comment #6 from Chris Kennedy bitbytebit@gmail.com 2011-02-18 13:36:01 --- I think there's an issue with some legacy chips plus low dotclocks and that same patch, oddly the only little part I can see which could do this is...
@@ -849,7 +951,7 @@ void radeon_compute_pll(struct radeon_pll *pll, max_fractional_feed_div = pll->max_frac_feedback_div; }
- for (post_div = max_post_div; post_div >= min_post_div; --post_div) { + for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { uint32_t ref_div;
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
Although it's basically looking like that must be the issue. A person has a ATI Radeon 9200SE 5964 (AGP)and with 2.6.38-rc4-git4+ it works while with 2.6.38-rc5 there are certain (not all) modelines with low dotclocks that end up being totally out of sync.
Here's an example of a non-working modeline for him with the newer kernel, vs. the older one step back before the patch with the above change...
# toki 256x224@59.61 15.6774Khz ModeLine "256x224x59.61" 5.518455 256 272 304 352 224 235 238 263 -HSync -VSync
There's a lot of other ones thought that can work with the same lower dotclocks, so I'm not sure why that is, but I can have him test with that change in the legacy pll computation reversed. Yet from what I can tell, that is the only code his Radeon should be hitting that changed in the patch.
Thanks, Chris
--- Comment #7 from Florian Mickler florian@mickler.org 2011-02-20 00:03:57 --- merged in .38-rc5: commit a4b40d5d97f5c9ad0b7f4bf2818291ca184bb433 Author: Alex Deucher alexdeucher@gmail.com Date: Mon Feb 14 11:43:10 2011 -0500
drm/radeon/kms: add bounds checking to avivo pll algo