On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote:
Adds a bit of flexibility to support SoCs without CK/DE pol support
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4746eb342567..545a1337cc89 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts;
- bool is_ck_de_pol; const struct mtk_dpi_yc_limit *limit;
};
@@ -211,13 +212,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol;
- unsigned int mask;
- pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL)
|
(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL)|
(dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 :HSYNC_POL) |
- mask = HSYNC_POL | VSYNC_POL;
- pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 :
HSYNC_POL) | (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
- if (dpi->conf->is_ck_de_pol) {
mask |= CK_POL | DE_POL;pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ?0 : CK_POL) |(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ?0 : DE_POL);- }
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask);
}
static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -799,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
- .is_ck_de_pol = true, .limit = &mtk_dpi_limit,
};
@@ -809,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
- .is_ck_de_pol = true, .limit = &mtk_dpi_limit,
};
@@ -818,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
- .is_ck_de_pol = true, .limit = &mtk_dpi_limit,
};
@@ -827,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts),
- .is_ck_de_pol = true, .limit = &mtk_dpi_limit,
};
Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com