On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote:
This phy controller is embedded in the Display Port Controller on mt8195 SoCs.
Sorry, but I think you need to go back to what you had in v8. While yes, the phy and controller IP often do change independently, this h/w looks pretty interwined.
You could make the controller a phy provider to itself if you wanted.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com
.../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml new file mode 100644 index 000000000000..1f5ffca4e140 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2022 MediaTek +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek Display Port PHY
+maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao shi jitao.shi@mediatek.com
+description: |
- Device tree bindings for the Mediatek (embedded) Display Port PHY
- present on some Mediatek SoCs.
+properties:
- compatible:
- enum:
- mediatek,mt8195-dp-phy- mediatek,dp-syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: Phandle to the Display Port node.
- "#phy-cells":
- const: 0
+required:
- compatible
- mediatek,dp-syscon
- "#phy-cells"
+additionalProperties: false
+examples:
- |
- dp_phy: dp-phy {
compatible = "mediatek,mt8195-dp-phy";mediatek,dp-syscon = <&dp_tx>;#phy-cells = <0>;- };
-- 2.34.1