Hello,
Display controllers have a need for minimum memory bandwidth in order to maintain data-stream to output at a required rate. There is a visual corruption once the requirement is violated and CRTC reset may be required in order to recover. This series adds preliminary support for the memory bandwidth management, it will become active once Memory Controller drivers will get support for the PM memory bandwidth QoS.
Dmitry Osipenko (3): drm/tegra: dc: Tune up high priority request controls on Tegra20 drm/tegra: dc: Extend debug stats with total number of events drm/tegra: Support PM QoS memory bandwidth management
drivers/gpu/drm/tegra/dc.c | 234 +++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 13 ++ drivers/gpu/drm/tegra/drm.c | 18 +++ drivers/gpu/drm/tegra/plane.c | 1 + drivers/gpu/drm/tegra/plane.h | 4 +- 5 files changed, 264 insertions(+), 6 deletions(-)