Add a dsi_cfg entry for APQ8064. Since this is the first DSIv2 chip to be supported, add a list of bus clocks that are required by the DSIv2 block.
Signed-off-by: Archit Taneja architt@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 19 ++++++++++++++++--- drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++ 2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index c40044f..2a827d8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -13,9 +13,22 @@
#include "dsi_cfg.h"
-/* DSI v2 has not been supported by now */ -static const struct msm_dsi_config dsi_v2_cfg = { +static const char * const dsi_v2_bus_clk_names[] = { + "core_mmss_clk", "iface_clk", "bus_clk", +}; + +static const struct msm_dsi_config apq8064_dsi_cfg = { .io_offset = 0, + .reg_cfg = { + .num = 3, + .regs = { + {"vdda", 1200000, 1200000, 100000, 100}, + {"avdd", 3000000, 3000000, 110000, 100}, + {"vddio", 1800000, 1800000, 100000, 100}, + }, + }, + .bus_clk_names = dsi_v2_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names), };
static const char * const dsi_6g_bus_clk_names[] = { @@ -75,7 +88,7 @@ static const struct msm_dsi_config msm8994_dsi_cfg = { };
static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { - {MSM_DSI_VER_MAJOR_V2, U32_MAX, &dsi_v2_cfg}, + {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, &msm8974_apq8084_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 5a36836..a68c836 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,8 @@ #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
+#define MSM_DSI_V2_VER_MINOR_8064 0x0 + #define DSI_6G_REG_SHIFT 4
struct msm_dsi_config {