On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
For PSR2 there is no register to tell HW to keep main link enabled
Right, there is no bit in PSR2_CTL Reviewed-by: Dhinakaran Pandiyan dhinakaran.pandiyan@intel.com
while PSR2 is active, so don't configure sink DPCD with a misleading value.
v2: Moving the set of DP_PSR_CRC_VERIFICATION to the else block of 'if (dev_priv->psr.psr2_enabled)' to another patch. (Rodrigo)
Cc: Dhinakaran Pandiyan dhinakaran.pandiyan@intel.com Cc: Rodrigo Vivi rodrigo.vivi@intel.com Signed-off-by: José Roberto de Souza jose.souza@intel.com
drivers/gpu/drm/i915/intel_psr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 40ca6cc43cc4..8515f4a6f4f1 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -395,10 +395,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE); dpcd_val |= DP_PSR_ENABLE_PSR2;
- } else {
if (dev_priv->psr.link_standby)dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
- if (dev_priv->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;