On Tue, Mar 03, 2020 at 10:01:59AM -0700, Jordan Crouse wrote:
On Tue, Mar 03, 2020 at 10:54:05AM -0500, Brian Masney wrote:
On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote:
On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse jcrouse@codeaurora.org wrote:
On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote:
Hi Jordan.
On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote:
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings.
Signed-off-by: Jordan Crouse jcrouse@codeaurora.org
.../devicetree/bindings/display/msm/gmu.txt | 116 -------------------
-Required properties: -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
- for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
- Note that you need to list the less specific "qcom,adreno-gmu"
- for generic matches and the more specific identifier to identify
- the specific device.
-- reg: Physical base address and length of the GMU registers. -- reg-names: Matching names for the register regions
- "gmu"
- "gmu_pdc"
- "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU. -- interrupt-names: Matching names for the interrupts
- "hfi"
- "gmu"
-- clocks: phandles to the device clocks -- clock-names: Matching names for the clocks
- "gmu"
- "cxo"
- "axi"
- "mnoc"
The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong.
-- power-domains: should be:
- <&clock_gpucc GPU_CX_GDSC>
- <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains -- iommus: phandle to the adreno iommu -- operating-points-v2: phandle to the OPP operating points
-Optional properties: -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.This property is not included in the new binding.
Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke.
I thought this was something Brian M added for older targets (A4XX?). Perhaps he should chime in?
Yes, this is needed for older systems with a3xx and a4xx GPUs.
Okay, this got added to the wrong place. The GMU is a specific entity only valid for a6xx targets. From the looks of the example the sram should be in the GPU definition. Do you want to submit a patch to move it or should I (and lets hope Rob doesn't insist on converting GPU to YAML).
I can take care of cleaning this up. I'll do that in a few days.
Brian