Hi Maxime
On Wed, 8 Jul 2020 at 18:43, Maxime Ripard maxime@cerno.tech wrote:
Even though it's not really clear why we need to flush the PV FIFO during the configuration even though we started by flushing it, experience shows that without it we get a stale pixel stuck in the FIFO between the HVS and the PV.
Signed-off-by: Maxime Ripard maxime@cerno.tech
Reviewed-by: Dave Stevenson dave.stevenson@raspberrypi.com
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 13fe0e370fb3..25a77cd46b28 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -358,7 +358,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) if (is_dsi) CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
CRTC_WRITE(PV_CONTROL,
CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |-- git-series 0.9.1