Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
On 19/04/2022 11:41, jason-jh.lin wrote:
- Add mt8195 mmsys compatible for 2 vdosys.
- Add io_start into each driver data of mt8195 vdosys.
- Add get match data function to identify mmsys by io_start.
- Add mt8195 routing table settings of vdosys0.
Signed-off-by: jason-jh.lin jason-jh.lin@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to decide which version of the two mmsys devices we are probing. I think a better approach would be, if we would have added some mediatek specific ID to the device tree binding (or use a two compatibles?).
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.327...
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.977...
we're trying to figure out the way to use the same compatible for different mmsys.
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive change. So I'll take this patch now, but maybe we can discuss if we can't do better in a follow-up patch. Especially I don't think it's a good approach to check for the io_start in the DRM driver. Couldn't we pass the information about which of the two mmsys blocks we are calling from through the mediatek-drm platform device spefic data?
But we can't find a suitable property to identify the different mmsys directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0 and vdosys1. Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own clock, I have tried to differentiate vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.966... But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/dri...
I'm not sure if there is another more suitable idea to fit in this problem. But I believe, if using different compatibles for each mmsys is acceptable, then we can keep the original compatible method for mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-) Thanks for your reviews again.
Regards, Jason-JH.Lin
I also had a look into the vdosys1 series to better understand why we need to do things as we do them. But honestly I wasn't able to really understand the implication of the patch that adds 'multi mmsys support' [1]. For this looks like a several patches that got squashed into one. But as I don't have to maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards, Matthias
[1]
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-media...
Based on series [1]
[1] MediaTek MT8195 display binding
https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-...
drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++- drivers/soc/mediatek/mtk-mmsys.h | 6 + include/linux/soc/mediatek/mtk-mmsys.h | 11 + 4 files changed, 528 insertions(+), 11 deletions(-) create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index 000000000000..13ab0ab64396 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK (1, 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK (13, 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK (20, 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK (21, 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK (22, 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+#define MT8195_VDO0_SEL_OUT 0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK (2, 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK (4, 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK (11, 11) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK (13, 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK (17, 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
- {
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0- }, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0- }, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1- }, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1- }, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1- }, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,MT8195_VDO0_OVL_MOUT_EN,MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_IN,MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE- }, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,MT8195_SEL_IN_DSI1_FROM_VPP_MERGE- }, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1- }, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN- }, {
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,MT8195_SOUT_DISP_DITHER0_TO_DSI0- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT- }, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE- }, {
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_DSI1- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_DP_INTF0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN- }, {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,MT8195_VDO0_SEL_OUT,MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0- }, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0- }, {
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE- }
+};
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 4fc4c2c9ea20..548efed8dc1c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -17,6 +17,7 @@ #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8192-mmsys.h" +#include "mt8195-mmsys.h" #include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_default_routing_table), };
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt2701_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), };
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt2712_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", };
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt6779_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", };
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt6797_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), };
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8167_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, };
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8173_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, };
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8183_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8186_mmsys_driver_data = { .clk_driver = "clk-mt8186-mm", .routes = mmsys_mt8186_routing_table, @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, };
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8186_mmsys_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), };
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8192_mmsys_driver_data,- },
+};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
- .io_start = 0x1c01a000,
- .clk_driver = "clk-mt8195-vdo0",
- .routes = mmsys_mt8195_routing_table,
- .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
- .io_start = 0x1c100000,
- .clk_driver = "clk-mt8195-vdo1",
+};
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
- .num_drv_data = 2,
- .drv_data = {
&mt8195_vdosys0_driver_data,&mt8195_vdosys1_driver_data,- },
+};
- static const struct mtk_mmsys_driver_data
mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), };
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
- .num_drv_data = 1,
- .drv_data = {
&mt8365_mmsys_driver_data,- },
+};
- struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev;
- phys_addr_t io_start; };
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
const structmtk_mmsys_match_data *match) +{
- int i;
- for (i = 0; i < match->num_drv_data; i++)
if (mmsys->io_start == match->drv_data[i]->io_start)return i;- return -EINVAL;
+}
- void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm;
const struct mtk_mmsys_match_data *match_data; struct mtk_mmsys *mmsys;
struct resource *res; int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; }
- mmsys->data = of_device_get_match_data(&pdev->dev);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
dev_err(dev, "Couldn't get mmsys resource\n");return -EINVAL;- }
- mmsys->io_start = res->start;
- match_data = of_device_get_match_data(dev);
- if (match_data->num_drv_data > 1) {
/* This SoC has multiple mmsys channels */ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);if (ret < 0) {dev_err(dev, "Couldn't get match driverdata\n");
return ret;}mmsys->data = match_data->drv_data[ret];} else {
dev_dbg(dev, "Using single mmsys channel\n");mmsys->data = match_data->drv_data[0];}
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data-
clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev) static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data,
.data = &mt2701_mmsys_match_data,
.data = &mt2712_mmsys_driver_data,
.data = &mt2712_mmsys_match_data,
.data = &mt6779_mmsys_driver_data,
.data = &mt6779_mmsys_match_data,
.data = &mt6797_mmsys_driver_data,
.data = &mt6797_mmsys_match_data,
.data = &mt8167_mmsys_driver_data,
.data = &mt8167_mmsys_match_data,
.data = &mt8173_mmsys_driver_data,
.data = &mt8173_mmsys_match_data,
.data = &mt8183_mmsys_driver_data,
.data = &mt8183_mmsys_match_data,
.data = &mt8186_mmsys_driver_data,
.data = &mt8186_mmsys_match_data,
.data = &mt8192_mmsys_driver_data,
.data = &mt8192_mmsys_match_data,- },
- {
.compatible = "mediatek,mt8195-mmsys",.data = &mt8195_mmsys_match_data,
.data = &mt8365_mmsys_driver_data,
.data = &mt8365_mmsys_match_data,diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 77f37f8c715b..f01ba206481d 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -87,12 +87,18 @@ struct mtk_mmsys_routes { };
struct mtk_mmsys_driver_data {
- const resource_size_t io_start; const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; };
+struct mtk_mmsys_match_data {
- unsigned short num_drv_data;
- const struct mtk_mmsys_driver_data *drv_data[];
+};
- /*
- Routes in mt8173, mt2701, mt2712 are different. That means
- in the same register address, it controls different
input/output diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4bba275e235a..cff5c9adbf46 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER1,
- DDP_COMPONENT_DP_INTF0,
- DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1,
- DDP_COMPONENT_DSC0,
- DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, DDP_COMPONENT_DSI3, DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_MERGE0,
- DDP_COMPONENT_MERGE1,
- DDP_COMPONENT_MERGE2,
- DDP_COMPONENT_MERGE3,
- DDP_COMPONENT_MERGE4,
- DDP_COMPONENT_MERGE5, DDP_COMPONENT_OD0, DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0,
c-- Jason-JH Lin jason-jh.lin@mediatek.com