Re: [PATCH V12 06/24] LoongArch: Add writecombine support for drm

在2022年6月1日六月 上午10:59，Huacai Chen写道：

LoongArch maintains cache coherency in hardware, but its WUC attribute (Weak-ordered UnCached, which is similar to WC) is out of the scope of cache coherency machanism. This means WUC can only used for write-only memory regions.

Cc: Daniel Vetter daniel@ffwll.ch Cc: dri-devel@lists.freedesktop.org Reviewed-by: WANG Xuerui git@xen0n.name Signed-off-by: Huacai Chen chenhuacai@loongson.cn

Reviewed-by: Jiaxun Yang jiaxun.yang@flygoat.com

Can still remember painful experiences on poke with WC on LS3B1500 + Polaris. Glad to see that WC is flawless this time.

Thanks.

---

drivers/gpu/drm/drm_vm.c | 2 +- drivers/gpu/drm/ttm/ttm_module.c | 2 +- include/drm/drm_cache.h | 8 ++++++++ 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index e957d4851dc0..f024dc93939e 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -69,7 +69,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map, pgprot_t tmp = vm_get_page_prot(vma->vm_flags);

#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \

• defined(__mips__)

• defined(__mips__) || defined(__loongarch__) if (map->type == _DRM_REGISTERS && !(map->flags &

_DRM_WRITE_COMBINING)) tmp = pgprot_noncached(tmp); else diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index a3ad7c9736ec..b3fffe7b5062 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -74,7 +74,7 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) #endif /* CONFIG_UML */ #endif /* __i386__ || __x86_64__ */ #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \

• defined(__powerpc__) || defined(__mips__)

• defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) if (caching == ttm_write_combined) tmp = pgprot_writecombine(tmp); else

diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 22deb216b59c..08e0e3ffad13 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -67,6 +67,14 @@ static inline bool drm_arch_can_wc_memory(void) * optimization entirely for ARM and arm64. */ return false; +#elif defined(CONFIG_LOONGARCH)

• /*

• * LoongArch maintains cache coherency in hardware, but its WUC 
  

attribute

• * (Weak-ordered UnCached, which is similar to WC) is out of the 
  

scope of

• * cache coherency machanism. This means WUC can only used for 
  

write-only

• * memory regions.
  

• */
  

• return false;

#else return true;

#endif

2.27.0