This enables access to some additional counters beyond the aggregating A counters, adding a '3D' metric set configuration useful while profiling 3D rendering workloads.
Signed-off-by: Robert Bragg robert@sixbynine.org --- drivers/gpu/drm/i915/i915_drv.h | 7 + drivers/gpu/drm/i915/i915_oa_perf.c | 124 +++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 294 ++++++++++++++++++++++++++++++++---- include/uapi/drm/i915_drm.h | 2 + 4 files changed, 385 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3d8e4ed..1e65dc2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1564,6 +1564,13 @@ struct i915_virtual_gpu { bool active; };
+#ifdef CONFIG_PERF_EVENTS +struct i915_oa_reg { + u32 addr; + u32 value; +}; +#endif + struct drm_i915_private { struct drm_device *dev; struct kmem_cache *objects; diff --git a/drivers/gpu/drm/i915/i915_oa_perf.c b/drivers/gpu/drm/i915/i915_oa_perf.c index a1cf55f..d0e144c 100644 --- a/drivers/gpu/drm/i915/i915_oa_perf.c +++ b/drivers/gpu/drm/i915/i915_oa_perf.c @@ -23,6 +23,80 @@ static int hsw_perf_format_sizes[] = { 64 /* C4_B8_HSW */ };
+ +/* A generated mux config to select counters useful for profiling 3D + * workloads */ +static struct i915_oa_reg hsw_profile_3d_mux_config[] = { + + { 0x253A4, 0x01600000 }, + { 0x25440, 0x00100000 }, + { 0x25128, 0x00000000 }, + { 0x2691C, 0x00000800 }, + { 0x26AA0, 0x01500000 }, + { 0x26B9C, 0x00006000 }, + { 0x2791C, 0x00000800 }, + { 0x27AA0, 0x01500000 }, + { 0x27B9C, 0x00006000 }, + { 0x2641C, 0x00000400 }, + { 0x25380, 0x00000010 }, + { 0x2538C, 0x00000000 }, + { 0x25384, 0x0800AAAA }, + { 0x25400, 0x00000004 }, + { 0x2540C, 0x06029000 }, + { 0x25410, 0x00000002 }, + { 0x25404, 0x5C30FFFF }, + { 0x25100, 0x00000016 }, + { 0x25110, 0x00000400 }, + { 0x25104, 0x00000000 }, + { 0x26804, 0x00001211 }, + { 0x26884, 0x00000100 }, + { 0x26900, 0x00000002 }, + { 0x26908, 0x00700000 }, + { 0x26904, 0x00000000 }, + { 0x26984, 0x00001022 }, + { 0x26A04, 0x00000011 }, + { 0x26A80, 0x00000006 }, + { 0x26A88, 0x00000C02 }, + { 0x26A84, 0x00000000 }, + { 0x26B04, 0x00001000 }, + { 0x26B80, 0x00000002 }, + { 0x26B8C, 0x00000007 }, + { 0x26B84, 0x00000000 }, + { 0x27804, 0x00004844 }, + { 0x27884, 0x00000400 }, + { 0x27900, 0x00000002 }, + { 0x27908, 0x0E000000 }, + { 0x27904, 0x00000000 }, + { 0x27984, 0x00004088 }, + { 0x27A04, 0x00000044 }, + { 0x27A80, 0x00000006 }, + { 0x27A88, 0x00018040 }, + { 0x27A84, 0x00000000 }, + { 0x27B04, 0x00004000 }, + { 0x27B80, 0x00000002 }, + { 0x27B8C, 0x000000E0 }, + { 0x27B84, 0x00000000 }, + { 0x26104, 0x00002222 }, + { 0x26184, 0x0C006666 }, + { 0x26284, 0x04000000 }, + { 0x26304, 0x04000000 }, + { 0x26400, 0x00000002 }, + { 0x26410, 0x000000A0 }, + { 0x26404, 0x00000000 }, + { 0x25420, 0x04108020 }, + { 0x25424, 0x1284A420 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00042049 }, +}; + +/* A corresponding B counter configuration for profiling 3D workloads */ +static struct i915_oa_reg hsw_profile_3d_b_counter_config[] = { + { 0x2724, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2710, 0x00000000 }, +}; + static void forward_one_oa_snapshot_to_event(struct drm_i915_private *dev_priv, u8 *snapshot, struct perf_event *event) @@ -551,6 +625,19 @@ static void update_oacontrol(struct drm_i915_private *dev_priv) I915_WRITE(GEN7_OACONTROL, 0); }
+static void config_oa_regs(struct drm_i915_private *dev_priv, + struct i915_oa_reg *regs, + int n_regs) +{ + int i; + + for (i = 0; i < n_regs; i++) { + struct i915_oa_reg *reg = regs + i; + + I915_WRITE(reg->addr, reg->value); + } +} + static void i915_oa_event_start(struct perf_event *event, int flags) { struct drm_i915_private *dev_priv = @@ -571,22 +658,31 @@ static void i915_oa_event_start(struct perf_event *event, int flags) WARN_ONCE(I915_READ(GEN6_UCGCTL3) & GEN6_OACSUNIT_CLOCK_GATE_DISABLE, "disabled OA unit level clock gating will result in incorrect per-context OA counters");
- /* XXX: On Haswell, when threshold disable mode is desired, - * instead of setting the threshold enable to '0', we need to - * program it to '1' and set OASTARTTRIG1 bits 15:0 to 0 - * (threshold value of 0) - */ - I915_WRITE(OASTARTTRIG6, (OASTARTTRIG6_B4_TO_B7_THRESHOLD_ENABLE | - OASTARTTRIG6_B4_CUSTOM_EVENT_ENABLE)); - I915_WRITE(OASTARTTRIG5, 0); /* threshold value */ + I915_WRITE(GDT_CHICKEN_BITS, GT_NOA_ENABLE);
- I915_WRITE(OASTARTTRIG2, (OASTARTTRIG2_B0_TO_B3_THRESHOLD_ENABLE | - OASTARTTRIG2_B0_CUSTOM_EVENT_ENABLE)); - I915_WRITE(OASTARTTRIG1, 0); /* threshold value */ + if (dev_priv->oa_pmu.metrics_set == I915_OA_METRICS_SET_3D) { + config_oa_regs(dev_priv, hsw_profile_3d_mux_config, + ARRAY_SIZE(hsw_profile_3d_mux_config)); + config_oa_regs(dev_priv, hsw_profile_3d_b_counter_config, + ARRAY_SIZE(hsw_profile_3d_b_counter_config)); + } else { + /* XXX: On Haswell, when threshold disable mode is desired, + * instead of setting the threshold enable to '0', we need to + * program it to '1' and set OASTARTTRIG1 bits 15:0 to 0 + * (threshold value of 0) + */ + I915_WRITE(OASTARTTRIG6, (OASTARTTRIG6_THRESHOLD_ENABLE | + OASTARTTRIG6_EVENT_SELECT_4)); + I915_WRITE(OASTARTTRIG5, 0); /* threshold value */
- /* Setup B0 as the gpu clock counter... */ - I915_WRITE(OACEC0_0, OACEC0_0_B0_COMPARE_GREATER_OR_EQUAL); /* to 0 */ - I915_WRITE(OACEC0_1, 0xfffe); /* Select NOA[0] */ + I915_WRITE(OASTARTTRIG2, (OASTARTTRIG2_THRESHOLD_ENABLE | + OASTARTTRIG2_EVENT_SELECT_0)); + I915_WRITE(OASTARTTRIG1, 0); /* threshold value */ + + /* Setup B0 as the gpu clock counter... */ + I915_WRITE(OACEC0_0, OACEC_COMPARE_GREATER_OR_EQUAL); /* to 0 */ + I915_WRITE(OACEC0_1, 0xfffe); /* Select NOA[0] */ + }
spin_lock_irqsave(&dev_priv->oa_pmu.lock, lock_flags);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9e427cc..d94932a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -532,34 +532,6 @@ #define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1) #define GEN7_OACONTROL_ENABLE (1<<0)
-#define OASTARTTRIG5 0x02720 -#define OASTARTTRIG5_THRESHOLD_VALUE_MASK 0xffff - -#define OASTARTTRIG6 0x02724 -#define OASTARTTRIG6_B4_TO_B7_THRESHOLD_ENABLE (1<<23) -#define OASTARTTRIG6_B4_CUSTOM_EVENT_ENABLE (1<<28) - -#define OASTARTTRIG1 0x02710 -#define OASTARTTRIG1_THRESHOLD_VALUE_MASK 0xffff - -#define OASTARTTRIG2 0x02714 -#define OASTARTTRIG2_B0_TO_B3_THRESHOLD_ENABLE (1<<23) -#define OASTARTTRIG2_B0_CUSTOM_EVENT_ENABLE (1<<28) - -#define OACEC0_0 0x2770 -#define OACEC0_0_B0_COMPARE_ANY_EQUAL 0 -#define OACEC0_0_B0_COMPARE_OR 0 -#define OACEC0_0_B0_COMPARE_GREATER_THAN 1 -#define OACEC0_0_B0_COMPARE_EQUAL 2 -#define OACEC0_0_B0_COMPARE_GREATER_OR_EQUAL 3 -#define OACEC0_0_B0_COMPARE_LESS_THAN 4 -#define OACEC0_0_B0_COMPARE_NOT_EQUAL 5 -#define OACEC0_0_B0_COMPARE_LESS_OR_EQUAL 6 -#define OACEC0_0_B0_COMPARE_VALUE_MASK 0xffff -#define OACEC0_0_B0_COMPARE_VALUE_SHIFT 3 - -#define OACEC0_1 0x2774 - #define GEN7_OABUFFER 0x23B0 /* R/W */ #define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3) #define GEN7_OABUFFER_EDGE_TRIGGER (1<<2) @@ -584,6 +556,272 @@ #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 #define GEN7_OASTATUS2_GGTT 0x1
+#define GDT_CHICKEN_BITS 0x9840 +#define GT_NOA_ENABLE 0x00000080 + +/* + * OA Boolean state + */ + +#define OAREPORTTRIG1 0x2740 +#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG2 0x2744 +#define OAREPORTTRIG2_INVERT_A_0 (1<<0) +#define OAREPORTTRIG2_INVERT_A_1 (1<<1) +#define OAREPORTTRIG2_INVERT_A_2 (1<<2) +#define OAREPORTTRIG2_INVERT_A_3 (1<<3) +#define OAREPORTTRIG2_INVERT_A_4 (1<<4) +#define OAREPORTTRIG2_INVERT_A_5 (1<<5) +#define OAREPORTTRIG2_INVERT_A_6 (1<<6) +#define OAREPORTTRIG2_INVERT_A_7 (1<<7) +#define OAREPORTTRIG2_INVERT_A_8 (1<<8) +#define OAREPORTTRIG2_INVERT_A_9 (1<<9) +#define OAREPORTTRIG2_INVERT_A_10 (1<<10) +#define OAREPORTTRIG2_INVERT_A_11 (1<<11) +#define OAREPORTTRIG2_INVERT_A_12 (1<<12) +#define OAREPORTTRIG2_INVERT_A_13 (1<<13) +#define OAREPORTTRIG2_INVERT_A_14 (1<<14) +#define OAREPORTTRIG2_INVERT_A_15 (1<<15) +#define OAREPORTTRIG2_INVERT_B_0 (1<<16) +#define OAREPORTTRIG2_INVERT_B_1 (1<<17) +#define OAREPORTTRIG2_INVERT_B_2 (1<<18) +#define OAREPORTTRIG2_INVERT_B_3 (1<<19) +#define OAREPORTTRIG2_INVERT_C_0 (1<<20) +#define OAREPORTTRIG2_INVERT_C_1 (1<<21) +#define OAREPORTTRIG2_INVERT_D_0 (1<<22) +#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG3 0x2748 +#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG4 0x274c +#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OAREPORTTRIG5 0x2750 +#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG6 0x2754 +#define OAREPORTTRIG6_INVERT_A_0 (1<<0) +#define OAREPORTTRIG6_INVERT_A_1 (1<<1) +#define OAREPORTTRIG6_INVERT_A_2 (1<<2) +#define OAREPORTTRIG6_INVERT_A_3 (1<<3) +#define OAREPORTTRIG6_INVERT_A_4 (1<<4) +#define OAREPORTTRIG6_INVERT_A_5 (1<<5) +#define OAREPORTTRIG6_INVERT_A_6 (1<<6) +#define OAREPORTTRIG6_INVERT_A_7 (1<<7) +#define OAREPORTTRIG6_INVERT_A_8 (1<<8) +#define OAREPORTTRIG6_INVERT_A_9 (1<<9) +#define OAREPORTTRIG6_INVERT_A_10 (1<<10) +#define OAREPORTTRIG6_INVERT_A_11 (1<<11) +#define OAREPORTTRIG6_INVERT_A_12 (1<<12) +#define OAREPORTTRIG6_INVERT_A_13 (1<<13) +#define OAREPORTTRIG6_INVERT_A_14 (1<<14) +#define OAREPORTTRIG6_INVERT_A_15 (1<<15) +#define OAREPORTTRIG6_INVERT_B_0 (1<<16) +#define OAREPORTTRIG6_INVERT_B_1 (1<<17) +#define OAREPORTTRIG6_INVERT_B_2 (1<<18) +#define OAREPORTTRIG6_INVERT_B_3 (1<<19) +#define OAREPORTTRIG6_INVERT_C_0 (1<<20) +#define OAREPORTTRIG6_INVERT_C_1 (1<<21) +#define OAREPORTTRIG6_INVERT_D_0 (1<<22) +#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG7 0x2758 +#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG8 0x275c +#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 + +#define OASTARTTRIG1 0x2710 +#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 +#define OASTARTTRIG1_THRESHOLD_MASK 0xffff + +#define OASTARTTRIG2 0x2714 +#define OASTARTTRIG2_INVERT_A_0 (1<<0) +#define OASTARTTRIG2_INVERT_A_1 (1<<1) +#define OASTARTTRIG2_INVERT_A_2 (1<<2) +#define OASTARTTRIG2_INVERT_A_3 (1<<3) +#define OASTARTTRIG2_INVERT_A_4 (1<<4) +#define OASTARTTRIG2_INVERT_A_5 (1<<5) +#define OASTARTTRIG2_INVERT_A_6 (1<<6) +#define OASTARTTRIG2_INVERT_A_7 (1<<7) +#define OASTARTTRIG2_INVERT_A_8 (1<<8) +#define OASTARTTRIG2_INVERT_A_9 (1<<9) +#define OASTARTTRIG2_INVERT_A_10 (1<<10) +#define OASTARTTRIG2_INVERT_A_11 (1<<11) +#define OASTARTTRIG2_INVERT_A_12 (1<<12) +#define OASTARTTRIG2_INVERT_A_13 (1<<13) +#define OASTARTTRIG2_INVERT_A_14 (1<<14) +#define OASTARTTRIG2_INVERT_A_15 (1<<15) +#define OASTARTTRIG2_INVERT_B_0 (1<<16) +#define OASTARTTRIG2_INVERT_B_1 (1<<17) +#define OASTARTTRIG2_INVERT_B_2 (1<<18) +#define OASTARTTRIG2_INVERT_B_3 (1<<19) +#define OASTARTTRIG2_INVERT_C_0 (1<<20) +#define OASTARTTRIG2_INVERT_C_1 (1<<21) +#define OASTARTTRIG2_INVERT_D_0 (1<<22) +#define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24) +#define OASTARTTRIG2_EVENT_SELECT_0 (1<<28) +#define OASTARTTRIG2_EVENT_SELECT_1 (1<<29) +#define OASTARTTRIG2_EVENT_SELECT_2 (1<<30) +#define OASTARTTRIG2_EVENT_SELECT_3 (1<<31) + +#define OASTARTTRIG3 0x2718 +#define OASTARTTRIG3_NOA_SELECT_MASK 0xf +#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OASTARTTRIG4 0x271c +#define OASTARTTRIG4_NOA_SELECT_MASK 0xf +#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OASTARTTRIG5 0x2720 +#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 +#define OASTARTTRIG5_THRESHOLD_MASK 0xffff + +#define OASTARTTRIG6 0x2724 +#define OASTARTTRIG6_INVERT_A_0 (1<<0) +#define OASTARTTRIG6_INVERT_A_1 (1<<1) +#define OASTARTTRIG6_INVERT_A_2 (1<<2) +#define OASTARTTRIG6_INVERT_A_3 (1<<3) +#define OASTARTTRIG6_INVERT_A_4 (1<<4) +#define OASTARTTRIG6_INVERT_A_5 (1<<5) +#define OASTARTTRIG6_INVERT_A_6 (1<<6) +#define OASTARTTRIG6_INVERT_A_7 (1<<7) +#define OASTARTTRIG6_INVERT_A_8 (1<<8) +#define OASTARTTRIG6_INVERT_A_9 (1<<9) +#define OASTARTTRIG6_INVERT_A_10 (1<<10) +#define OASTARTTRIG6_INVERT_A_11 (1<<11) +#define OASTARTTRIG6_INVERT_A_12 (1<<12) +#define OASTARTTRIG6_INVERT_A_13 (1<<13) +#define OASTARTTRIG6_INVERT_A_14 (1<<14) +#define OASTARTTRIG6_INVERT_A_15 (1<<15) +#define OASTARTTRIG6_INVERT_B_0 (1<<16) +#define OASTARTTRIG6_INVERT_B_1 (1<<17) +#define OASTARTTRIG6_INVERT_B_2 (1<<18) +#define OASTARTTRIG6_INVERT_B_3 (1<<19) +#define OASTARTTRIG6_INVERT_C_0 (1<<20) +#define OASTARTTRIG6_INVERT_C_1 (1<<21) +#define OASTARTTRIG6_INVERT_D_0 (1<<22) +#define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24) +#define OASTARTTRIG6_EVENT_SELECT_4 (1<<28) +#define OASTARTTRIG6_EVENT_SELECT_5 (1<<29) +#define OASTARTTRIG6_EVENT_SELECT_6 (1<<30) +#define OASTARTTRIG6_EVENT_SELECT_7 (1<<31) + +#define OASTARTTRIG7 0x2728 +#define OASTARTTRIG7_NOA_SELECT_MASK 0xf +#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OASTARTTRIG8 0x272c +#define OASTARTTRIG8_NOA_SELECT_MASK 0xf +#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 + +/* CECX_0 */ +#define OACEC_COMPARE_LESS_OR_EQUAL 6 +#define OACEC_COMPARE_NOT_EQUAL 5 +#define OACEC_COMPARE_LESS_THAN 4 +#define OACEC_COMPARE_GREATER_OR_EQUAL 3 +#define OACEC_COMPARE_EQUAL 2 +#define OACEC_COMPARE_GREATER_THAN 1 +#define OACEC_COMPARE_ANY_EQUAL 0 + +#define OACEC_COMPARE_VALUE_MASK 0xffff +#define OACEC_COMPARE_VALUE_SHIFT 3 + +#define OACEC_SELECT_NOA (0<<19) +#define OACEC_SELECT_PREV (1<<19) +#define OACEC_SELECT_BOOLEAN (2<<19) + +/* CECX_1 */ +#define OACEC_MASK_MASK 0xffff +#define OACEC_CONSIDERATIONS_MASK 0xffff +#define OACEC_CONSIDERATIONS_SHIFT 16 + +#define OACEC0_0 0x2770 +#define OACEC0_1 0x2774 +#define OACEC1_0 0x2778 +#define OACEC1_1 0x277c +#define OACEC2_0 0x2780 +#define OACEC2_1 0x2784 +#define OACEC3_0 0x2788 +#define OACEC3_1 0x278c +#define OACEC4_0 0x2790 +#define OACEC4_1 0x2794 +#define OACEC5_0 0x2798 +#define OACEC5_1 0x279c +#define OACEC6_0 0x27a0 +#define OACEC6_1 0x27a4 +#define OACEC7_0 0x27a8 +#define OACEC7_1 0x27ac + + #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index f78f232..7aa1d33 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -71,6 +71,8 @@ #define I915_OA_FORMAT_B4_C8_A16_HSW 6 #define I915_OA_FORMAT_C4_B8_HSW 7
+#define I915_OA_METRICS_SET_3D 1 + #define I915_OA_ATTR_SIZE_VER0 32 /* sizeof first published struct */
typedef struct _drm_i915_oa_attr {