From: Xiubin Zhang zhangxiubin1@huawei.com
Modfiy mipi dsi lanes to improve HDMI compatibility.
Signed-off-by: Xiubin Zhang zhangxiubin1@huawei.com Signed-off-by: Liuyao An anliuyao@huawei.com Signed-off-by: Mauro Carvalho Chehab mchehab+huawei@kernel.org --- drivers/staging/hikey9xx/gpu/dw_drm_dsi.c | 24 ++++++++++++------- drivers/staging/hikey9xx/gpu/hdmi/adv7535.c | 4 ---- .../staging/hikey9xx/gpu/kirin970_dpe_reg.h | 1 + 3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/hikey9xx/gpu/dw_drm_dsi.c b/drivers/staging/hikey9xx/gpu/dw_drm_dsi.c index e87363ab7373..2ba94fa15d0f 100644 --- a/drivers/staging/hikey9xx/gpu/dw_drm_dsi.c +++ b/drivers/staging/hikey9xx/gpu/dw_drm_dsi.c @@ -359,7 +359,10 @@ static void get_dsi_dphy_ctrl(struct dw_dsi *dsi, if (bpp < 0) return;
- dsi->client[id].lanes = 4; + if (mode->clock > 80000) + dsi->client[id].lanes = 4; + else + dsi->client[id].lanes = 3;
if (dsi->client[id].phy_clock) dphy_req_kHz = dsi->client[id].phy_clock; @@ -935,8 +938,7 @@ static void mipi_config_dphy_spec1v2_parameter(struct dw_dsi *dsi, char __iomem u32 lanes;
lanes = dsi->client[dsi->cur_client].lanes - 1; - - for (i = 0; i <= (lanes+1); i++) { + for (i = 0; i <= (lanes + 1); i++) { //Lane Transmission Property addr = MIPIDSI_PHY_TST_LANE_TRANSMISSION_PROPERTY + (i << 5); dsi_phy_tst_set(mipi_dsi_base, addr, 0x43); @@ -960,10 +962,12 @@ static void mipi_config_dphy_spec1v2_parameter(struct dw_dsi *dsi, char __iomem //clock lane timing ctrl - t_hs_trial dsi_phy_tst_set(mipi_dsi_base, MIPIDSI_PHY_TST_CLK_TRAIL, DSS_REDUCE(dsi->phy.clk_t_hs_trial));
- for (i = 0; i <= (lanes + 1); i++) { - if (i == 2) { + for (i = 0; i <= 4; i++) { + if (lanes == 2 && i == 1) /*init mipi dsi 3 lanes shoud skip lane3*/ + i++; + + if (i == 2) /* skip clock lane*/ i++; //addr: lane0:0x60; lane1:0x80; lane2:0xC0; lane3:0xE0 - }
//data lane pre_delay addr = MIPIDSI_PHY_TST_DATA_PRE_DELAY + (i << 5); @@ -1019,6 +1023,9 @@ static void dsi_mipi_init(struct dw_dsi *dsi, char __iomem *mipi_dsi_base) dss_rect_t rect; u32 cmp_stopstate_val = 0; u32 lanes; +#if !defined (CONFIG_HISI_FB_970) + int i = 0; +#endif
WARN_ON(!dsi); WARN_ON(!mipi_dsi_base); @@ -1132,7 +1139,7 @@ static void dsi_mipi_init(struct dw_dsi *dsi, char __iomem *mipi_dsi_base) /* clock lane timing ctrl - t_hs_trial*/ dsi_phy_tst_set(mipi_dsi_base, 0x25, dsi->phy.clk_t_hs_trial);
- for (int i = 0; i <= lanes; i++) { + for (i = 0; i <= lanes; i++) { /* data lane pre_delay*/ tmp = 0x30 + (i << 4); dsi_phy_tst_set(mipi_dsi_base, tmp, DSS_REDUCE(dsi->phy.data_pre_delay)); @@ -1361,10 +1368,9 @@ static int mipi_dsi_on_sub1(struct dw_dsi *dsi, char __iomem *mipi_dsi_base)
static int mipi_dsi_on_sub2(struct dw_dsi *dsi, char __iomem *mipi_dsi_base) { + u64 pctrl_dphytx_stopcnt = 0; WARN_ON(!mipi_dsi_base); - u64 pctrl_dphytx_stopcnt;
- pctrl_dphytx_stopcnt = 0; /* switch to video mode */ set_reg(mipi_dsi_base + MIPIDSI_MODE_CFG_OFFSET, 0x0, 1, 0);
diff --git a/drivers/staging/hikey9xx/gpu/hdmi/adv7535.c b/drivers/staging/hikey9xx/gpu/hdmi/adv7535.c index 0343b2cd4c45..a21a8f8b917e 100644 --- a/drivers/staging/hikey9xx/gpu/hdmi/adv7535.c +++ b/drivers/staging/hikey9xx/gpu/hdmi/adv7535.c @@ -939,14 +939,10 @@ static void adv7511_mode_set(struct adv7511 *adv7511, struct mipi_dsi_device *dsi = adv7511->dsi; int lanes, ret;
-#if defined(CONFIG_HISI_FB_970) - lanes = 4; -#else if (adj_mode->clock > 80000) lanes = 4; else lanes = 3; -#endif
if (lanes != dsi->lanes) { mipi_dsi_detach(dsi); diff --git a/drivers/staging/hikey9xx/gpu/kirin970_dpe_reg.h b/drivers/staging/hikey9xx/gpu/kirin970_dpe_reg.h index 867266073bc0..5c2ddcf01b26 100644 --- a/drivers/staging/hikey9xx/gpu/kirin970_dpe_reg.h +++ b/drivers/staging/hikey9xx/gpu/kirin970_dpe_reg.h @@ -449,6 +449,7 @@ enum dss_chn_module { MODULE_SCL_LUT, MODULE_ARSR2P, MODULE_ARSR2P_LUT, + MODULE_POST_CLIP_ES, MODULE_POST_CLIP, MODULE_PCSC, MODULE_CSC,