Hi,
On 15-01-19 15:55, Ville Syrjälä wrote:
On Sat, Dec 01, 2018 at 12:31:46PM +0100, Hans de Goede wrote:
The display engine has 2 dithering enable bits which both need to be set for dithering to happen, 1 in the PIPECONF register which is taken care of by i9xx_set_pipeconf() and a second bit at the encoder level.
The dsi code was not setting the encoder level dithering enable bit causing dithering to be disabled, this commit fixes this.
Signed-off-by: Hans de Goede hdegoede@redhat.com
drivers/gpu/drm/i915/vlv_dsi.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index c10def5efa22..c21cbfa9653c 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -711,6 +711,10 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, LANE_CONFIGURATION_DUAL_LINK_B : LANE_CONFIGURATION_DUAL_LINK_A; }
if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)temp |= DITHERING_ENABLE;The docs say this was only made to work in C0 stepping. Not sure any BYT-Ts were ever shipped with B2/3, nor am I sure if setting the bit would have any effect there. IMO let's just set the bit and hope for the best.
Reviewed-by: Ville Syrjälä ville.syrjala@linux.intel.com
Thank you, I've pushed patches 1 and 2 of this series to dinq.
Regards,
Hans