09.10.2014, 21:42, "Christian König" christian.koenig@amd.com:
Hi Alexander,
in the ring test we write the value 0xDEADBEEF and 0xCAFEDEAD into registers, not VRAM.
And the register bar shouldn't be accessed write combined, cause that could lead to a couple of ordering problems. Why do you think the access is done write combined?
Because there is this code in r600_dma_ring_test(): void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
And vram_scratch is allocated in r600_vram_scratch_init() with domain RADEON_GEM_DOMAIN_VRAM which implies write-combining. I assumed that this means it points to the video memory.
Also when I look at page table attributes I can see that it is indeed mapped as write-combining. In this test only "rdev->rmmio" area was mapped as UC (the one where radeon_ring_commit() writes to to start the execution).
For VRAM it is true that we have a couple of different caches between the CPU and the actually memory, which need to be flushed explicitly if you want to see a value written by the GPU.
Then maybe such a flush is what I need. How do I put it in the instruction ring buffer?