https://bugzilla.kernel.org/show_bug.cgi?id=71891
--- Comment #35 from Dieter Nützel Dieter@nuetzel-hh.de --- (In reply to Alex Deucher from comment #33)
I wonder if UVD uses the reference clock directly, or if it uses xclk. If it uses xclk, they may explain the problems. Can you post your dmesg output with this patch applied?
Here is mine (with latest stuff from Christian):
[ 11.159443] [drm] initializing kernel modesetting (RV730 0x1002:0x9495 0x174B:0x0028).
[ 11.257005] [drm] ref: 2700, xclk: 2700
[ 11.263794] radeon 0000:01:00.0: WB disabled <--- Is this intended?
01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] RV730 [Radeon HD 4600 AGP Series] (prog-if 00 [VGA controller]) Subsystem: PC Partner Limited / Sapphire Technology Radeon HD 4650 AGP DDR2 Flags: bus master, 66MHz, medium devsel, latency 32, IRQ 16 Memory at c0000000 (32-bit, prefetchable) [size=256M] I/O ports at a800 [size=256] Memory at dfdf0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at dfdc0000 [disabled] [size=128K] Capabilities: [50] Power Management version 3 Capabilities: [58] AGP version 3.0 Kernel driver in use: radeon Kernel modules: radeon