15 Apr
2016
15 Apr
'16
10:34 p.m.
On 03/23, Maxime Ripard wrote:
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring robh@kernel.org Acked-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
Acked-by: Stephen Boyd sboyd@codeaurora.org
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