Hi, Jitao:
Jitao Shi jitao.shi@mediatek.com 於 2021年9月16日 週四 上午6:31寫道:
Some dsi devices require the packets on lanes aligned at the end, or the screen will shift or scroll.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org
Signed-off-by: Jitao Shi jitao.shi@mediatek.com
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 93b40c245f00..9d72e6dce0bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk;
u32 data_rate;
/* force dsi line end without dsi_null data */
bool hs_packet_end_aligned; unsigned long mode_flags; enum mipi_dsi_pixel_format format;
@@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); }
if (dsi->hs_packet_end_aligned) {
horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2;
horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
}
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
@@ -793,6 +802,7 @@ static int mtk_dsi_host_attach(struct mipi_dsi_host *host, dsi->lanes = device->lanes; dsi->format = device->format; dsi->mode_flags = device->mode_flags;
dsi->hs_packet_end_aligned = device->hs_packet_end_aligned; return 0;
}
2.25.1