Re: [PATCH v4, 1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11

Il 11/04/22 04:31, xinlei.lee@mediatek.com ha scritto:

From: Jitao Shi jitao.shi@mediatek.com

Old sequence:

1. Pull the MIPI signal high
2. Delay & Dsi_reset
3. Set the dsi timing register
4. dsi clk & lanes leave ulp mode and enter hs mode

The sequence after patching is:

1. Set the dsi timing register
2. Pull the MIPI signal high
3. Delay & Dsi_reset
4. dsi clk & lanes leave ulp mode and enter hs mode

Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")

Signed-off-by: Jitao Shi jitao.shi@mediatek.com Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com

Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com